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JPS54142025A - Address system - Google Patents

Address system

Info

Publication number
JPS54142025A
JPS54142025A JP4930978A JP4930978A JPS54142025A JP S54142025 A JPS54142025 A JP S54142025A JP 4930978 A JP4930978 A JP 4930978A JP 4930978 A JP4930978 A JP 4930978A JP S54142025 A JPS54142025 A JP S54142025A
Authority
JP
Japan
Prior art keywords
highest
firmware
address
rank bit
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4930978A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4930978A priority Critical patent/JPS54142025A/en
Publication of JPS54142025A publication Critical patent/JPS54142025A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To secure a control for both memories of the software and firmware via the same control circuit and thus to simplify the control by turning the highest-rank bit of the memory address to ''1'' at the starting time of the firmware. CONSTITUTION:The circuit consists of FF11 which is set at the power ON time and reset by the firmware and OR gate 12 which delivers the highest-rank bit of the address when FF11 is set with the output of FF11 plus the highest-rank bit giving an access to the memory used as the input. If the address supplied at the power ON time is 16 bits, the highest-rank bit becomes ''1'' thus to show output address 32K. Accordingly, an access is given from the firmware area.
JP4930978A 1978-04-27 1978-04-27 Address system Pending JPS54142025A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4930978A JPS54142025A (en) 1978-04-27 1978-04-27 Address system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4930978A JPS54142025A (en) 1978-04-27 1978-04-27 Address system

Publications (1)

Publication Number Publication Date
JPS54142025A true JPS54142025A (en) 1979-11-05

Family

ID=12827339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4930978A Pending JPS54142025A (en) 1978-04-27 1978-04-27 Address system

Country Status (1)

Country Link
JP (1) JPS54142025A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0366458A2 (en) * 1988-10-26 1990-05-02 Nec Corporation Data processing system wherein a simple peripheral control arrangement enables a CPU to access an enlarged address area

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0366458A2 (en) * 1988-10-26 1990-05-02 Nec Corporation Data processing system wherein a simple peripheral control arrangement enables a CPU to access an enlarged address area

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