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JPS54148336A - Information processor - Google Patents

Information processor

Info

Publication number
JPS54148336A
JPS54148336A JP5634978A JP5634978A JPS54148336A JP S54148336 A JPS54148336 A JP S54148336A JP 5634978 A JP5634978 A JP 5634978A JP 5634978 A JP5634978 A JP 5634978A JP S54148336 A JPS54148336 A JP S54148336A
Authority
JP
Japan
Prior art keywords
memory
unit
main memory
information processor
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5634978A
Other languages
Japanese (ja)
Inventor
Kazuhisa Genma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5634978A priority Critical patent/JPS54148336A/en
Publication of JPS54148336A publication Critical patent/JPS54148336A/en
Pending legal-status Critical Current

Links

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To eliminate the data queuing time of the arithmetic control unit and to shorten the access start of the subsequent memory unit for the control of the block transfer control of the main memory and the buffer for the information processor containing the high-speed buffer memory, and thus to enhance the performance of the information processor.
CONSTITUTION: The information processor contains main memory 1 to store the order and the data plus buffer memory 9 to memorized part of the information stored in memory 1. Then the fixed amount of the data is read out from memory 1 to be divided into plural partial data and then written into memory 9 in sequence through main memory control unit 27. In addition to such unit 27, buffer memory control unit 22 is provided. Main memory read register 4 and 5 are installed to unit 27 with connection of arithmetic unit 12 to unit 22. Then such function is provided via unit 22 that the transfer sequence of plural partial data is altered in relation to the address within the block of the main memory access address.
COPYRIGHT: (C)1979,JPO&Japio
JP5634978A 1978-05-12 1978-05-12 Information processor Pending JPS54148336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5634978A JPS54148336A (en) 1978-05-12 1978-05-12 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5634978A JPS54148336A (en) 1978-05-12 1978-05-12 Information processor

Publications (1)

Publication Number Publication Date
JPS54148336A true JPS54148336A (en) 1979-11-20

Family

ID=13024744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5634978A Pending JPS54148336A (en) 1978-05-12 1978-05-12 Information processor

Country Status (1)

Country Link
JP (1) JPS54148336A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4989447A (en) * 1972-12-04 1974-08-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4989447A (en) * 1972-12-04 1974-08-27

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