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JPS54128636A - Cash memory control system - Google Patents

Cash memory control system

Info

Publication number
JPS54128636A
JPS54128636A JP3609278A JP3609278A JPS54128636A JP S54128636 A JPS54128636 A JP S54128636A JP 3609278 A JP3609278 A JP 3609278A JP 3609278 A JP3609278 A JP 3609278A JP S54128636 A JPS54128636 A JP S54128636A
Authority
JP
Japan
Prior art keywords
cpu
memory
comparator
output
cash
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3609278A
Other languages
Japanese (ja)
Inventor
Takashi Rokutanda
Yoshiyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3609278A priority Critical patent/JPS54128636A/en
Publication of JPS54128636A publication Critical patent/JPS54128636A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To perform good efficiency control, by providing the comparator representing whether the address data designated with CPU is in existing in the cash memory or not, and changing the handling of the cash memory based on the nature of the access request from CPU.
CONSTITUTION: In the data processing unit having the cash memory, the directory consisting of the high speed static RAM having the comparator 43 representing whether the address data designated with CPU is in existing in the memory or not. Further, the tag signal representing the input and output operation of CPU is fed to the directory, the output from the address register 41 is fed to the high speed static RAM 42, the output of RAM 42 and the bank designation field of the register 41 are compared by the comparator 43, the output of the comparator 43 is outputted via the multiplexer 45, the addrss designated is delivered from the main memory to CPU, and the block including the address data designated is transferred from the main memory to other memory.
COPYRIGHT: (C)1979,JPO&Japio
JP3609278A 1978-03-30 1978-03-30 Cash memory control system Pending JPS54128636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3609278A JPS54128636A (en) 1978-03-30 1978-03-30 Cash memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3609278A JPS54128636A (en) 1978-03-30 1978-03-30 Cash memory control system

Publications (1)

Publication Number Publication Date
JPS54128636A true JPS54128636A (en) 1979-10-05

Family

ID=12460102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3609278A Pending JPS54128636A (en) 1978-03-30 1978-03-30 Cash memory control system

Country Status (1)

Country Link
JP (1) JPS54128636A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5727336A (en) * 1980-04-25 1982-02-13 Data General Corp Data processing system
JPS6479843A (en) * 1987-09-22 1989-03-24 Nec Corp Information processor
DE3842100A1 (en) * 1988-01-21 1989-08-03 Mitsubishi Electric Corp CACHE SYSTEM AND CONTROL METHOD FOR THIS

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4989447A (en) * 1972-12-04 1974-08-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4989447A (en) * 1972-12-04 1974-08-27

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5727336A (en) * 1980-04-25 1982-02-13 Data General Corp Data processing system
JPH0578050B2 (en) * 1980-04-25 1993-10-28 Data General Corp
JPS6479843A (en) * 1987-09-22 1989-03-24 Nec Corp Information processor
DE3842100A1 (en) * 1988-01-21 1989-08-03 Mitsubishi Electric Corp CACHE SYSTEM AND CONTROL METHOD FOR THIS

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