JPS54100651A - Pulse-width/pusle-period converter circuit - Google Patents

Abstract

PURPOSE:To obtain an inexpensive and practical circuit by combining a dividing circuit and multiplier circuit together and by composing the divider circuit of a shift register. CONSTITUTION:In Nd divider circuit 14 composed of a shift register, input data Din supplied from input terminal 11 at frequency (f1) and timing of input clock CLin has its rise phase shifted at frequency f1/Nd 1/f1 by 1/f1, and is supplied to buffer memory 13 as read pulses phi1, phi2 of the pulse width multiplied by Nd, which are read out at the same timing as that when the input is divided. On the other hand, the output of Nd divider circuit 14 is multiplied by Nn to form output clock CLout. Then, the output is divided by Nn again in Nn divider circuit 16 to generate read-out pulses phi1, phi2 . Although the repetitive frequency of pulses phi1, phi2 is f1/Nd, the pulse width is Nd X Nn X 1/f1 and the rise phase is shifted Nd/Nn X 1/f1 by Nd/Nn X 1/f1. Input data Din from buffer memory 13 and input Data Din from the AND circuit are sampled through AND circuit 17-1, etc., and sent out from output Q of D-FF19 through the OR circuit.