JPH1196768A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase operation speed to operable timing speed by generating a series of operation timing including writing/reading in/from a memory circuit and a peripheral circuit based on a signal generated by dummy cell operation. SOLUTION: After receiving of return of an address selection signal TAD, a timing generating circuit TIM sends a writing/reading signal WO/RO to a sense circuit RWS. Writing/reading operation is performed for dummy cells D1-D4 by this signal, the timing generating circuit TIM turns off the writing/ reading signal WO/RO by 0 of return signals WD1-WD4 written in the dummy cells D1-D4 and 1 of return signals RD1RD4 of data read out from the dummy cells D1-D4. By returning off the reading/writing signal WO/RO, the address selection signal TAD is turned off, next, a pre-charge signal PRI of a data line is turned off, and a series of operation for the memory circuit is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a memory cell array.

[0002]

2. Description of the Related Art Heretofore, this kind of semiconductor integrated circuit has been widely used because it has a memory circuit comprising a memory cell array section and its peripheral circuits and a circuit of other functions. For example, FIG. 9 is a block diagram showing a configuration example of a memory circuit in an LCD driving IC which is one of conventional semiconductor integrated circuits. The memory circuit of this conventional semiconductor integrated circuit includes a memory cell array section MERRY, an X address decoder XAD, a Y address decoder YAD, a sense circuit RWS, and a timing generation circuit TIM.

In this conventional example of a memory circuit of a semiconductor integrated circuit, in a memory cell array portion and its peripheral circuit MA,
RRY, XAD, YAD, and RWS perform sequential write / read operations by a timing generation circuit TIM for which a designer has set fixed timing. That is, the timing circuit TIM receives the write / read selection signal, and determines the time when the X and Y address signals are determined.
A series of operation timings has been generated in consideration of the time when writing / reading is started and sufficient data writing / reading can be performed.

Further, as another example of a memory circuit of a conventional semiconductor integrated circuit, there is a semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 8-138383, for example. In brief, this semiconductor memory device is the same as a memory cell as a delay element for adjusting a write pulse generation timing to a write delay characteristic of a memory cell in a RAM module or the like mounted on a memory with a logic function. A characteristic compensating cell having the same configuration and having the same write delay characteristic is used, and a plurality of dummy cells having the same configuration as the memory cell are arranged around the characteristic compensating cell to form a dummy cell array.

By arranging the characteristic compensating cell or the dummy cell array in the layout area of the memory array or adjacent to the memory array, the write delay characteristic of the characteristic compensating cell including its peripheral portion can be reduced. Can be approximated. As a result, the timing margin of the write pulse can be reduced, and the cycle time of a RAM module mounted on the memory with a logic function can be shortened.

[0006]

A problem of the conventional semiconductor integrated circuit is that the operation speed of writing / reading is limited by the setting of a fixed timing and cannot be increased.

The reason is that, in a conventional memory circuit of a semiconductor integrated circuit, it is necessary to increase a fixed timing design margin in order to guarantee the operation under the worst condition.

Further, even when the timing is controlled by approximating the delay characteristic of the memory cell by the characteristic compensation cell or the dummy cell, the wiring resistance of the data line or the like varies due to a manufacturing process or the like, and each of the elements in the memory array section is varied. This is because it is necessary to add a fixed timing design margin in order to guarantee the operation of the memory cell.

Accordingly, it is an object of the present invention to eliminate the need for a fixed timing design margin in a memory circuit built in a semiconductor integrated circuit and to speed up the write / read operation.

[0010]

SUMMARY OF THE INVENTION Therefore, the present invention provides a semiconductor integrated circuit having a memory cell array portion formed by arranging static memory cells in a lattice pattern. A plurality of dummy cells respectively arranged at the corners, each connected to a data line for writing / reading and having a separate output terminal, and a write timing for each of the memory cells corresponding to a signal of each output terminal of each dummy cell. A timing generation circuit that generates a controlled write signal and generates a read signal in which the read timing for each of the memory cells is controlled in accordance with the read data from each of the dummy cells.

In addition, each of the dummy cells is initialized when not selected, and is selected at the time of writing to each of the memory cells, and the inverted data of the initialization data is simultaneously written to each of the dummy cells, and selected at the time of reading from each of the memory cells. Then, the respective initialization data are simultaneously read from the respective dummy cells.

Further, the write signal is inactivated in accordance with the coincidence signal of the signals at the respective output terminals, and the read signal is inactivated in accordance with the coincidence signal of the read data from each of the dummy cells. .

Further, data lines and word lines respectively connected to the dummy cells are connected to peripheral circuits equivalent to the peripheral circuits of the memory cell array section.

Further, the data lines and word lines respectively connected to the dummy cells have the same wiring capacitance, inter-line capacitance, and wiring resistance as the data lines and word lines in the memory cell array.

[0015]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a memory circuit portion in a semiconductor integrated circuit according to an embodiment of the present invention.
Referring to FIG. 1, the memory circuit in the semiconductor integrated circuit according to the present embodiment includes a memory cell array unit MARRY and dummy cells D1 to D4.
X address decoders XAD, DX1 to DX2, Y address decoders YAD, DY1 to DY4, and a sense circuit R
WS, DRW1 to DRW4 and a timing generation circuit TI
M.

FIG. 2 is a connection diagram showing a specific connection example between the data lines and the word lines of the memory cell array section arry and the dummy cells D1 to D4 in FIG. Referring to FIG. 2, load switch groups L1 and L3 are connected to the data lines of the dummy cells D1 and D2 as the line-to-line capacitive loads between the word lines and the data lines of the memory cell array section arry. I have. The word lines of the dummy cells D1 to D4 have a memory cell array section M between the dummy cells D1 and D2 and between the dummy cells D3 and D4.
Load switch groups L2 and L4 are connected as line capacitance loads between the data lines and the ARRY word lines in the same manner as the ARRY word lines.

FIG. 3 is a circuit diagram showing a specific example of the configuration of the memory cell array section arry in FIG. This memory cell array section MARRY is used in an LCD drive IC having a data display function, and has a display timing signal Tn.
, The data is separately output to the display output OUn. The basic memory cells are also connected to word line signals AD0 to ADn and write / read data lines RWD0 to RWDn, RWDB0 to RWDBn, respectively, and separately output data to output lines OU1 to OUn. I have.

FIG. 4 shows the dummy cells D1 to D in FIG.
4 is a circuit diagram illustrating a specific configuration example of FIG. These dummy cells Dn are exactly the same as the memory cells with respect to the data write / read function, and are connected to word lines DAn and data lines DDYn, DDYn. Also, a return signal WDn of data initialized by the dummy cell reset signal DRE and written in the dummy cell is separately output. Initialized by a dummy cell reset signal DRE from the timing generation circuit TIM at the time of non-selection, each dummy cell D1 to D4 selected at the time of writing to each memory cell.
, The inverted data of the initialization data is simultaneously written to each of the dummy cells D.
Each initialization data is simultaneously read from 1 to D4. In the present embodiment, the bit is set to "1" by initialization, "0" is written at the time of writing, and "1" is read at the time of reading. In addition, at least one of the dummy cells D1 to D4 is arranged to be opposite to the timing generation circuit TIM with the memory cell array unit MARY interposed therebetween.

FIG. 5 shows the Y address decoder DYn and the sense circuits DRW1 to DRW1 provided for the dummy cells in FIG.
FIG. 9 is a circuit diagram illustrating a specific configuration example of RW4. These Y address decoder DYn and sense circuits DRW1 to DRW4
Has the same internal configuration as the Y-address decoder YAD for the memory cell array unit MARRY and the circuit for each data line in the sense circuit RWS, and the data line precharge OFF signal PR output from the timing generation circuit TIM.
I, address selection signal TDA, write / read signal WO
/ RO and operate on each. At the same time, the signals read from the respective dummy cells D1 to D4 are returned and the signal RDn is returned to the timing generation circuit TIM.

FIG. 6 is a circuit diagram showing a specific configuration example of the X address decoders XAD and DX1 to DX2 in FIG. The X address decoder XAD provided for the memory cell array unit arry receives the word line signal ADn even if the X address signal XADn is input unless the address selection signal TAD from the timing generation circuit TIM is input.
Is not output. When the address selection signal TAD is sent, the X address decoders DX1 and DX2 provided for the dummy cells receive word line signals DA1 to DA1 for the dummy cells.
DA2 is automatically output.

FIG. 7 is a circuit diagram showing a specific configuration example of the timing generation circuit TIM in FIG. FIG.
Is a timing chart showing the operation of the timing generation circuit TIM. The function of the timing generation circuit TIM will be described with reference to FIG.

When the reset signal REST is "1", the timing generation circuit TIM sets each timing output signal to an initial state. The precharge OFF signal PRI, the write / read signal WO / RO, and the sense circuit reset signal SRE are set to "0", respectively, and the address selection signal TAD and the dummy cell reset signal DRE are set to "1".

Thereafter, a write / read selection signal CW / C
When R changes to “1”, the precharge OFF signal PR
I changes to "1", the return signal PRID changes the address selection signal TAD to "0", and the return signal TAD
D causes the write / read signal WO / RO to change to "1",
Become active.

Due to the active change of the write / read signal WO / RO, a write / read operation is performed on the dummy cells D1 to D4, and "0" of the return signals WD1 to WD4 of the data written in the dummy cells D1 to D4 is obtained. Return signal R of data read from dummy cells D1 to D4
When "1" of D1 to RD4 is input, the write / read signal WO / RO becomes "0" and becomes inactive.

Due to the inactive change of the write / read signals WO / RO, their return signals WOD / RO
D becomes "0", the address selection signal TAD becomes "1", and the return signal TADD switches the precharge signal PRI of the data line to "0" to complete all operations.

As described above, the circuit configuration is such that the timing signal of the next operation is sequentially generated in response to the return of the timing signal of the previous operation.

Next, the operation of the memory circuit in the semiconductor integrated circuit of this embodiment will be described.

Referring to FIG. 1, for a memory circuit,
When the write / read selection signal CW / CR and the X address signal XADn and the Y address signal YADn are sent,
The timing generation circuit TIM sends a precharge OFF signal PRI for the data line to the sense circuit unit RWS.
In response to the return of this signal, the timing generation circuit TIM
Sends an address selection signal TAD to both X and Y address decoders. With this signal, the word line signals of the dummy cells D1 to D4 are simultaneously selected. Address selection signal T
In response to the return of AD, the timing generation circuit TIM sends the write / read signal WO / RO to the sense circuit RWS. With this signal, a write / read operation is performed on the dummy cell, and the return signals WD1 to WD4 of the data written in the dummy cells D1 to D4 are set to “0”.
The timing generation circuit TIM turns off the write / read signal WO / RO in response to "1" of the return signals RD1 to RD4 of the data read from the dummy cells D1 to D4.
When the write / read signal is turned off, the address selection signal TAD is turned off, then the precharge signal PRI of the data line is turned off, and a series of operations on the memory circuit is completed.

In the present embodiment, the case where the number of the memory cell array units MARRY is one has been described. However, as a modified example of the semiconductor integrated circuit of the present embodiment, there are a plurality of memory cell array units MARRY and one timing generation circuit. It is clear that a semiconductor integrated circuit controlled by the TIM is also possible.

[0030]

As described above, in the semiconductor integrated circuit according to the present invention, a series of operation timings including writing / reading for the built-in memory circuit and the peripheral circuit can be increased to a timing speed at which the operation can be performed. Has the effect.

The reason is that the dummy cells arranged at the four corners adjacent to the memory cell array are used,
Data writing / reading is performed from address selection of a dummy cell under the same conditions as a memory cell, and a series of operations including writing / reading for a memory circuit and a peripheral circuit are performed based on signals generated by the operation of the dummy cell. Because the timing is generated, the wiring resistance of the data line and the like varies due to the manufacturing process, and it is not necessary to add a fixed timing design margin to guarantee the operation of each memory cell in the memory array section. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a memory circuit unit in a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a connection diagram showing a specific connection example between a data line and a word line of a memory cell array unit and a dummy cell in FIG. 1;

FIG. 3 is a circuit diagram showing a specific configuration example of a memory cell array unit in FIG. 1;

FIG. 4 is a circuit diagram showing a specific configuration example of a dummy cell in FIG. 1;

5 is a circuit diagram showing a specific configuration example of a Y address decoder and a sense circuit provided for a dummy cell in FIG. 1;

FIG. 6 is a circuit diagram showing a specific configuration example of an X address decoder in FIG. 1;

FIG. 7 is a circuit diagram showing a specific configuration example of a timing generation circuit in FIG. 1;

FIG. 8 is a timing chart showing an operation of the timing generation circuit of FIG. 7;

FIG. 9 is a block diagram showing a memory circuit section in a conventional semiconductor integrated circuit.

[Explanation of symbols]

AD0 to ADn, DAn Word lines D1 to D4 Dummy cells DDYn, DDBYn, RWD0 to RWDn, RWDB
0 to RWDBn Data line DRE Dummy cell reset signal DRW1 to DRW4, RWS sense circuit DX1 to DX2, XAD X address decoder DY1 to DY4, YAD Y address decoder L1 to L4 Load switch group MARRY Memory cell array unit PRI Precharge OFF signal PRID, RD1 RD4, TADD, WD1 to WD
4, WOD / ROD return signal REST reset signal SRE sense circuit reset signal TAD address selection signal TIM timing generation circuit Tn display timing signal WO / RO write / read signal XADn X address signal YADn Y address signal

Claims (5)

[Claims] 1. A semiconductor integrated circuit having a memory cell array portion formed by arranging static memory cells in a lattice pattern, and arranged at four corners adjacent to the memory cell array portion for writing / reading. A plurality of dummy cells each connected to a data line and having a separate output terminal, and generating a write signal in which a write timing for each of the memory cells is controlled in accordance with a signal at each of the output terminals of each of the dummy cells; A semiconductor integrated circuit comprising: a timing generation circuit that generates a read signal in which read timing for each of the memory cells is controlled in accordance with read data from a dummy cell. 2. Each of the dummy cells is initialized when it is not selected, and is selected at the time of writing to each of the memory cells, and inverted data of the initialization data is simultaneously written to each of the dummy cells, and selected at the time of reading of each of the memory cells. 2. The semiconductor integrated circuit according to claim 1, wherein said initialization data is simultaneously read out from each of said dummy cells. 3. The write signal is inactivated in response to a coincidence signal of the signals at the respective output terminals, and the read signal is inactivated in response to a coincidence signal of read data from each of the dummy cells. The semiconductor integrated circuit according to claim 1. 4. The semiconductor integrated circuit according to claim 1, wherein data lines and word lines respectively connected to said dummy cells are connected to peripheral circuits equivalent to peripheral circuits of said memory cell array section. 5. A data line and a word line respectively connected to the dummy cell, wherein the data line and the word line of the memory cell array section have the same wiring capacity, the inter-line capacity,
5. The semiconductor integrated circuit according to claim 1, having a wiring resistance.