JPH1185549A - Register set circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it impossible to set the value lower than the minimumly necessary value. SOLUTION: This circuit is provided with an AND gate 21 for inverting and ANDing out respective data inputted to data input terminals (bit setting terminals) D3-D7 of a register 23 and an OR circuit for ORing this AND gate output and data to an input terminal D2 and outputting the result to the input terminal D2, and when the value higher than 08H is set to a data bus, the set value from the data bus B is inputted to the register 23 with no output from the AND gate 21. When values 07H-04H are set to the data bus, the AND gate 21 outputs '1' but the register 23 is set as the set values are. Further, when a value lower than 03H is set to the data bus, the AND gate 21 outputs '1' to the input terminal D2. Therefore, the minimumly necessary value is set to the register 23 in any case.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register set circuit in a digital circuit such as an ASIC.

[0002]

2. Description of the Related Art ASIC (Application Specific Integ
A rated circuit is a type of IC that performs a specific operation by combining a gate circuit such as an AND circuit or an OR circuit. For example, an PWM controlled inverter uses an ASIC to perform PWM modulation digitally. When an ASIC is used as an inverter, the ASIC is connected to a CPU and performs various operations according to a signal (a voltage signal having a voltage of 0 V and a power supply voltage of 1) sent from the CPU.

The ASIC uses a data bus (CPU) from the CPU.
CPU and ASIC to transmit data sent from
When the CPU receives a write signal for the data of an electric wire on the printer board connecting the printer, the data is taken into the internal circuit of the ASIC.

[0004] As shown in FIG.
A latch circuit such as an 8-bit register 3 is used to save the data written from the memory. The register is a type of a gate circuit, and outputs signals from the data input terminals D0 to D7 to the output terminals Q0 to Q7 only when a write signal comes to the gate terminal G. When the write signal is not received, the signal of the input terminals D0 to D7 written last is continuously output to the output terminals Q0 to Q7.

As described above, the ASIC is provided with versatility by performing the operation of the ASIC with the data written by the CPU.

[0006]

Some of the data set in the ASIC register include forgetting to set, noise, and AS.
If the correct value is not set due to a failure in mounting the IC or CPU to the printed circuit board, serious damage to the system may occur.

For example, in the case of an inverter, there is a setting of a dead time at the time of PWM modulation. If this value is set in a register smaller than the correct set value, the inverter main circuit element will be destroyed.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a register set circuit in which a value below a minimum necessary value is not set. It is intended for.

[0009]

According to the present invention, a power supply is connected to a lower input terminal of a register connected to a data bus which can set a minimum required value of a system, and the minimum required value is supplied to the register. It is characterized in that settings below the value are not made.

Alternatively, an AND circuit for inverting data input to each input terminal higher than a lower input terminal capable of setting a minimum value required by the system, and outputting each inverted signal as a logical product, A logical sum circuit for outputting the output of the logical product circuit and the data from the data bus to the predetermined lower input terminal to the predetermined lower input terminal by a logical sum, the minimum necessary value for the register It is characterized in that the following settings are not made.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment FIG. 1 shows a register set circuit according to a first embodiment. This circuit includes a data input terminal D0,
D1, D3 to D7 are connected to the data bus B and the data input terminals D
2 is connected to a power supply Vcc, a write signal W is input to a gate terminal G, and a circuit using a register value is connected to output terminals Q0 to Q7.

FIG. 1 shows an example in which the lowest value must be hexadecimal 04H. The voltage signals coming to the data input terminals D0 to D7 are 0 when the voltage is 0 V, and 1 when the power supply voltage Vcc. The represented signal is hexadecimal as a binary signal. That is, the voltage of each input terminal is D7 = 0, D6 =
0, D5 = 0, D4 = 0, D3 = 0, D2 = 1, D1 =
0, D0 = 0 state (00000100) is "04H"
And

According to this circuit, even if data is not set in the register due to a setting error or the like, the input terminal D
2 is connected to the power supply Vcc and is pulled up by the power supply voltage Vcc, so that a value “04H” that does not cause a failure in the system is set.

According to the above embodiment, the power supply V is used instead of connecting the data bus to the data input terminal D2 of the register.
Since cc is connected and pulled up, a value that does not damage the system can be set even if a correct value is not set in the register. Further, there is an advantage that it can be realized without adding a new gate circuit to the register.

Second Embodiment In the first embodiment, by pulling up the minimum required value in the register in advance, even if the correct value is not set in the register, the system may be damaged. Although no value is set, in the case of the example of FIG. 1 described above, a value that cannot be set occurs when an attempt is made to set a value of 04H or more. For example, 08H (000010
00), the input terminal D2 is connected to the power supply Vc.
c, and the signal of 1 is always set.
01100 (0CH) is set. When the variation of the set value is small, the method of the first embodiment is sufficient.

The second embodiment relates to a register set circuit which eliminates the drawbacks of the first embodiment and prevents setting below the minimum value.

FIG. 2 shows a register set circuit according to the second embodiment. In this circuit, data input terminals D0, D1, and D3 to D7 of a register 11 are connected to a data bus B, and data input terminals D3 to D3 are connected to a data input terminal D2.
7, the output signal of the AND circuit 21 with an inverter or the data for D2 from the data bus is input through the OR circuit 22 and the gate terminal. A write signal W is input to G, and a circuit using a register value is connected to output terminals Q0 to Q7.

The AND circuit 21 outputs an output 1 when all the data at the input terminals D3 to D7 of the register 11 are 0. Therefore, the D2 data from the data bus B and the OR circuit 22
Is the data of the input terminal D2.

08H (00001000) by the CPU
When the above values are set, all the data buses input from the data bus B to the input terminals D3 to D7 do not become 0, so that the AND circuit 21 does not operate and the output thereof becomes 0,
The set value set by the CPU is input to the register 23.

In addition, 07H (0000,0111) -0
When 4H (0000, 0100) is set, all data at the input terminals D3 to D7 become 0, so that AND
The circuit 21 operates and outputs a signal Y1. OR circuit 22
Is the signal Y1 and the data for D2 from the data bus B (=
Since the logical sum with (1) is obtained, the data input terminal D2 is set to 1 and the data as set is input to the register 23.

When a value equal to or less than 03H (0000, 0011) is set, the AND circuit 21 operates and the input Y1 of the OR circuit 22 becomes 1. Since the input Y1 and the data bus for D2 (= 0) from the data bus B are ORed,
Input terminal D2 is set to one. Thus, in any case, a value of 04H or more is set in the register. The relationship between the set value and the value set in the register is shown below.

Set value Register input value 00H 04H 01H 05H 02H 06H 03H 07H According to the second embodiment, a value equal to or less than 04H is not set, and a set value that cannot be set as in the first embodiment is set. There is nothing you can do.

[0023]

Since the present invention is constructed as described above, even if a program error, noise, assembly failure, etc. occur, and a set value lower than the correct set value is set in the register, the register has at least a minimum value. Since the required values are set, there is no serious damage to the system.

[Brief description of the drawings]

FIG. 1 is a register set circuit diagram according to a first embodiment;

FIG. 2 is a register set circuit diagram according to a second embodiment;

FIG. 3 is a register set circuit diagram according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CPU 2 ... ASIC 3, 11, 23 ... Register 21 ... AND circuit with an inverter on the input side 22 ... OR circuit B ... Data bus W ... Write signal D0-D7 ... Data input terminal Q0-Q7 ... Register output Terminal.

Claims (2)

[Claims] 1. A power supply is connected to a lower input terminal of a register connected to a data bus to which a minimum value required by a system can be set, so that the register is not set to a value lower than the minimum required value. A register set circuit comprising: 2. Inverting each data input to each input terminal of a register connected to a data bus, which is higher than a lower input terminal capable of setting a minimum value required by the system,
An AND circuit that outputs each inverted signal as a logical product, and outputs the logical product of the output of the logical product circuit and the data from the data bus to the predetermined lower input terminal to the predetermined lower input terminal. A register set circuit, comprising: an OR circuit, wherein the register is not set below a minimum required value.