JPH1168029A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shut off noise entering a semiconductor device from the front and back sides by providing connection members for electrically connecting a semiconductor chip mount which mounts a semiconductor chip with element- forming faces opposed and has a conductive shield layer at a part facing the chip to this layer. SOLUTION: A semiconductor chip 6 has electronic circuits on element- forming faces which are held a chip back face conductive layer 8 formed on the back of the chip 6 and conductive shield layer 16 formed, facing the chip 6, on a mounting face of an insulative board 2 and electrically connected to both the conductive layers 8, 16. The layer 8 mainly shuts off noise entering from the top face of the board 2 while the shield layer 16 mainly blocks noise entering from the bottom face, thus shutting off noise entering from the front and back sides of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of shielding a mounted semiconductor chip from radiation noise.

[0002]

2. Description of the Related Art Many conventional semiconductor devices are mounted on a lead frame and sealed with a resin. It is known that in such a semiconductor device, when a semiconductor element for processing a small signal, a semiconductor element having a high input impedance part, and the like are present, the performance is greatly affected by noise invading from the outside. Therefore, it is necessary to shield these elements from external noise.

A conventional technique for this purpose is disclosed, for example, in Japanese Patent Application Laid-Open No. 58-127338 (JP-B-63-64899).
No.) There is a structure disclosed in the gazette. As shown in FIG.
This structure includes a grounding electrode pattern 88 on an LSI chip mounting substrate 81 provided with a conductive pattern 82. The grounding electrode pattern 88 is provided so as to extend to a region on the substrate 81 facing the LSI chip 84 and is formed so wide that it does not come into contact with other conductive patterns 82. It is formed to cover. Also, since the ground electrode pattern 88 is electrically connected to the ground lead 87 of the LSI chip 84,
This is effective for blocking noise that enters from the mounting substrate side.

[0004]

The noise that enters a semiconductor device mounted on a substrate or the like includes noise that enters from the surface of an LSI chip on which an LSI element is formed, and LSI.
It can be divided into noise that enters from the back side of the chip via the semiconductor substrate.

In the structure disclosed in the above publication, noise that enters from the surface of the LSI chip is shielded by a grounding power supply pattern that extends and faces the LSI. On the other hand, since there is nothing in the semiconductor device for blocking noise that enters from the back side,
It reaches the semiconductor element portion of the I chip. For this reason, it causes a malfunction of a semiconductor element or the like that processes a small signal.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device capable of blocking both noises entering from the front side and the back side of the semiconductor device.

[0007]

Therefore, the present invention has the following configuration.

The semiconductor device according to the present invention has a chip surface conductive layer provided on an element forming surface, a chip back surface conductive layer formed on a chip back surface which is a back surface of the element forming surface, and a chip penetrating from the element forming surface side to the chip back surface side. A semiconductor chip having a via conductive portion for electrically connecting the chip rear surface conductive layer and the chip front surface conductive layer via a via connection hole to be formed, and a semiconductor chip mounted with the element forming surface facing the semiconductor chip and facing the semiconductor chip. A semiconductor chip mounting member having a shield conductive layer at a portion to be connected, and a connection member for electrically connecting the shield conductive layer and the chip surface conductive layer.

As described above, the semiconductor chip is mounted with the element forming surface facing the semiconductor chip mounting member. Therefore, the electronic circuit arranged on the element formation surface by the chip back surface conductive layer formed on the back surface of the semiconductor chip and the shield conductive layer formed on the mounting surface of the semiconductor mounting member and facing the semiconductor chip. Is sandwiched from both upper and lower sides. Therefore, by these upper and lower conductive layers,
Noise applied to the semiconductor chip from the front side and the back side of the semiconductor chip is cut off.

The semiconductor mounting member may be a lead frame. Further, it may be an insulating substrate.

As described above, when the semiconductor chip is mounted using the lead frame and the insulating substrate, high-density mounting is possible, so that the present invention can be realized while reducing the size of the semiconductor device.

In the semiconductor device according to the present invention, the insulating substrate includes a conductive layer on the back surface of the substrate, which is provided on the back surface of the mounting surface on which the semiconductor chip is mounted, and a through-hole penetrating from the mounting surface to the back surface of the substrate. A through-hole conductive portion for electrically connecting the conductive layer on the back surface of the substrate and the shield conductive layer via the conductive layer may be further provided.

As described above, the shield conductive layer provided on the insulating substrate is connected to the grounded rear surface conductive layer of the substrate through the through-hole conductive portion. For this reason, the impedance of the shield conductive layer can be reduced, so that it functions as a stable ground potential even for high-frequency signals. Further, noise is also blocked by the conductive layer on the back surface of the substrate, so that the shielding effect can be enhanced.

In the semiconductor device according to the present invention, the conductive layer on the back surface of the chip may be formed on the entire surface, and the via connection portion may be provided at a central portion of the semiconductor chip.

With this configuration, the via connection portion can be arranged at substantially the same distance from the chip back surface conductive layer in the square of the semiconductor chip, so that the impedance of the chip back surface conductive layer can be reduced as a whole. .

In the semiconductor device according to the present invention, the semiconductor chip may have a thickness of 30 μm or more.

If the thickness of the semiconductor chip can be reduced in this manner, formation of via connection holes and formation of via conductive portions become easy.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. In addition, the same portions are denoted by the same reference numerals, and overlapping description will be omitted.

In the embodiment, a light receiving element for receiving a signal light and converting it into an electric signal and a semiconductor chip having a built-in preamplifier for amplifying a signal from the light receiving element are provided on the same insulating substrate and the same lead. The case of mounting on a frame will be described.

(First Embodiment) FIG. 1 is a plan view showing an embodiment in which an insulating substrate is used as a semiconductor mounting member in a semiconductor device of the present invention. FIG. 2 shows FIG.
3 is a cross-sectional view taken along the line AA ′ of FIG. FIG.
5 is a top view of a semiconductor chip mounted on the semiconductor device of FIG. FIG. 4 is a top view of the insulating substrate on which the semiconductor device of FIG. 3 is mounted, and the cross section line AA ′ corresponds to the cross section of the insulating substrate shown in FIG.

1 and 2, a semiconductor device 1 of the present invention comprises an insulating substrate 2, a light receiving element 4, a semiconductor chip 6
And connecting members 18 and 20. The insulating substrate 2 has the shield conductive layer 16 and the wiring pattern 22 on the mounting surface, the light receiving element 4 has the connection pads 14 on the surface, and the semiconductor chip 6 has the chip surface conductive layer 8 and the connection pads 14 on the element formation surface. And a chip back surface conductive layer 16 on the chip back surface. On the surface of the insulating substrate 2, the chip surface conductive layer 12 and the connection pad 14 are aligned with the corresponding shield conductive layer 16 and wiring pattern 22, respectively, and the light receiving element 4, the semiconductor chip 6 and the substrate 2 connect the connection members 18, 20. The light receiving element 4 and the semiconductor chip 6 are flip-chip mounted with their surfaces facing the mounting surface of the substrate 2, sandwiched between the chip surface conductive layer 12 and the connection pads 14. In the embodiment shown in FIG. 1, the insulating substrate 2, the light receiving element 4, and the semiconductor chip 6 have a rectangular or square planar shape.

In FIG. 1, the conductive layers 16 and 22 on the insulating substrate 2 which are arranged below the light receiving element 4 and the semiconductor chip 6 and thus cannot be seen directly from the upper surface, and the conductive layers 16 and 22 on the light receiving element 4 and the semiconductor chip 6 The broken lines indicate the conductive layers 12 and 14 at the connection portions with the conductive layers 16 and 22.

As the light receiving element 4, a back-illuminated light receiving element is used for flip-chip mounting. As such an element, for example, there is a back illuminated photodiode element. This type of light receiving element receives the signal light 28 (FIG. 2) on the back surface of the light receiving element and outputs an electric signal converted from the signal light 28 from the front surface. Therefore, as shown in FIG. 2, connection wirings (not shown) for output signal lines, power supply lines, and the like of the light receiving element and connection pads 14 are arranged on the front surface side of the light receiving element. The connection pad 14 is connected to the shield conductive layer 16 and the wiring pattern 2 via the connection member 20.
2 is electrically connected.

The semiconductor chip 6 includes a current / voltage conversion preamplifier for converting a current signal from the light receiving element to a voltage signal, a signal processing circuit for processing a signal from the light receiving element or the preamplifier, and the like. The semiconductor elements constituting these circuits are formed on the chip surface, that is, on the element formation surface.

Since these circuits process, for example, amplify, small electric signals from the light receiving element 4, they are easily affected by noise entering from outside due to radiation or the like. In order to prevent this effect, a chip back surface conductive layer 8 is provided on the chip back surface. In other words, if the semiconductor chip 6 is mounted on the substrate 2 with the element formation surface facing the insulating substrate 2, the chip back surface conductive layer 8 covers the element formation surface from the back surface, and the chip back surface conductive layer 8 generates noise. Since it faces the surface where the noise enters, it is possible to prevent noise from entering from the back surface of the chip. Since the chip back surface conductive layer 8 can improve the shielding characteristics of external noise and does not require a process for forming a pattern, it is preferable that the chip back surface conductive layer 8 be formed so as to cover the entire back surface as shown in FIG. It is not limited to the one provided on the entire back surface of the chip.
May be formed so as to shield noise received by the semiconductor element on which the element formation surface is formed. For example, the chip back surface conductive layer 8 may be formed in a region on the back surface of the substrate that faces the element formation region 30 (FIG. 3) on the front surface with the substrate interposed therebetween. Note that the chip back surface conductive layer 8 is preferably formed by stacking a metal, for example, titanium (Ti) / gold (Au).

On the element formation surface, at least one chip surface conductive layer 12, elements forming a circuit such as a preamplifier, and a plurality of conductive layers 14, for example, a power line and a ground line connected to the circuit And signal pads for input lines, output lines, and the like. The conductive layers 12 and 14 are preferably formed in the same step during manufacturing.

In the embodiment shown in FIG. 2, on the light receiving element 4 and the semiconductor chip 6, a connection made of a conductor is made in contact with a conductive layer 12 for a ground electrode pad and a conductive layer 14 for a signal pad. Members 18 and 20 are arranged.
For this purpose, the connecting members 18 and 20 are connected to the conductive layers 12 and 14.
Is formed as a conductor having substantially the same height on a predetermined region, for example, a portion where the passivation film is opened, and when the light receiving element 4 and the semiconductor chip 6 are mounted on the substrate 2, the corresponding shield conductive layer 16 and wiring The shield conductive layer 16 and the wiring pattern 22
And the corresponding chip surface conductive layer 12 and connection pad 14 are electrically connected, and the light receiving element 4 and the semiconductor chip 6 are supported on the mounting surface of the insulating substrate 2. As the connection members 18 and 20, bump electrodes and the like can be applied. Bump electrodes are preferred because they are suitable for flip-chip mounting. As a method of forming a bump electrode, there are various methods using a copper bump, a gold bump, a solder bump, and the like. Further, the connection members 18 and 20 are not limited to the conductors formed on the light receiving element 4 and the semiconductor chip 6 like the bump electrodes.
A conductor provided on the substrate 22 may be used.

It is preferable that the connecting member 18 is disposed near the via conductive portion 10 in order to lower the impedance. For example, in FIG. 2, it is disposed immediately above the via connection unit 10. The number of connection members 18 and 20 for each wiring pattern 22 and shield conductive layer 16 is 1
The number is not limited to a single number, and a plurality of numbers may be provided according to required electric characteristics. Since the chip surface conductive layer 12 is electrically connected to the shield conductive layer 16 via the bump electrode 18 disposed on the ground electrode pad, the chip surface conductive layer 12 has the same potential, and is further connected to the ground potential during operation.

In the semiconductor chip 6 shown in FIG. 3, the element forming surface includes an element forming area 30 in which a passive element and an active element are formed in an area including a central portion of the semiconductor chip 6, and a signal pad in a peripheral area thereof. 14 in which a pad region is formed. A via conductive portion 10 for electrically connecting the chip rear surface conductive layer 8 and the chip front surface conductive layer 12 is provided at a central portion of the element formation region 30. As an example of a method for forming the via conductive portion 10, a via connection hole penetrating from the chip back surface side to the element formation surface side is formed in the semiconductor chip 6 by solution etching or dry etching using a reactive gas, and then the via connection hole is formed. There is a method in which selective plating is applied only to the inside, a conductor is buried in the connection hole to form a conductive portion, or a conductive layer is formed on the inner surface of the via connection hole. The conductive portion and the conductive layer are via conductive portions 10 provided from the chip back surface side to the element forming surface side through the substrate of the semiconductor chip 6, and electrically connect the chip back surface conductive layer 8 and the chip surface conductive layer 12. Connect to A plating metal formed by a plating step may be laminated on the chip back surface conductive layer 8. By doing so, the chip back surface conductive layer 8
The impedance can be further reduced.

Further, by reducing the substrate thickness of the semiconductor chip 6, the formation of the via connection hole and the via conductive portion 10
Is easy to form. As a range of such a substrate thickness, the thickness of the semiconductor chip is 30 [μm] or more and 300 [μm].
(Enter the upper limit.) The following range is suitable. Generally, the thickness of the semiconductor substrate is 400 [μm] to 500 [μm].
m]. This is because the thickness can be reduced to a lower limit at which the mechanical strength of the semiconductor substrate can be maintained, for example, about 30 [μm] for a GaAs semiconductor.

As shown in FIG. 3, when one via conductive portion 10 is provided in the semiconductor chip 6 in which the chip back surface conductive layer 8 is formed on the entire back surface, it is preferable to arrange the via conductive portion 10 in the center of the chip 6. . By doing so, the via conductive portion 10 can be arranged at a position where the impedance is averagely reduced with respect to the entire surface of the chip back surface conductive layer 8, so that a higher shielding effect can be obtained. Further, the position where the via conductive portion 10 is provided is not limited to the central portion of the chip, but may be provided in the pad region. Further, a plurality of via conductive portions 10 may be provided in both the central portion of the chip and the pad region to lower the impedance with respect to the conductive layer 8 on the back surface of the chip. Although the planar shape of the via conductive portion 10 is shown as a square in the embodiment shown in FIG. 3, it is not limited to this and may be rectangular, circular, elliptical or the like.

As shown in FIGS. 1 and 4, the insulating substrate 2 has a shield conductive layer 16 made of a conductor and a wiring pattern 22 on a mounting surface on which the light receiving element 4 and the semiconductor chip 6 are mounted. . The shield conductive layer 16 is preferably provided on a portion facing the semiconductor chip to be mounted, particularly, facing the element forming region 30 of the semiconductor chip. Furthermore, it is preferable to increase the area as long as electrical insulation from the wiring pattern 22 can be maintained. By doing so, the impedance of the shield conductive layer 16 can be reduced, and the path through which noise can enter can be cut off to enhance the shielding effect. For example, the shield conductive layer 16 may be provided on the front surface side of the substrate 2 on which the semiconductor chip 6 is mounted, covering the substrate 2 except for a portion facing a region on the semiconductor chip 6 where signal pads are provided. Good. In such an example, there is a conductive layer pattern shown in FIGS. In this way, even in a semiconductor device that processes a high-frequency signal of several hundred MHz to several GHz, the impedance can be reduced so that the extended shield conductive layer 16 functions sufficiently as a conductive layer for shielding. Therefore, the shield conductive layer 16 functions as a conductive layer having a stable ground potential, so that the effect of shielding external noise can be enhanced. Furthermore, if a conductive layer for shielding is provided on the surface of the light receiving element 4, the signal extraction surface side of the light receiving element 4 can also be shielded.

As the insulating substrate 2, a ceramic substrate formed of alumina ceramic or the like, a sapphire substrate, or the like can be used. The conductive layers 16 and 22 formed on the insulating substrate 2 can be made of, for example, a metal such as AgPt or Au.

In FIGS. 1 and 2, the light receiving element 4 is mounted with the signal light incident surface facing the signal incident surface, that is, with the surface of the element 4 facing the mounting surface of the ceramic substrate 2,
The semiconductor chip 6 is mounted with the element forming surface facing the mounting surface of the ceramic substrate 2. Signal transmission between the light receiving element 4 and the semiconductor chip 6 and the outside, signal transmission between the light receiving element 4 and the semiconductor chip 6, supply of power to the light receiving element 4 or the semiconductor chip 6, and the like are performed by a connection having a bump structure. This is performed via the members 18 and 20 and the wiring pattern 22. Therefore, the shield conductive layer 16 is also electrically connected to the chip surface conductive layer 12 through the connection member 18. Therefore, the shield conductive layer 16 and the chip back surface conductive layer 8 can be set to the same potential. Further, the chip back surface conductive layer 8 together with the shield conductive layer 16 can be kept at a sufficiently low impedance. Further, these conductive layers 8 and 16 can be set to the ground potential. After mounting, the light receiving element 4, the semiconductor chip 6, and the substrate 2
Is, for example, about 20 to 30 [μm].

As described above in detail, according to the configuration of the present invention, the electronic circuit arranged on the element forming surface of the semiconductor chip 6 is formed by the chip back conductive layer 8 formed on the back surface of the semiconductor chip 6 and The semiconductor chip 6 is mounted on the mounting surface of the substrate 2
The chip conductive layer 8 is sandwiched from both upper and lower surfaces by the shield conductive layer 16 formed opposite to the semiconductor chip, and the chip back conductive layer 8 and the shield conductive layer 16 are electrically connected. Therefore, the chip back surface conductive layer 8 blocks noise that mainly enters from the upper surface of the mounting substrate 2, and the shield conductive layer 16 blocks noise that mainly enters from the upper surface of the mounting substrate 2. Therefore, it is possible to obtain a good shield characteristic with respect to externally applied noise.

In the embodiment shown in FIG. 2, the insulating substrate 2
It further has a substrate backside conductive layer 24 formed on the entire backside of the substrate 2. The substrate backside conductive layer 24 is not limited to being provided on the entire surface, but is preferably formed on the entire surface, judging from the point that the shielding characteristics of external noise can be improved and the patterning of the backside conductive layer 24 becomes unnecessary. preferable.
The conductive layer 24 on the back surface of the substrate is electrically connected to the shield conductive layer 16 by a through-hole conductive portion 26 provided in the through-hole connection hole. For this purpose, the through-hole connection hole is formed from the back surface side of the substrate to the mounting surface side so as to penetrate the insulating substrate 2, and the inside of the through-hole connection hole is buried with a conductor or the inner surface of the through-hole connection hole. A conductive layer is formed on the through-hole conductive portion 26.
Becomes If a plurality of through-hole conductive portions 26 are provided, the impedance can be reduced, and the shielding effect can be enhanced. When a plurality of connection portions 26 are provided, the shield conductive layer 1
The connection portions 26 may be provided in a distributed manner according to the size of the connection portion 6. In the example shown in FIG. 4, nine through-hole conductive portions 26 are uniformly provided in a portion facing the semiconductor chip 6. In this way, the impedance of the shield conductive layer 16 can be reduced by the substrate backside conductive layer 24. The substrate backside conductive layer 24 itself has an effect of blocking noise that mainly enters the semiconductor chip 6 and the light receiving element 2 from the front side, that is, a shielding effect.

As described above, according to the structure of the present invention, the electronic circuit arranged on the element formation surface of the semiconductor chip 6 includes the chip back surface conductive layer 8 formed on the back surface of the semiconductor chip 6 and the insulating substrate 2. The shield conductive layer 1 formed on the mounting surface of the chip and electrically connected to the chip back surface conductive layer 8
6 sandwiched from both upper and lower surfaces. For this reason, it is possible to obtain good shielding characteristics with respect to noise given by radiation from the outside. In addition, the insulating substrate 2
The shield conductive layer 16 provided above is connected to a grounded substrate backside conductive layer 24 through a through-hole conductive portion 26. Therefore, the shield conductive layer 16 acts as a stable ground potential even for high-frequency signals,
The shielding effect can be enhanced.

(Second Embodiment) FIG. 5 is a plan view showing an embodiment in which a lead frame is used as a semiconductor mounting member in a semiconductor device according to the present invention. FIG.
FIG. 6 is a sectional view taken along line BB ′ of FIG. 5.

In this embodiment, the same light-receiving element 4, semiconductor chip 6, and connecting members 18 and 20 as those used in the first embodiment are used.
However, it is not limited to this.

5 and 6, a semiconductor device 50 of the present invention includes a lead frame 52, a light receiving element 4, a semiconductor chip 6, and connection members 18 and 20. The lead frame 52 has a shield conductive layer 54 and an internal lead 56 for wiring. On the lead frame 52, the chip surface conductive layer 12 and the connection pad 14 are aligned with the corresponding shield conductive layer 54 and wiring internal lead 56, respectively. The light receiving element 4 and the semiconductor chip 6 are flip-chip mounted with the connecting members 18 and 20 made of a conductor therebetween at the position (1). As a result, the connection members 18 and 20 electrically connect the shield conductive layer 54 and the internal lead 56 for wiring to the chip surface conductive layer 12 and the connection pad 14, and the light receiving element 4 and the semiconductor chip 6 are placed on the substrate 2. To support.

In FIG. 5, a portion of the lead frame 52 which is arranged below the light receiving element 4 and the semiconductor chip 6 and thus cannot be seen directly from the upper surface, for example, the conductive layer 54 and the internal leads 56, and the light receiving element 4 and the semiconductor chip 6, the conductive layers 12, 14 at the connection with the conductive layers 54, 56
Are indicated by broken lines.

The lead frame 52 includes a shield conductive layer 54 formed by using a conductor and the internal lead 5 for wiring.
6. The shield conductive layer 54 is preferably provided in a portion facing the semiconductor chip 6, particularly, facing the element forming region 30 (FIG. 3) of the mounted semiconductor chip 6. It is preferable to increase the area as long as proper insulation can be maintained. By doing so, the impedance of the shield conductive layer 54 can be reduced, and the path through which noise may enter can be cut off to enhance the shielding effect. For example, as shown in FIG. 5, the shield conductive layer 54 except for a portion facing the region where the signal pad of the semiconductor chip 6 is provided and a portion of another internal wiring lead.
May be provided. As in the case of the insulating substrate 2, in a semiconductor device for processing a high-frequency signal, the impedance is reduced so that the extending shield conductive layer 54 sufficiently functions as a conductive layer for shielding.

As shown in FIG. 5 and FIG.
Is mounted with its surface facing the mounting surface of the lead frame 52, that is, the device 4 is mounted with its surface facing the mounting surface of the lead frame 52, and the semiconductor chip 6 has the device forming surface mounted on the lead frame 52. It is mounted facing the surface. Signal transmission between the light receiving element 4 and the semiconductor chip 6 and the outside, transmission of a signal between the light receiving element 4 and the semiconductor chip 6, supply of power to the light receiving element 4 and the semiconductor chip 6, and the like are performed by a connection having a bump structure. Member 18,
20 and the internal lead 56 for wiring. Thereby, the shield conductive layer 54 is also electrically connected to the chip surface conductive layer 12 through the connection member 18. Therefore, the shield conductive layer 54 and the chip back surface conductive layer 8 can be set to the same potential. Also, the shield conductive layer 54
At the same time, the chip back surface conductive layer 8 can be kept at a sufficiently low impedance. Further, the shield conductive layer 54 and the chip back surface conductive layer 8 can be set to the ground potential. In addition,
The light receiving element 4 and the semiconductor chip 6 are connected to a lead frame 52.
After being mounted thereon, it is preferable to seal with a molding resin such as an epoxy resin.

As described above, according to the structure of the present invention, the electronic circuit disposed on the element forming surface of the semiconductor chip 6 includes the chip back conductive layer 8 on which the back surface of the semiconductor chip 6 is formed, and the lead frame 52. It is sandwiched from both upper and lower surfaces by a shield conductive layer 54 which forms a part and is electrically connected to the chip rear surface conductive layer 8. For this reason, the chip backside conductive layer 8 mainly blocks noise that mainly enters from the backside of the semiconductor chip 6, and the shield conductive layer 16 mainly blocks noise that mainly enters from the leadframe side of the semiconductor chip 6. . Therefore, it is possible to obtain a good shield characteristic with respect to externally applied noise.

In the first embodiment, the insulating substrate 2 is used. In the second embodiment, the lead frame 52 is used.
Are described above, but the semiconductor mounting member is not limited to these, and may be a flexible printed circuit board or the like.

[0046]

As described in detail above, according to the present invention, a chip back surface conductive layer provided on the back surface of a semiconductor chip and a shield conductive layer formed on a portion facing the element formation surface are provided. These conductive layers were electrically connected, and the semiconductor chip was sandwiched between the conductive layers from above and below. For this reason, it is possible to block both noises entering from the front side and the back side of the semiconductor device. Therefore, it is possible to provide a semiconductor device that can effectively shield circuits and signal wiring of a semiconductor chip that is sensitive to external electromagnetic noise.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device of the present invention when an insulating substrate is used.

FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1;

FIG. 3 is a top view of a semiconductor chip used in the semiconductor device of FIG. 1;

FIG. 4 is a top view of a ceramic substrate used for the semiconductor device of FIG. 1;

FIG. 5 is a plan view of a semiconductor device of the present invention when a lead frame is used.

FIG. 6 is a cross-sectional view taken along the line BB ′ of FIG. 5;

FIG. 7 is a plan view of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Insulating substrate, 4 ... Light receiving element, 6 ...
Semiconductor chip, 8: chip rear surface conductive layer, 10: connection pad, 12: chip surface conductive layer, 14: conductive layer, 16: shield conductive layer, 20: connection member, 22: wiring pattern,
24: Backside conductive layer 2, 26 ... Through-hole conductive portion,
28: signal light, 30: element formation region, 50: semiconductor device, 52: lead frame, 54: shield conductive layer, 5
6 ... Internal lead for wiring

Claims (6)

[Claims] 1. A chip surface conductive layer provided on an element formation surface, a chip back surface conductive layer formed on a chip back surface which is a back surface of the element formation surface, and a via connection penetrating from the element formation surface side to the chip back surface side. A semiconductor chip having a via conductive portion that electrically connects the chip rear surface conductive layer and the chip surface conductive layer via a hole, and the semiconductor chip is mounted with an element forming surface facing the semiconductor chip,
A semiconductor device comprising: a semiconductor chip mounting member having a shield conductive layer in a portion facing the semiconductor chip; and a connection member for electrically connecting the shield conductive layer and the chip surface conductive layer. 2. The semiconductor device according to claim 1, wherein the semiconductor mounting member is a lead frame. 3. The semiconductor device according to claim 1, wherein the semiconductor mounting member is an insulating substrate. 4. The substrate according to claim 1, wherein the insulating substrate is provided with a conductive layer provided on a back surface of the substrate which is a back surface of the mounting surface on which the semiconductor chip is mounted, and a through hole penetrating from the mounting surface to the back surface of the substrate. The semiconductor device according to claim 3, further comprising a through-hole conductive portion that electrically connects the back surface conductive layer and the shield conductive layer. 5. The semiconductor device according to claim 1, wherein the chip back surface conductive layer is formed on the entire surface, and the via connection portion is provided at a central portion of the semiconductor chip. Semiconductor device. 6. The semiconductor device according to claim 1, wherein the semiconductor chip has a thickness of 30 μm or more.