JPH1165623A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmable controller in which a data link request can be exactly processed, and the well-balanced processing of each interruption processing request can be attained. SOLUTION: When a data link request from an outside programmable controller(PC) is generated during the execution of a scan cycle by the PC, a reception handler successively sets the reception request in a reception queue, and when a data link request to the outside PC is requested from the PC, a transmission handler successively sets the transmission request in a transmission queue. Then, an OS(operating system) task controlling part executes a data link cycle for activating a responding task for processing the reception request set in the reception queue, and activating a transmitting task for processing the transmission request set in the transmission queue after the execution of the scan cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of causing a processor to repeatedly execute a scan cycle including an input scan, a program scan, and an output scan.
The present invention relates to a programmable controller that controls an externally connected control target.

[0002]

A processor of a programmable controller (hereinafter, referred to as a PC) requests a processing request of an interrupt program generated at regular time intervals during a repetitive execution of the above-described scan cycle, and a request for I / O. Various interrupt processing requests such as an O interrupt request and a data link request from another PC are received.

[0003] The priorities of these various interrupt processing requests are set in advance so as to cope with a conflict between interrupts. Then, when the processor receives the interrupt processing request, the processor compares the priority of the interrupt processing request with the priority of the currently performed processing task, and suspends the latter processing task if the former has a higher priority, The former processing task is executed preferentially.

However, in such an interrupt processing method, when a large number of interrupt processing requests having a high priority are continuously generated, the processing of interrupt processing requests having a low priority may be significantly delayed. And if the processing request has the purpose of simultaneously operating some functions,
There has been a problem that the achievement of the purpose cannot be guaranteed.

[0005] In order to solve such a problem, for example, as disclosed in Japanese Patent Laid-Open No. 3-282903, a task for processing a data link request is preferentially executed,
The other interrupt processing requests generated during the execution are put into an execution waiting state, and after the data link task is executed, the interrupt processing tasks in the execution waiting state are processed one by one for each type of interrupt. There is something.

However, in the above interrupt processing method, when a large number of data link requests are generated within a predetermined time, the processing of other interrupt processing requests is not started unless all generated data link requests are processed. become. In other words, this method assumes that the frequency of other processing requests is higher than the frequency of data link requests. If this assumption is not maintained, some processing requests may be delayed. Problem.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a programmable controller capable of reliably processing a data link request and processing each interrupt processing request in a well-balanced manner. It is in.

[0008]

According to the programmable controller of the present invention, when a data link request from an external device occurs during the execution of a scan cycle by the processor, the reception queue setting means receives the reception request. When a data link request to an external device occurs, the transmission queue setting means sequentially sets the transmission request in the transmission queue. The link cycle execution means activates a response task for processing the reception request set in the reception queue after the processor executes the scan cycle, and also executes a transmission task for processing the transmission request set in the transmission queue. Causes the processor to execute a data link cycle that activates

Accordingly, a data link request generated during the execution of a scan cycle is reliably processed after the execution of the scan cycle. Performance can be maintained. Conversely, other interrupt processing that occurs during the execution of the scan cycle is not hindered by the processing of the data link request, so that it is possible to improve the responsiveness to the interrupt processing that is desirably performed in real time. Interrupt processing requests can be processed in a well-balanced manner.

According to the second aspect of the present invention, the response task and the transmission task started by the link cycle execution means limit the number of reception requests and transmission requests to be processed by the processor at one start. By limiting the execution time of the data link cycle, each interrupt processing request can be processed in a more balanced manner.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 6 shows a programmable controller (hereinafter referred to as P) set in each slot of the rack.
C) and I / O configuration examples of other units. At the left end of the rack 1, a power supply unit 2 for supplying power to each unit is arranged. The PC 3 is arranged in the slot 0 adjacent thereto, and the input unit 4, the output unit 5 and the communication unit 6 are arranged in the subsequent slots 1, 2, and 3, respectively.

The input unit 4 is a unit for inputting data from a relay (not shown) to the PC 3, and the output unit 5 is a unit for outputting data from the PC 3 to the relay. The communication unit 6 is a unit for performing communication between the PC 3 and another PC.

FIG. 7 is a functional block diagram showing an electrical configuration of the PC 3. As shown in FIG. In FIG. 5, a general-purpose CPU (processor, hereinafter simply referred to as CPU) 7 and a bit operation processor (hereinafter, simply referred to as operation processor) 8 store addresses and data in ROM 9, RAM 10 and I / O interface 11. They are connected via a bus 12 including a bus and control signal lines.

The ROM 9 has a reception handler (reception queue setting means) 9a, a transmission handler (transmission queue setting means) 9b, a response task 9c, a transmission task 9d, and a time-out monitoring task (hereinafter referred to as a monitoring task).
A program for each task such as 9e and a program for a task control unit (scan cycle execution means, link cycle execution means) 9f for controlling each task are stored as an operating system (hereinafter referred to as OS) (FIG. 8 (b)).

The RAM 10 stores a sequence program (user program) created by a user, and secures areas for a reception queue 10a and a transmission queue 10b, which will be described later (see FIG. 8A). Also, I /
The O interface 11 connects the PC 3 and each of the units 4 to 6 via a system bus 13 provided on a back plane (not shown) of the rack 1.

The operation processor 8 executes only basic instructions (bit operation, word addition / subtraction, word logical operation, etc.) in the sequence program. CPU
Reference numeral 7 performs preprocessing as described later before executing the program, and executes application instructions (instructions such as word multiplication / division, branch, longword arithmetic operation, and logical operation, which cannot be executed by the arithmetic processor 8) in the program. It is supposed to. The CPU 7 receives and processes input, output, and interrupts from the communication units 4, 5, and 6, and also processes software interrupts generated by execution of the sequence program.

Next, the operation of the present embodiment will be described with reference to FIGS. FIG. 1 schematically shows the flow of software processing controlled by the OS of the PC 3.

As shown in FIG. 1, the CPU 7 of the PC 3
And an operation processor 8 for input scanning for obtaining input information from the input unit 4, program scanning for executing a routine of a sequence program, and output information according to the execution result of the sequence program for the output unit 5.
A scan cycle consisting of an output scan to be output is executed repeatedly.

Interrupts other than the data link request that occur during the execution of the scan cycle are processed when the interrupt occurs. Such interrupts include: Timed interrupt 1: An interrupt program of a sequence program is executed at regular intervals. Timed interrupt 2: Checks at regular intervals whether each part of the PC 3 is in a normal state. Timer refresh: Updates the value of the timer used in the sequence program. I / O interrupt: An interrupt from the input and output units 4 and 5. Start the interrupt processing program of the sequence program. In addition, regarding the time for processing these interrupts, in order to prevent the scan cycle time from becoming extremely long,
There are certain restrictions on the number of processes and the like.

Further, the task control unit 9f executes the timed interrupt 2
As described above, for an interrupt processing task having a relatively low urgency, a limit is imposed on the execution time of the processing task by one interrupt. For example, if it takes 100 ms to execute the routine of the processing task, the execution time by one interruption is limited to 20 ms. Therefore,
In one interruption, only the range that can be inspected within the time limit among the inspection items of each part of the PC 3 is inspected, and inspection of all items is completed by five interruptions.

As shown in FIGS. 2 and 3, during the execution of the scan cycle, a data link request (reception 1, 2) via the communication unit 6 or a communication unit 6 from the PC 3 is received.
When a data link request (link command execution 1 and 2) is generated, the reception handler 9a or the transmission handler 9b is activated, respectively.

The reception and transmission handlers 9a and 9b
S is an interrupt processing program for receiving a received message (received 1,
2) and instructions (instructions 1 and 2) are written into the reception queue 10a and the transmission queue 10b on the RAM 10, and the reception flag and the transmission flag are set in predetermined areas on the RAM 10.

When the reception flag and the transmission flag are set, the response task 9c and the transmission task 9d of the OS are activated after the end of the scan cycle, and the reception and the transmission set in the reception queue 10a and the transmission queue 10b are performed. Processing according to the transmission request is executed. This period corresponds to a data link cycle (hereinafter, referred to as a link cycle).

FIG. 4 is a flowchart showing the control contents of the response task 9c. In FIG. 2, first,
In the determination step R1 of “is the number of receptions equal to or greater than a specified value?
It is determined whether or not the number of received messages set in the reception queue 10a is equal to or greater than a specified number. Here, the specified number is a limit set so that the processing time of the link cycle does not become too long, and is set to, for example, “5”.

If the number of received messages is less than the specified number in the determination step R1 and the determination is "NO", the flow shifts to the processing step R2 of "execution of response processing". In the processing step R2, a process corresponding to the received message set in the reception queue 10a is executed on the PC3 side,
Return a response to the interrupt source. Then, the processing of the response task 9c ends.

On the other hand, if the number of received messages is equal to or greater than the specified number and the determination is "YES" in the determination step R1, a processing step R3 of "execute response processing for the specified number" is performed.
Move to In the processing step R3, the processing corresponding to the specified number of "5" received messages from the head among the received messages set in the reception queue 10a is performed by the PC.
Execution is performed on the 3 side, and a response is returned to the interrupt source. Then, the processing shifts to the processing step R4 of “Reception flag setting”.

When the response task 9c is activated, the reception flag is automatically cleared. In this case, since an unprocessed reception message remains in the reception flag, the response task 9c is reset in the next link cycle. To start,
In processing step R4, a reception flag is set.
Then, the process ends. Since the processing time of the scan cycle is shorter between the link cycle and the scan cycle, even if the remaining processing is transferred to the next link cycle, the effect of the processing being delayed is small.

FIG. 5 is a flowchart showing the control contents of the transmission task 9d. In FIG. 5, first, in a determination step S1 of “response waiting packet?”, It is determined whether a response waiting packet is listed.

Here, the response waiting packet is created as a result of transmission from the PC 3 to another PC or the like in the transmission task 9d, and while waiting for a response from the transmission destination, These are listed in a predetermined area of the RAM 10. The contents of the response waiting packet include a serial number, a code indicating a transmission destination, a transmission time, and the like.

If the response waiting packet is not listed in the judgment step S1 and the judgment is "NO", the process proceeds to a judgment step S2 of "less than the specified number of transmission requests?" In the determination step S2, the transmission queue 10
It is determined whether or not the number of transmission requests (commands 1, 2,...) set in b is equal to or greater than a specified number. The prescribed number here is set for the same reason as described above for the response task 9c.

When the number of transmission requests is equal to or less than the specified number and the determination is "YES" in the determination step S2, the process proceeds to the next processing step S3 of "fetch one transmission packet from a queue". In processing step S3, one transmission request set in the transmission queue 10b is taken out from the head and a transmission packet for performing transmission is created. The transmission packet is a transmission message (command) added with data and the like necessary for transmission to form a predetermined data format.

When one transmission packet has been created, the process proceeds to the next step S4 for determining whether the transmission queue is empty. In determination step S4, it is determined whether or not all the transmission requests set in transmission queue 10b have been extracted. If the transmission request still remains and "NO" is determined, step S
Move to 2.

That is, when the number of transmission requests in the transmission queue 10b is equal to or smaller than the specified number, the process goes through a loop of steps S2 to S4, and all the transmission requests are taken out of the transmission queue 10b. Until it is determined, transmission requests are taken out one by one and transmission packets are created.

Then, in the judgment step S4, "YE
If it is determined to be "S", the process proceeds to the "transmission" processing step S6 to transmit all the created transmission packets. At the same time as the transmission, a response waiting packet is created and listed. At this time, the monitoring task 9e is activated (processing step W3), and the transmission time is written and stored in the response waiting packet corresponding to the one newly transmitted at this time.
Thereafter, the transmission task processing ends.

On the other hand, in the judgment step S2, the number of transmission requests in the transmission queue 10b exceeds the specified number and "N
If it is determined to be "O", the process proceeds to the processing step S5 of "creating a specified number of transmission packets". In the processing step S5, a specified number of transmission requests from the transmission request in the transmission queue 10b are taken out from the head to create a transmission packet.

Then, the processing shifts to the processing step S5a of the next "transmission flag setting", where the transmission flag is set so that the transmission task 9d is activated in the next link cycle. Then, the process proceeds to step S6 to transmit the specified number of transmission packets.

In step S1, if a response waiting packet has already been listed and the judgment is "YES", the monitoring task 9e is started (judgment step W).
1). In the determination step W1 of “time over?”, The monitoring task 9e refers to the transmission time written in the response waiting packet and determines whether or not the specified response waiting time has been exceeded. If there is no response waiting packet exceeding the waiting time, “NO” is determined, and the process shifts to step S2.

In the determination step W1, if there is a response waiting packet exceeding the waiting time, the monitoring task 9e determines "YES", and proceeds to the processing step W2 of "setting an error flag and deleting the packet". Transition. In processing step W2, an error flag indicating that there was no response from the transmission destination within a specified time is stored in RAM1.
When the packet is set to a predetermined area of 0, the response waiting packet whose time has expired is deleted from the list. Then, control goes to a step S2.

As described above, according to this embodiment, when a data link request is issued from an external PC during the execution of a scan cycle by the CPU 7 and the arithmetic processor 8 of the PC 3, the reception handler 9a receives the reception request. When the data link request for the external PC is generated from the PC 3 side, the transmission handler 9b sequentially sets the transmission request in the transmission queue 10b. Then, after executing the scan cycle, the task control unit 9f of the OS activates the response task 9c for processing the reception request set in the reception queue 10a and processes the transmission request set in the transmission queue 10b. The data link cycle for activating the transmission task 9d is executed by the CPU 7 or the arithmetic processor 8.

Therefore, the data link request generated during the execution of the scan cycle is reliably processed after the execution of the scan cycle. Performance can be maintained. Conversely, other interrupt processing that occurs during the execution of the scan cycle is not hindered by the processing of the data link request, so that responsiveness to processing such as an I / O interrupt that is preferably processed in real time is also good. Thus, each interrupt processing request can be processed in a well-balanced manner.

According to the present embodiment, the task control unit 9
f, the response task and the transmission task
Since the number of reception requests and transmission requests to be processed by the CPU 7 or the arithmetic processor 8 at the time of starting each time is limited, the execution time of the data link cycle is limited so that each interrupt processing request can be processed in a more balanced manner. it can.

The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. If it is unlikely that a large number of data link requests will occur within a certain period of time due to the specifications of the system, it is not necessary to particularly limit the number of reception requests and transmission requests that are processed during one activation. Also,
The user may be allowed to set the limit number according to the specifications of the system.

The processor does not necessarily need to use both the CPU 7 and the arithmetic processor 8, and one CPU
May process basic instructions and application instructions. FIG. 1 shows an example in which a reception request and a transmission request occur in different scan cycles. However, even when both requests occur simultaneously in the same scan cycle, the response task 9c,
The transmission task 9d may be serially activated and processed.
Instead of setting the reception and transmission flags to activate the reception and transmission tasks 9c and 9d, the task control unit 9
By directly referring to the reception and transmission queues 10a and 10b by f, each task may be activated if a reception and transmission request is set.

[Brief description of the drawings]

FIG. 1 is a diagram conceptually showing a processing flow of a scan cycle and a link cycle in one embodiment of the present invention.

FIG. 2 is a diagram showing in detail a portion corresponding to the generated reception request in FIG.

FIG. 3 is a diagram showing in detail a portion corresponding to the generated transmission request in FIG. 1;

FIG. 4 is a flowchart showing processing contents of a response task.

FIG. 5 is a flowchart showing processing contents of a transmission task.

FIG. 6 is a diagram showing an I / O configuration of an entire rack including a programmable controller;

FIG. 7 is a diagram showing an electrical configuration of a main part of the programmable controller;

FIG. 8A is a RAM of a programmable controller.
(B) is a diagram conceptually showing the contents of the ROM of the programmable controller.

[Explanation of symbols]

3 is a programmable controller, 4 is an input unit,
5 is an output unit, 7 is a general-purpose CPU (processor), 8
Is a bit operation processor (processor), 9a is a reception handler (reception queue setting means), 9b is a transmission handler (transmission queue setting means), 9c is a response task, 9d is a transmission task, and 9f is a task control unit (scan cycle execution means). , Link cycle executing means), 10a indicates a reception queue, and 10b indicates a transmission queue.

Claims (2)

[Claims] 1. A scan comprising an input scan for obtaining input information from an input unit, a program scan for executing a routine of a user program, and an output scan for outputting output information corresponding to an execution result of the user program to an output unit. Scan cycle execution means for causing a processor to repeatedly execute a cycle, and during execution of the scan cycle by the processor, when a data link request from an external device occurs, reception queue setting means for sequentially setting the reception request in a reception queue, Transmission queue setting means for sequentially setting the transmission request in a transmission queue when a data link request to an external device occurs during the execution of the scan cycle by the processor; and after the execution of the scan cycle by the processor. A link that activates a response task that processes a reception request set in the reception queue and causes the processor to execute a data link cycle that activates a transmission task that processes a transmission request set in the transmission queue. A programmable controller comprising: a cycle execution unit. 2. The response task and the transmission task started by the link cycle execution means have a limit on the number of reception requests and transmission requests to be processed by the processor at one start. The programmable controller according to claim 1.