JPH113946A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of processes for manufacturing a semiconductor device and the number of photomasks for manufacturing the device, by a method wherein an ion-implanted layer constituting a lightly doped layer provided in a drain diffused layer and an ion-implanted layer constituting a field stopper layer in an element isolation region are made equal to each other. SOLUTION: A lightly doped layer 15 is provided in the end part, which opposes to a gate electrode 5, of a source diffused layer 7 and a field relaxation oxide film 41 is provided on the upper part of the layer 15. A drain diffused layer 11 is provided in the other end, on which a field oxide film 39 is aligned with the gate electrode 5, of the film 41. In an element isolation region, the film 39 is provided on a semiconductor substrate 1, and a field stopper layer 19 is provided under the lower part of the film 39. An ion-implanted layer constituting the layer 15 provided under the lower part of the film 41 is provided as the layer 19 in the element isolation region. The impurity concentrations in the surfaces of these of the ion-implanted layer constituting the layer 15 and an ion-implanted layer constituting the layer 19 are 1×17<17> cm<-3> , for example, and the impurity concentration in the surface of a well is 1×10<16> cm<-3> , for example.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device in which a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A prior art structure of a semiconductor device in which a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate will be described with reference to a sectional view of FIG.

FIG. 2 shows a conventional structure of a semiconductor device in which a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate. FIG. 2 shows a complementary transistor including N-channel and P-channel transistors. A P-type well and an N-type well are provided in a semiconductor substrate. The region where the P-type well 21 is provided has an N-channel type high breakdown voltage transistor 27 and a low breakdown voltage transistor 29.
The region where the N-type well 23 is provided has a P-channel type high breakdown voltage transistor 27 and a low breakdown voltage transistor 29.

[0004] The structure of the low breakdown voltage transistor 29 will be briefly described below. The gate insulating film 3 is provided on the semiconductor substrate 1, and the gate electrode 5 is provided on the gate insulating film 3.
A source diffusion layer 7 is provided at an end of the gate electrode 5, and the source diffusion layer 7 and the source electrode 9 are electrically connected. Further, a drain diffusion layer 11 is provided at an end of the gate electrode 5 facing the source diffusion layer 7, and the drain diffusion layer 11 and the drain electrode 13 are electrically connected.

The structure of the high voltage transistor 27 will be briefly described below. The gate insulating film 3 is provided on the semiconductor substrate 1, and the gate electrode 5 is provided on the gate insulating film 3.
A source diffusion layer 7 is provided at an end of the gate electrode 5, and the source diffusion layer 7 and the source electrode 9 are electrically connected. Further, a drain diffusion layer 11 is provided at an end of the gate electrode 5 facing the source diffusion layer 7, and the drain diffusion layer 11 and the drain electrode 13 are electrically connected. Further, a lightly doped layer 15 composed of an impurity diffusion layer having a lower impurity concentration than that of the drain diffusion layer 11 is provided on the drain diffusion layer 11, and an electric field relaxation oxide film 41 is provided between the gate electrode 5 and the lightly doped layer 15.

A field oxide film 39 is provided in the element isolation region, and a field stopper layer 19 is provided below the field oxide film 39.

In general, the breakdown voltage of a MOS transistor is determined mainly by the extension of a depletion layer formed at a PN junction between a drain diffusion layer composed of a high-concentration impurity diffusion layer and a semiconductor substrate. In particular, a semiconductor substrate greatly affected by an electric field from a gate electrode. In the vicinity of the surface, the depletion layer becomes more difficult to extend. In order to improve the breakdown voltage, the depletion layer formed at the PN junction may be easily extended. In general, the lower the impurity concentration at the PN junction, the more easily the depletion layer is extended. It is common practice to form a layer between the drain diffusion layer and the semiconductor substrate.

In the high breakdown voltage transistor shown in FIG. 2, a lightly doped layer 15 made of an impurity diffusion layer of the same conductivity type with a lower concentration than the drain diffusion layer 11 is provided so as to surround the drain diffusion layer 11, so that the PN junction is improved. , The impurity concentration is reduced, and the depletion layer is easily extended.

On the other hand, in order to prevent the surface of the semiconductor substrate in the element isolation region from being inverted due to the voltage of the wiring and causing a leak current between the elements, a field stopper layer 19 must be provided to increase the impurity concentration on the surface of the semiconductor substrate. There is.

Next, the high voltage transistor 27 and the low voltage transistor 2 driven by different power supply voltages shown in FIG.
A conventional technique for manufacturing a semiconductor device in which the semiconductor device 9 is formed on the same semiconductor substrate 1 will be described with reference to the drawings. 3 to 13
3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in the related art in the order of steps.

First, as shown in FIG. 3, the surface of the semiconductor substrate 1 is oxidized in an oxidizing atmosphere to form a film having a thickness of 0.5.
A silicon oxide film 17 of about μm is formed. Next, a photoresist (not shown) is formed on the entire upper surface of the silicon oxide film 17 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that a region for forming an N-type well is opened. Subsequently, using the photoresist as an etching mask, the silicon oxide film 17 in the photoresist opening is completely removed. After that, the photoresist is removed.

Next, as shown in FIG. 4, the silicon oxide film 17 is used as an ion
1 is ion-implanted. After that, the silicon oxide film 17 is completely removed.

Next, as shown in FIG. 5, a photoresist 25 is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Next, an exposure process using a predetermined photomask,
A development process is performed, and the photoresist 25 is patterned so that a region for forming a P-type well is opened. Subsequently, ions of the P-type impurity 35 are implanted by using the photoresist 25 as an ion implantation blocking film. After that, the photoresist 25 is removed.

Next, as shown in FIG. 6, an N-type impurity 31 and a P-type impurity 35 are diffused deeply into the semiconductor substrate 1 by performing a heat treatment, so that an N-type well 23 and a P-type well 2 are formed.
Form one.

Next, as shown in FIG. 7, a photoresist 25 is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Next, an exposure process using a predetermined photomask,
A developing process is performed, and the photoresist 25 is patterned so that a region for forming the N-type lightly doped layer is opened.

Subsequently, the N-type impurity 31 is ion-implanted using the photoresist 25 as an ion-implantation preventing film. After that, the photoresist 25 is removed.

Next, as shown in FIG. 8, a photoresist 25 is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Next, an exposure process using a predetermined photomask,
A development process is performed, and the photoresist 25 is patterned so that a region where a P-type lightly doped layer is formed is opened.

Subsequently, P-type impurities 35 are ion-implanted using the photoresist 25 as an ion-implantation preventing film. After that, the photoresist 25 is removed.

Next, as shown in FIG. 9, heat treatment in a nitrogen atmosphere is performed to
The n-type and P-type lightly doped diffusion layers 15 are formed by diffusing the type impurities 35. Subsequently, the silicon nitride film 3
7 is formed on the entire upper surface of the semiconductor substrate 1. further,
A photoresist 25 is formed on the entire upper surface of the silicon nitride film 37 by a spin coating method.

Subsequently, an exposure process and a development process are performed using a predetermined photomask, and a photoresist 25 is formed so that a region for forming an electric field relaxation oxide film is opened in an element isolation region and a region for forming a high breakdown voltage transistor. Perform patterning. Further, a patterned photoresist 2
5 is used as an etching mask until the silicon nitride film 37 in the photoresist opening is completely removed. After that, the photoresist is removed.

Next, as shown in FIG. 10, a photoresist 25 is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. After that, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that a region for forming an N-type field stopper layer is opened.

Subsequently, the N-type impurity 31 is ion-implanted using the photoresist 25 and the silicon nitride film 37 as an ion-implantation preventing film. After that, the photoresist 25 is removed.

Next, as shown in FIG. 11, a photoresist 25 is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. After that, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that a region for forming a P-type field stopper layer is opened.

Subsequently, ions of the P-type impurity 35 are implanted using the photoresist 25 and the silicon nitride film 37 as an ion implantation blocking film. After that, the photoresist 25 is removed.

Next, as shown in FIG. 12, by performing an oxidation process, a region where the silicon nitride film 37 is not present is selectively oxidized, and a field oxide film 39 and an electric field relaxation oxide film 41 are formed. After that, the silicon nitride film 37 is removed.

Next, a gate oxide film (not shown) is formed by performing an oxidation process. Thereafter, polysilicon, which is a gate electrode material, is formed on the entire upper surface of the semiconductor substrate 1. Thereafter, a photoresist (not shown) is formed on the entire upper surface of the polysilicon by a spin coating method. Continued
Exposure processing and development processing are performed using a predetermined photomask, and the photoresist is patterned so that openings are formed in regions other than the region serving as the gate electrode.

Next, using a photoresist as an etching mask, etching is performed until the polysilicon in the photoresist opening is completely removed, thereby forming a gate electrode (not shown). After that, the photoresist is removed.

Next, as shown in FIG. 13, a photoresist 25 is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Subsequently, in order to form a drain diffusion layer and a source diffusion layer, an exposure process and a development process are performed using a predetermined photomask, and the photoresist 25 is formed into an N-channel type low breakdown voltage transistor and a high breakdown voltage transistor. Pattern so that the region is opened.

Subsequently, the photoresist 25 is used as an ion implantation blocking film, and the P-type well 21 which matches the gate electrode 3, the field oxide film 39 and the electric field relaxation oxide film 41 is used.
Then, an N-type impurity is ion-implanted. After that, the photoresist 25 is removed.

Next, a photoresist (not shown) is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Subsequently, in order to form a drain diffusion layer and a source diffusion layer, an exposure process and a development process are performed using a predetermined photomask, and a photoresist is formed in a region where a P-channel low breakdown voltage transistor and a high breakdown voltage transistor are to be formed. Pattern so as to open.

Subsequently, a P-type impurity is ion-implanted into the N-type well 23 corresponding to the gate electrode 3, the field oxide film 39 and the electric field relaxation oxide film 41 by using a photoresist as an ion implantation preventing film. After that, the photoresist is removed.

Next, as shown in FIG. 2, an insulating film 43 is formed on the entire upper surface of the semiconductor substrate 1. Thereafter, a heat treatment is performed in a nitrogen atmosphere, so that the drain diffusion layer 1 is formed.
1 and the impurity implanted into the source diffusion layer 7 are electrically activated. This heat treatment in a nitrogen atmosphere is performed by the insulating film 4.
3 also serves as the surface flattening.

Next, a photoresist (not shown) is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Subsequently, an exposure process and a development process are performed using a predetermined photomask, and a photoresist (not shown) is patterned so that a contact hole is opened.

Subsequently, the insulating film 4 in the photoresist opening
Etching is performed until 3 is completely removed to form a contact hole. After that, the photoresist is removed. Subsequently, a film of a metal electrode material for forming the drain electrode 13 and the source electrode 9 is formed on the entire upper surface of the semiconductor substrate 1.

Next, a photoresist (not shown) is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Subsequently, an exposure process and a development process are performed using a predetermined photomask, and a photoresist (not shown) is patterned so as to open an area other than a region where the drain electrode 13 and the source electrode 9 are formed.

Subsequently, the drain electrode 13 and the source electrode 9 are formed by etching until the metal electrode material in the photoresist opening is completely removed. After that, the photoresist is removed.

In this way, it is possible to form a semiconductor device in which the high breakdown voltage transistor 27 and the low breakdown voltage transistor 29 driven by different power supply voltages are mixed on the same semiconductor substrate 1 in the conventional technique as shown in FIG. it can.

[0038]

SUMMARY OF THE INVENTION High breakdown voltage transistor 2
In order to secure the withstand voltage of 7, the lightly doped layer 15 needs to be provided. On the other hand, it is necessary to provide a field stopper layer 19 in the element isolation region so that the surface of the semiconductor substrate in the element isolation region is not inverted and a leak current does not occur. Since the lightly doped layer 15 and the field stopper layer 19 have different roles as described above, the optimum surface impurity concentrations are different from each other. In the device manufacturing process, different photoresist patterning and ion implantation are performed. It is formed in a process.

For this reason, the manufacturing process of the semiconductor device in which the high breakdown voltage transistor and the low breakdown voltage transistor are formed on the same semiconductor substrate is more complicated than the case where only the low breakdown voltage transistor or only the high breakdown voltage transistor is manufactured. number,
And the number of photomasks increases.

[Object of the Invention] An object of the present invention is to solve the above-mentioned problems, and to provide a semiconductor device and a method for manufacturing the same in which a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate. An object of the present invention is to provide a semiconductor device capable of reducing the number and the number of photomasks and a method for manufacturing the same.

[0041]

In order to achieve the above object, a semiconductor device and a method of manufacturing the same according to the present invention employ the following structure and manufacturing method.

In the semiconductor device of the present invention, a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate, and the high breakdown voltage transistor is a gate insulating film provided on the semiconductor substrate. A gate electrode provided on the gate insulating film, a source diffusion layer provided at an end of the gate electrode, a source electrode connected to the source diffusion layer, and an end of the gate electrode facing the source diffusion layer. A drain diffusion layer provided; a drain electrode connected to the drain diffusion layer; a lightly doped layer provided in the drain diffusion layer comprising an impurity diffusion layer having an impurity concentration lower than that of the drain diffusion layer; a gate electrode and a lightly doped layer An electric field relaxation oxide film provided between the gate insulating film and the gate insulating film provided on the semiconductor substrate. A gate electrode provided above the insulating film; a source diffusion layer provided at one end of the gate electrode; a source electrode connected to the source diffusion layer; and a drain diffusion layer provided at an end of the gate electrode facing the source diffusion layer. And a drain electrode connected to the drain diffusion layer, wherein a lightly doped layer and a field stopper layer in an element isolation region are the same ion-implanted layer.

In the semiconductor device of the present invention, a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate, and the high breakdown voltage transistor is a gate insulating film provided on the semiconductor substrate. A gate electrode provided on the gate insulating film, a source diffusion layer provided at an end of the gate electrode, a source electrode connected to the source diffusion layer, and an end of the gate electrode facing the source diffusion layer. A drain diffusion layer provided; a drain electrode connected to the drain diffusion layer; and a lightly doped layer provided on the drain diffusion layer and the source diffusion layer comprising an impurity diffusion layer having an impurity concentration lower than that of the drain diffusion layer and the source diffusion layer. And an electric field relaxation oxide film provided between the gate electrode and the lightly doped layer. A gate insulating film provided thereon, a gate electrode provided on the gate insulating film, a source diffusion layer provided at an end of the gate electrode, a source electrode connected to the source diffusion layer, and a source of the gate electrode. A drain diffusion layer provided at an end opposite to the diffusion layer, including a drain electrode connected to the drain diffusion layer, a lightly doped layer,
The ion implantation layer constituting the field stopper layer in the element isolation region is the same.

In the method of manufacturing a semiconductor device according to the present invention, a P-type impurity is selectively implanted into a semiconductor substrate to form a P-type well, and an N-type impurity is implanted selectively. Forming an N-type well by patterning a photoresist so that a region for forming a lightly doped layer in an N-channel region and a field stopper layer in a P-channel region are opened; and using the photoresist as an ion implantation preventing film, N-type impurity atoms are ion-implanted into a region where a field stopper layer is to be formed, and heat treatment is performed to simultaneously form a light-doped layer having an N-type conductivity and a field stopper layer; The photoresist so that the region and the region for forming the field stopper layer of the N channel region are opened. A step of ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are to be formed using a photoresist as an ion-implantation preventing film, and simultaneously forming a light-doped layer and a field stopper layer of P-type conductivity; By forming a silicon nitride film on the entire surface and performing photoetching, an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor is formed. A step of opening the silicon nitride film in the region, a step of forming a silicon oxide film on the surface in the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere, and a step of etching and removing the silicon nitride film; A gate electrode material is formed on the entire surface, and photo-etching is performed. Patterning, selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer to form drain diffusion layers and source diffusion layers of high-voltage transistors and low-voltage transistors, and forming an insulating film over the entire surface And forming a contact hole by performing a photoetching process, and patterning the drain electrode and the source electrode by performing a photoetching process by forming a drain electrode and a source electrode material on the entire surface. Features.

According to the method of manufacturing a semiconductor device of the present invention, a P-type impurity is selectively implanted into a semiconductor substrate to form a P-type well, and an N-type impurity is implanted selectively. Forming an N-type well by patterning a photoresist so that a region for forming a lightly doped layer in an N-channel region and a field stopper layer in a P-channel region are opened; and using the photoresist as an ion implantation preventing film, N-type impurity atoms are ion-implanted into a region where a field stopper layer is to be formed, and heat treatment is performed to simultaneously form a light-doped layer having an N-type conductivity and a field stopper layer; The photoresist so that the region and the region for forming the field stopper layer of the N channel region are opened. A step of ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are to be formed using a photoresist as an ion-implantation preventing film, and simultaneously forming a light-doped layer and a field stopper layer of P-type conductivity; A silicon nitride film is formed on the entire surface and photoetching is performed to reduce the electric field composed of a silicon oxide film thicker than the gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor. A step of opening the silicon nitride film in a region where the oxide film is to be formed, a step of forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere, and a step of etching the silicon nitride film. Removing and forming a gate electrode material over the entire surface and performing photoetching A step of patterning the gate electrode, a step of selectively ion-implanting impurity atoms of the same conductivity type as that of the lightly doped layer, and a step of forming a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor; Forming a contact hole by performing a photo-etching process, and a process of patterning the drain electrode and the source electrode by performing a photo-etching process by forming a drain electrode and a source electrode material on the entire surface, It is characterized by having.

According to the method of manufacturing a semiconductor device of the present invention, a P-type well is formed by selectively ion-implanting P-type impurity atoms into a N-type semiconductor substrate; The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. Then, by performing a heat treatment, a step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer, and a region for forming a lightly doped layer of a P channel region and a field stopper layer of an N channel region are opened. Pattern the photoresist as described above, and use the photoresist as a light doping layer as an ion implantation blocking film. The P-type impurity atoms are ion-implanted into a region for forming a field stop layer and conductivity type is P
Forming a light-doped layer and a field stopper layer of a mold at the same time, and forming a silicon nitride film on the entire surface and performing photo-etching to provide an element isolation region and a gate provided on the drain diffusion layer side of a gate electrode in a high breakdown voltage transistor. Forming a silicon oxide film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than an insulating film is formed, and forming a silicon oxide film on a surface in the silicon nitride film opening by performing an oxidation process in an oxidizing atmosphere Performing a step of etching and removing the silicon nitride film; a step of forming a gate electrode material on the entire surface and patterning the gate electrode by performing a photoetching process; and a step of forming impurity atoms having the same conductivity type as the lightly doped layer. Is selectively implanted, and the drains of the high-voltage transistor and the low-voltage transistor are drained. Forming a diffusion layer and a source diffusion layer, forming an insulating film on the entire surface and performing a photoetching process to form a contact hole, and forming a drain electrode and a source electrode material on the entire surface and performing a photoetching process. Performing a patterning of the drain electrode and the source electrode by performing.

According to the method of manufacturing a semiconductor device of the present invention, a P-type well is formed by selectively ion-implanting P-type impurity atoms into a N-type semiconductor substrate; The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. Then, by performing a heat treatment, a step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer, and a region for forming a lightly doped layer of a P channel region and a field stopper layer of an N channel region are opened. Pattern the photoresist as described above, and use the photoresist as a light doping layer as an ion implantation blocking film. The P-type impurity atoms are ion-implanted into a region for forming a field stop layer and conductivity type is P
Forming a light-doped layer and a field stopper layer of the mold at the same time, forming a silicon nitride film on the entire surface, and performing photo-etching to separate the source electrode from the drain diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor. A step of opening the silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than the gate insulating film provided on the layer side is formed, and performing an oxidation process in an oxidizing atmosphere to form a surface inside the silicon nitride film opening. Forming a silicon oxide film, etching and removing the silicon nitride film, and forming a gate electrode material on the entire surface;
A step of patterning the gate electrode by photoetching, and selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer to form a drain diffusion layer and a source diffusion layer of the high-breakdown-voltage transistor and the low-breakdown-voltage transistor Forming a contact hole by forming an insulating film on the entire surface and performing a photoetching process; and forming a drain electrode and a source electrode by forming a drain electrode and a source electrode material on the entire surface and performing a photoetching process. And a step of patterning.

The method of manufacturing a semiconductor device according to the present invention includes the steps of selectively ion-implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well; The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. Then, by performing a heat treatment, a step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer, and a region for forming a lightly doped layer of a P channel region and a field stopper layer of an N channel region are opened. Pattern the photoresist as described above, and use the photoresist as a light doping layer as an ion implantation blocking film. The P-type impurity atoms are ion-implanted into a region for forming a field stop layer and conductivity type is P
Forming a light-doped layer and a field stopper layer of a mold at the same time, and forming a silicon nitride film on the entire surface and performing photo-etching to provide an element isolation region and a gate provided on the drain diffusion layer side of a gate electrode in a high breakdown voltage transistor. Forming a silicon oxide film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than an insulating film is formed, and forming a silicon oxide film on a surface in the silicon nitride film opening by performing an oxidation process in an oxidizing atmosphere Performing a step of etching and removing the silicon nitride film; a step of forming a gate electrode material on the entire surface and patterning the gate electrode by performing a photoetching process; and a step of forming impurity atoms having the same conductivity type as the lightly doped layer. Is selectively implanted, and the drains of the high-voltage transistor and the low-voltage transistor are drained. Forming a diffusion layer and a source diffusion layer, forming an insulating film on the entire surface and performing a photoetching process to form a contact hole, and forming a drain electrode and a source electrode material on the entire surface and performing a photoetching process. Performing a patterning of the drain electrode and the source electrode by performing.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of selectively implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well; The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. Then, by performing a heat treatment, a step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer, and a region for forming a lightly doped layer of a P channel region and a field stopper layer of an N channel region are opened. Pattern the photoresist as described above, and use the photoresist as a light doping layer as an ion implantation blocking film. The P-type impurity atoms are ion-implanted into a region for forming a field stop layer and conductivity type is P
Forming a light-doped layer and a field stopper layer of the mold at the same time, forming a silicon nitride film on the entire surface, and performing photo-etching to separate the source electrode from the drain diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor. A step of opening the silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than the gate insulating film provided on the layer side is formed, and performing an oxidation process in an oxidizing atmosphere to form a surface inside the silicon nitride film opening. Forming a silicon oxide film, etching and removing the silicon nitride film, and forming a gate electrode material on the entire surface;
A step of patterning the gate electrode by photoetching, and selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer to form a drain diffusion layer and a source diffusion layer of the high-breakdown-voltage transistor and the low-breakdown-voltage transistor Forming a contact hole by forming an insulating film on the entire surface and performing a photoetching process; and forming a drain electrode and a source electrode by forming a drain electrode and a source electrode material on the entire surface and performing a photoetching process. And a step of patterning.

According to the method of manufacturing a semiconductor device of the present invention, a P-type impurity is selectively implanted into a semiconductor substrate to form a P-type well, and an N-type impurity is implanted selectively. Forming an N-type well by patterning a photoresist so that a region for forming a lightly doped layer in an N-channel region and a field stopper layer in a P-channel region are opened; and using the photoresist as an ion implantation preventing film, A step of ion-implanting N-type impurity atoms into a region where a field stopper layer is to be formed, and simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer; Pattern the photoresist so that the area where the field stopper layer is formed is opened, and ionize the photoresist A step of ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are formed as a blocking layer and simultaneously forming a P-type light-doped layer and a field stopper layer with a conductivity type; Silicon nitride in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a drain diffusion layer side of a gate electrode in a device isolation region and a high breakdown voltage transistor is formed by performing photo-etching processing over the entire surface. A step of opening the film, a step of forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere, a step of etching and removing the silicon nitride film, Patterning the gate electrode by forming it on the entire surface and performing photoetching; A step of selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer to form a drain diffusion layer and a source diffusion layer of a high-voltage transistor and a low-voltage transistor; To form a contact hole, and a step of patterning the drain electrode and the source electrode by forming a material of the drain electrode and the source electrode on the entire surface and performing a photo-etching process.

According to the method of manufacturing a semiconductor device of the present invention, a P-type well is formed by selectively implanting P-type impurity atoms into a semiconductor substrate, and an N-type impurity atom is selectively implanted into a semiconductor substrate. Forming an N-type well by patterning a photoresist so that a region for forming a lightly doped layer in an N-channel region and a field stopper layer in a P-channel region are opened; and using the photoresist as an ion implantation preventing film, A step of ion-implanting N-type impurity atoms into a region where a field stopper layer is to be formed, and simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer; Pattern the photoresist so that the area where the field stopper layer is formed is opened, and ionize the photoresist A step of ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are formed as a blocking layer and simultaneously forming a P-type light-doped layer and a field stopper layer with a conductivity type; Formed over the entire surface and photoetched to form an electric field relaxation oxide film consisting of a silicon oxide film thicker than the gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode in the element isolation region and high breakdown voltage transistor Forming a silicon oxide film on the surface in the silicon nitride film opening by performing an oxidizing process in an oxidizing atmosphere, and removing the silicon nitride film by etching. ,
Forming a gate electrode material on the entire surface and patterning the gate electrode by performing a photoetching process;
Selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer to form a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor;
A step of forming a contact hole by forming an insulating film on the entire surface and performing photoetching processing; and a step of forming a drain electrode and a source electrode material on the entire surface and patterning the drain electrode and source electrode by performing photoetching processing And the following.

The method of manufacturing a semiconductor device according to the present invention includes the steps of selectively ion-implanting P-type impurity atoms into a N-type semiconductor substrate to form a P-type well; The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. And the conductivity type is N
Forming a light-doped layer and a field stopper layer of the mold at the same time; patterning the photoresist so that the regions for forming the light-doped layer in the P-channel region and the field stopper layer in the N-channel region are opened; A step of ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are formed as a film, and simultaneously forming a P-type light-doped layer and a field stopper layer with a conductivity type; The silicon nitride film in the region for forming the field relaxation oxide film made of a silicon oxide film thicker than the gate insulating film provided on the drain diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor is formed by performing the photo-etching process. Opening process and performing oxidation treatment in an oxidizing atmosphere Therefore, a step of forming a silicon oxide film on the surface in the opening of the silicon nitride film, a step of etching and removing the silicon nitride film, and forming a gate electrode material over the entire surface and patterning the gate electrode by performing a photoetching process Forming a drain diffusion layer and a source diffusion layer of a high breakdown voltage transistor and a low breakdown voltage transistor by selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer, and forming an insulating film over the entire surface. Forming a contact hole by performing a photo-etching process, and patterning a drain electrode and a source electrode by performing a photo-etching process by forming a drain electrode and a source electrode material on the entire surface. And

The method of manufacturing a semiconductor device according to the present invention comprises the steps of selectively implanting P-type impurity atoms into a N-type semiconductor substrate to form a P-type well; The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. And the conductivity type is N
Forming a light-doped layer and a field stopper layer of the mold at the same time; patterning the photoresist so that the regions for forming the light-doped layer in the P-channel region and the field stopper layer in the N-channel region are opened; A step of ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are formed as a film, and simultaneously forming a P-type light-doped layer and a field stopper layer with a conductivity type; Forming and photo-etching the element isolation region and a region for forming an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode in the high breakdown voltage transistor Opening a silicon nitride film of
Forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere;
A step of etching and removing the silicon nitride film, a step of forming a gate electrode material on the entire surface and patterning the gate electrode by performing a photoetching process, and selectively removing impurity atoms of the same conductivity type as the lightly doped layer. A step of forming a drain diffusion layer and a source diffusion layer of a high breakdown voltage transistor and a low breakdown voltage transistor by ion implantation, a step of forming a contact hole by forming an insulating film over the entire surface and performing a photoetching process, and a step of forming a drain electrode. And a step of patterning the drain electrode and the source electrode by forming a source electrode material on the entire surface and performing a photoetching process.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of selectively implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well; The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. And the conductivity type is N
Forming a light-doped layer and a field stopper layer of the mold at the same time; patterning the photoresist so that the regions for forming the light-doped layer in the P-channel region and the field stopper layer in the N-channel region are opened; A step of ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are formed as a film, and simultaneously forming a P-type light-doped layer and a field stopper layer with a conductivity type; The silicon nitride film in the region for forming the field relaxation oxide film made of a silicon oxide film thicker than the gate insulating film provided on the drain diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor is formed by performing the photo-etching process. Opening process and performing oxidation treatment in an oxidizing atmosphere Therefore, a step of forming a silicon oxide film on the surface in the opening of the silicon nitride film, a step of etching and removing the silicon nitride film, and forming a gate electrode material over the entire surface and patterning the gate electrode by performing a photoetching process Forming a drain diffusion layer and a source diffusion layer of a high breakdown voltage transistor and a low breakdown voltage transistor by selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer, and forming an insulating film over the entire surface. Forming a contact hole by performing a photo-etching process, and patterning a drain electrode and a source electrode by performing a photo-etching process by forming a drain electrode and a source electrode material on the entire surface. And

The method of manufacturing a semiconductor device according to the present invention includes the steps of selectively ion-implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well; The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. And the conductivity type is N
Forming a light-doped layer and a field stopper layer of the mold at the same time; patterning the photoresist so that the regions for forming the light-doped layer in the P-channel region and the field stopper layer in the N-channel region are opened; A step of ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are formed as a film, and simultaneously forming a P-type light-doped layer and a field stopper layer with a conductivity type; Forming and photo-etching the element isolation region and a region for forming an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode in the high breakdown voltage transistor Opening a silicon nitride film of
Forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere;
A step of etching and removing the silicon nitride film, a step of forming a gate electrode material on the entire surface and patterning the gate electrode by performing a photoetching process, and selectively removing impurity atoms of the same conductivity type as the lightly doped layer. A step of forming a drain diffusion layer and a source diffusion layer of a high breakdown voltage transistor and a low breakdown voltage transistor by ion implantation, a step of forming a contact hole by forming an insulating film over the entire surface and performing a photoetching process, and a step of forming a drain electrode. And a step of patterning the drain electrode and the source electrode by forming a source electrode material on the entire surface and performing a photoetching process.

According to the method of manufacturing a semiconductor device of the present invention, a P-type impurity is selectively implanted into a semiconductor substrate to form a P-type well, and an N-type impurity is implanted selectively. Forming an N-type well by patterning a photoresist so that a region for forming a lightly doped layer in an N-channel region and a field stopper layer in a P-channel region are opened; and using the photoresist as an ion implantation preventing film, N-type impurity atoms are ion-implanted into a region where a field stopper layer is to be formed, and heat treatment is performed to simultaneously form a light-doped layer having an N-type conductivity and a field stopper layer; The photoresist so that the region and the region for forming the field stopper layer of the N channel region are opened. P-type impurity atoms are ion-implanted into a region where a light dope layer and a field stopper layer are to be formed using a photoresist as an ion implantation blocking film, and heat treatment is performed to form a light-doped layer having a P-type conductivity and a field stopper layer. An electric field consisting of a silicon oxide film thicker than the gate insulating film provided on the drain diffusion layer side of the gate electrode in the element isolation region and the high-breakdown-voltage transistor by performing a simultaneously forming step and forming a silicon nitride film over the entire surface and performing photoetching processing. A step of opening the silicon nitride film in a region where the relaxed oxide film is to be formed, a step of forming a silicon oxide film on the surface in the opening of the silicon nitride film by performing oxidation treatment in an oxidizing atmosphere, and Process, and a gate electrode material is formed on the entire surface. Patterning the gate electrode by selectively implanting impurity atoms of the same conductivity type as the lightly doped layer to form a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor; A step of forming a contact hole by forming an insulating film on the entire surface and performing photoetching processing; and a step of forming a drain electrode and a source electrode material on the entire surface and patterning the drain electrode and source electrode by performing photoetching processing And the following.

According to the method of manufacturing a semiconductor device of the present invention, a P-type impurity atom is selectively implanted into a semiconductor substrate to form a P-type well, and an N-type impurity atom is selectively implanted. Forming an N-type well by patterning a photoresist so that a region for forming a lightly doped layer in an N-channel region and a field stopper layer in a P-channel region are opened; and using the photoresist as an ion implantation preventing film, N-type impurity atoms are ion-implanted into a region where a field stopper layer is to be formed, and heat treatment is performed to simultaneously form a light-doped layer having an N-type conductivity and a field stopper layer; The photoresist so that the region and the region for forming the field stopper layer of the N channel region are opened. P-type impurity atoms are ion-implanted into a region where a light dope layer and a field stopper layer are to be formed using a photoresist as an ion implantation blocking film, and heat treatment is performed to form a light-doped layer having a P-type conductivity and a field stopper layer. Simultaneous formation and formation of a silicon nitride film over the entire surface and photo-etching to form an oxide film thicker than the gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor. A step of opening the silicon nitride film in a region where an electric field relaxation oxide film made of a silicon film is formed; a step of forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation process in an oxidizing atmosphere; Removing the silicon film by etching;
Forming a gate electrode material on the entire surface and patterning the gate electrode by performing a photoetching process;
Selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer to form a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor;
A step of forming a contact hole by forming an insulating film on the entire surface and performing photoetching processing; and a step of forming a drain electrode and a source electrode material on the entire surface and patterning the drain electrode and source electrode by performing photoetching processing And the following.

The method of manufacturing a semiconductor device according to the present invention includes the steps of selectively ion-implanting P-type impurity atoms into a N-type semiconductor substrate to form a P-type well; The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. Then, by performing a heat treatment, a step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer, and a region for forming a lightly doped layer of a P channel region and a field stopper layer of an N channel region are opened. Pattern the photoresist as described above, and use the photoresist as a light doping layer as an ion implantation blocking film. Ion implantation of P-type impurity atoms into a region where a field stopper layer is to be formed and heat treatment to form a lightly doped layer having a P-type conductivity and a field stopper layer at the same time; And a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor by performing photoetching processing Forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidizing process in an oxidizing atmosphere; etching the silicon nitride film to remove the silicon nitride film; Patterning the gate electrode by photolithography and patterning the gate electrode. Doped layer and the same conductivity type impurity atoms are selectively ion-implanted, and forming a drain diffusion layer and the source diffusion layer of the high breakdown voltage transistors and low voltage transistors, the insulating film is formed on the entire surface,
Forming a contact hole by performing a photoetching process, and patterning a drain electrode and a source electrode by forming a drain electrode and a source electrode material on the entire surface and performing a photoetching process. I do.

According to the method of manufacturing a semiconductor device of the present invention, a P-type well is formed by selectively ion-implanting P-type impurity atoms into a N-type semiconductor substrate, and a lightly doped N-channel region is formed. The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. Then, by performing a heat treatment, a step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer, and a region for forming a lightly doped layer of a P channel region and a field stopper layer of an N channel region are opened. Pattern the photoresist as described above, and use the photoresist as a light doping layer as an ion implantation blocking film. Ion implantation of P-type impurity atoms into a region where a field stopper layer is to be formed and heat treatment to form a lightly doped layer having a P-type conductivity and a field stopper layer at the same time; And an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor by performing photoetching processing. A step of opening the silicon nitride film in the region, a step of forming a silicon oxide film on the surface in the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere, and a step of etching and removing the silicon nitride film; Gate electrode material is formed on the entire surface and photo-etching is performed to pattern the gate electrode Forming a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor by selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer; and forming an insulating film over the entire surface. Forming a contact hole by performing a photo-etching process, and patterning a drain electrode and a source electrode by performing a photo-etching process by forming a drain electrode and a source electrode material on the entire surface. And

The method of manufacturing a semiconductor device according to the present invention comprises the steps of selectively ion-implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well; The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. Then, by performing a heat treatment, a step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer, and a region for forming a lightly doped layer of a P channel region and a field stopper layer of an N channel region are opened. Pattern the photoresist as described above, and use the photoresist as a light doping layer as an ion implantation blocking film. Ion implantation of P-type impurity atoms into a region where a field stopper layer is to be formed and heat treatment to form a lightly doped layer having a P-type conductivity and a field stopper layer at the same time; And a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor by performing photoetching processing Forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidizing process in an oxidizing atmosphere; etching the silicon nitride film to remove the silicon nitride film; Patterning the gate electrode by photolithography and patterning the gate electrode. Doped layer and the same conductivity type impurity atoms are selectively ion-implanted, and forming a drain diffusion layer and the source diffusion layer of the high breakdown voltage transistors and low voltage transistors, the insulating film is formed on the entire surface,
Forming a contact hole by performing a photoetching process, and patterning a drain electrode and a source electrode by forming a drain electrode and a source electrode material on the entire surface and performing a photoetching process. I do.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of selectively implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well and forming a lightly doped N-channel region. The photoresist is patterned so that the layer and the region where the field stopper layer of the P channel region is formed are opened, and N-type impurity atoms are ion-implanted into the region where the lightly doped layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film. Then, by performing a heat treatment, a step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer, and a region for forming a lightly doped layer of a P channel region and a field stopper layer of an N channel region are opened. Pattern the photoresist as described above, and use the photoresist as a light doping layer as an ion implantation blocking film. Ion implantation of P-type impurity atoms into a region where a field stopper layer is to be formed and heat treatment to form a lightly doped layer having a P-type conductivity and a field stopper layer at the same time; And an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor by performing photoetching processing. A step of opening the silicon nitride film in the region, a step of forming a silicon oxide film on the surface in the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere, and a step of etching and removing the silicon nitride film; Gate electrode material is formed on the entire surface and photo-etching is performed to pattern the gate electrode Forming a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor by selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer; and forming an insulating film over the entire surface. Forming a contact hole by performing a photo-etching process, and patterning a drain electrode and a source electrode by performing a photo-etching process by forming a drain electrode and a source electrode material on the entire surface. And

[Operation] In a semiconductor device according to the present invention in which a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate, a lightly doped layer of the high breakdown voltage transistor and a field stopper layer in an element isolation region are provided. Are formed in the same ion-implanted layer.

Since the ion implantation layer forming the lightly doped layer and the field stopper layer are the same, the field stopper layer is also used in the photolithography step for forming the lightly doped layer and the ion implantation step in the manufacturing process. It can be formed simultaneously. Thus, in the present invention, the number of steps can be reduced by four, and the number of photomasks can be reduced by two.

Further, in the present invention, by making the ion implantation layer constituting the field stopper layer the same as the ion implantation layer constituting the lightly doped layer, the inversion voltage of the element isolation region is reduced and the leakage current is increased. There is no.

[0065]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments for carrying out the present invention will be described below with reference to the drawings. First, the structure of a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

[Structure of Semiconductor Device: FIG. 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention in which a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate. . FIG. 1 shows a complementary transistor including N-channel and P-channel transistors.

The high breakdown voltage transistor 27 is connected to the semiconductor substrate 1
A gate insulating film 3 is provided thereon. As the gate insulating film 3, a silicon oxide film having a thickness of about 80 nm is used. A gate electrode 5 made of polysilicon having a thickness of about 450 nm is provided on the gate insulating film 3, and a source diffusion layer 7 is provided at one end where the gate electrode 5 and the field oxide film 39 match. As an impurity used for the source diffusion layer 7, a phosphorus atom is used for the N-channel type high breakdown voltage transistor 27, and a boron atom is used for the P-channel type high breakdown voltage transistor 27. A source electrode 9 is connected to the source diffusion layer 7.

A lightly doped layer 15 is provided at the end of the gate electrode 5 facing the source diffusion layer 7,
An electric field relaxation oxide film 41 made of a silicon oxide film having a thickness of about 700 nm is provided on the upper part of FIG. This electric field relaxation oxide film 41
Is provided so as to overlap a part of the gate electrode 5. As an impurity used for the lightly doped layer 15, a phosphorus atom is used for an N-channel high breakdown voltage transistor, and a boron atom is used for a P-channel high breakdown voltage transistor.

The drain diffusion layer 11 is provided on the other end where the gate electrode 5 of the electric field relaxation oxide film 41 and the field oxide film 39 match.
And a drain electrode 13 is connected to the drain diffusion layer 11. The impurities used for the drain diffusion layer 11 are as follows:
Phosphorus atoms are used for an N-channel high breakdown voltage transistor, and boron atoms are used for a P-channel high breakdown voltage transistor.

The low breakdown voltage transistor 29 is formed on the semiconductor substrate 1
The gate insulating film 3 is provided on the upper surface of the substrate. As the gate insulating film 3, a silicon oxide film having a thickness of about 80 nm is used. A gate electrode 5 made of polysilicon having a thickness of about 450 nm is provided on the gate insulating film 3, and a source diffusion layer 7 and a drain diffusion layer 11 are provided in a region where the gate electrode 5 and the field oxide film 39 match.

As an impurity used for the source diffusion layer 7 and the drain diffusion layer 11, a phosphorus atom is used for an N-channel type low breakdown voltage transistor, and a boron atom is used for a P-channel type low breakdown voltage transistor. Source diffusion layer 7
And the drain diffusion layer 11 has a source electrode 9
And the drain electrode 13 are connected.

Next, in the element isolation region, a field oxide film 39 made of a silicon oxide film having a thickness of about 700 nm is provided on the semiconductor substrate 1, and a field stopper layer 19 is provided thereunder. An insulating film 43 containing phosphorus and boron is provided as an interlayer insulating film. The insulating film 43 has contact holes for connecting the source diffusion layer 7 and the source electrode 9 and the drain diffusion layer 11 and the drain electrode 13.

In the semiconductor device of the present invention, the ion implantation layer constituting the lightly doped layer 15 provided below the electric field relaxation oxide film 41 of the high breakdown voltage transistor 27 is provided as the field stopper layer 19 in the element isolation region. At this time, the surface impurity concentration of the ion implantation layer constituting the lightly doped layer and the field stopper layer is about 1 × 10 17 cm ⁻³ . The surface impurity concentration of the well is about 1 × 10 16 c
m ^-3 .

By using the ion-implanted layer constituting the lightly doped layer 15 as the field stopper layer, the inversion voltage in the element isolation region does not fall below the power supply voltage, and the leakage current between the elements does not increase. .

[Description of Manufacturing Method of Semiconductor Device: FIGS. 3 to 6 and FIGS. 14 to 20] Next, a manufacturing method for forming the semiconductor device structure shown in FIG. 1 will be described with reference to the drawings. . 3 to 6 and FIGS. 14 to 20
4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

First, as shown in FIG. 3, a heat treatment is performed on the surface of the N-type or P-type semiconductor substrate 1 at a temperature of 1000 ° C. for about 100 minutes in a humidified oxidizing atmosphere. A silicon oxide film 17 of about 0.5 μm is formed. Next, a photoresist (not shown) is formed on the entire upper surface of the silicon oxide film 17 by a spin coating method.
Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that a region for forming an N-type well is opened.

Subsequently, using the photoresist as an etching mask, the silicon oxide film 17 in the photoresist opening is completely removed by using hydrofluoric acid (HF) as an etching solution. Thereafter, the photoresist is removed using sulfuric acid (H2 SO4).

Next, as shown in FIG. 4, the implantation energy is 100 KeV and the implantation dose is 6 × 10 ¹² cm ^{−2 by} using the silicon oxide film 17 as an ion implantation prevention film.
The N-type impurity 31 is ion-implanted under such a condition. A phosphorus atom is used as the N-type impurity. Thereafter, the silicon oxide film 17 is completely removed using hydrofluoric acid.

Next, as shown in FIG. 5, a photoresist 25 is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Next, an exposure process using a predetermined photomask,
A development process is performed, and the photoresist 25 is patterned so that a region for forming a P-type well is opened. Subsequently, the P-type impurity 35 is ion-implanted using the photoresist 25 as an ion implantation preventing film under the conditions of an implantation energy of 60 KeV and an implantation dose of about 1.5 × 10 ¹³ cm ⁻² . As the P-type impurity 35, a boron atom is used. Thereafter, the photoresist 25 is removed using sulfuric acid.

Next, as shown in FIG. 6, heat treatment is performed under the conditions of an oxygen flow rate of 0.5 sccm, a nitrogen flow rate of 8.5 sccm, a temperature of 1140 ° C., and a time period of about 70 hours to form an N-type impurity 31 and a P-type impurity. The impurity 35 is diffused deeply into the semiconductor substrate 1 so that the N-type well 23 and the P-type well 2
Form one.

Next, as shown in FIG. 14, a photoresist 25 is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist 25 is patterned so that regions where the N-type lightly doped layer and the field stopper layer are formed are opened.

Subsequently, using the photoresist 25 as an ion implantation preventing film, the implantation energy is 25 KeV,
An N-type impurity 31 is ion-implanted under the condition of a dose of about 8 × 10 ¹² cm ⁻² . As the N-type impurity 31, a phosphorus atom is used. Thereafter, the photoresist 25 is removed using sulfuric acid.

Next, as shown in FIG. 15, a photoresist 25 is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist 25 is patterned so that a region where a P-type lightly doped layer and a field stopper layer are formed is opened.

Subsequently, using the photoresist 25 as an ion implantation preventing film, the implantation energy is 50 KeV,
P-type impurities 35 are ion-implanted under the conditions of an implantation dose of about 5 × 10 ¹³ cm ⁻² . As the P-type impurity 35, a boron atom is used. Thereafter, the photoresist 25 is removed using sulfuric acid.

Next, as shown in FIG. 16, the N-type impurity 31 and the P-type impurity 35 are diffused by applying a heat treatment at a temperature of 1100 ° C. for a time period of about 15 hours in a nitrogen atmosphere, so that the N-type and P-type impurities 35 are diffused. The light-doped layer 15 and the field stopper layer 19 are formed.

Subsequently, a silicon nitride film 37 is formed on the entire upper surface of the semiconductor substrate 1 by a chemical vapor deposition (CVD) method using dichlorosilane (SiH2 Cl2) and ammonia (NH3) as a reaction gas. Further, a photoresist 25 is formed on the entire upper surface of the silicon nitride film 37 by a spin coating method.

Subsequently, an exposure process and a development process are performed using a predetermined photomask, and a photoresist 25 is formed so that a region for forming an electric field relaxation oxide film is opened in an element isolation region and a region for forming a high breakdown voltage transistor. Perform patterning. Further, using the patterned photoresist 25 as an etching mask, the silicon nitride film 37 in the photoresist opening is formed by reactive ion etching using a mixed gas of carbon tetrafluoride (CF4) and oxygen (O2) as an etching gas. Etch until completely removed. Thereafter, the photoresist is removed using sulfuric acid.

Next, as shown in FIG.
By performing an oxidation process in an oxygen atmosphere at 0 ° C. for about 3 hours, a region where the silicon nitride film 37 does not exist is selectively oxidized, and a field oxide film 39 and an electric field relaxation oxide film 41 are formed. Then, phosphoric acid (H3PO4
), The silicon nitride film 37 is removed.

Next, a heat treatment is performed for about 2 hours in an oxygen atmosphere at a temperature of 1000 ° C., so that a film thickness of 80 nm
A gate oxide film (not shown) made of a silicon oxide film is formed. Thereafter, polysilicon (not shown) as a gate electrode material is formed on the entire upper surface of the semiconductor substrate 1 by a CVD method using monosilane (SiH4) as a reaction gas.

Thereafter, a photoresist (not shown) is formed on the entire upper surface of the polysilicon by a spin coating method. Subsequently, using a predetermined photomask, an exposure process and a development process are performed, and the photoresist is patterned so as to open an area other than a region to be a gate electrode.

Next, using the photoresist as an etching mask, reactive ion etching using sulfur hexafluoride (SF6) and oxygen (O2) as a reaction gas is performed until the polysilicon in the photoresist opening is completely removed. Etching is performed to form a gate electrode (not shown). Thereafter, the photoresist is removed using sulfuric acid.

Next, as shown in FIG. 18, a photoresist 25 is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method. Subsequently, in order to form a drain diffusion layer and a source diffusion layer having N-type conductivity, an exposure process and a development process are performed using a predetermined photomask.
5 is patterned so as to open an area where an N-channel type low breakdown voltage transistor and a high breakdown voltage transistor are formed.

Subsequently, the photoresist 25 is used as an ion implantation preventing film, and the implantation energy is 100 Ke.
Under the ion implantation conditions of V and an implantation dose of about 5 × 10 ¹⁵ cm ⁻² , phosphorus atoms, which are N-type impurities, are ion-implanted into the entire surface of the semiconductor substrate 1, and the gate electrode 3, the field oxide film 39 and the electric field relaxation oxidation P-type well 21 matching film 41
The source diffusion layer 7 and the drain diffusion layer 1 having N-type conductivity
Form one. After that, the photoresist 25 is removed.

Similarly, a photoresist (not shown) is formed on the entire upper surface of the semiconductor substrate 1 by a spin coating method in order to form a drain diffusion layer and a source diffusion layer of P-type conductivity. Subsequently, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that regions for forming the P-channel type low breakdown voltage transistor and the high breakdown voltage transistor are opened.

Subsequently, using a photoresist as an ion implantation blocking film, boron atoms, which are P-type impurities, are deposited on the entire surface of the semiconductor substrate 1 under ion implantation conditions of implantation energy of 100 KeV and implantation dose of about 5 × 10 ¹⁵ cm ^−2. The gate electrode 3 and the field oxide film 39 are implanted by ion implantation.
The source diffusion layer 7 and the drain diffusion layer 11 having the P-type conductivity are formed in the N-type well 23 which matches with the electric field relaxation oxide film 41. Thereafter, the photoresist is removed using sulfuric acid.

Next, as shown in FIG. 19, monosilane (SiH4) and phosphine (PH3) are used as reaction gases.
Then, an insulating film 43 made of a silicon oxide film containing phosphorus and boron as impurities is formed on the entire surface to a thickness of about 0.5 μm by a CVD method using diborane (B2 H6). Thereafter, heat treatment is performed in a nitrogen atmosphere at a temperature of 900 ° C. for about 30 minutes. As a result, the impurities ion-implanted into the drain diffusion layer 11 and the source diffusion layer 7 are electrically activated. The heat treatment in this nitrogen atmosphere
The surface of the insulating film 43 is also flattened.

Next, a photoresist (not shown) is formed on the entire upper surface of the insulating film 43 by a spin coating method. Subsequently, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that the contact holes are opened.

Subsequently, carbon tetrafluoride (CF) was used as the reaction gas.
4), methane trifluoride (CHF3) and helium (He)
Is etched until the insulating film 43 in the photoresist opening is completely removed, thereby forming a contact hole (not shown). Thereafter, the photoresist is removed using sulfuric acid.

Subsequently, as shown in FIG.
A metal electrode material (not shown) for forming a drain electrode and a source electrode is formed in a film thickness of about 1 μm on the entire upper surface of the substrate by sputtering. Aluminum is used as the metal electrode material.

Next, a photoresist (not shown) is formed on the entire upper surface of the metal electrode material (not shown) by a spin coating method. Subsequently, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that openings are formed in regions other than the regions to be the drain electrode and the source electrode.

Subsequently, using a photoresist (not shown) as an etching mask, the metal electrode material in the photoresist opening is removed by reactive ion etching using boron trichloride (BCl3) and chlorine (Cl2) as a reaction gas. Etch until completely removed, drain electrode 1
3 and a source electrode 9 are formed. Then, nitric acid (H2PO
4) Remove the photoresist using.

As a result, as shown in FIG. 1, the ion-implanted layer constituting the lightly doped layer 15 provided in the high breakdown voltage transistor 27 and the field stopper layer 19 in the element isolation region are formed to be the same.

According to the manufacturing method described in the embodiment of the present invention, a high-voltage transistor and a low-voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate. The ion implantation layers constituting the layer 15 and the field stopper layer 19 in the element isolation region are formed to be the same. If a semiconductor device having this structure is used, the field stopper layer 19 can be formed in the same step and with the same photomask as the lightly doped layer 15, so that the N-type and P-type field stopper layers 19 are formed in the prior art. The necessary four steps and two photomasks can be eliminated. Further, the inversion voltage of the element isolation region does not fall below the power supply voltage, and the leakage current between the elements does not increase.

In the embodiment of the present invention described above,
In order to diffuse the light dope layer 15 and the field stopper layer 19, a temperature of 1100 ° C.
Even if the heat treatment is performed for about an hour, but the heat treatment is not performed, and the diffusion is performed by a heat treatment for forming a field oxide film and an electric field relaxation oxide film in a later step, the same effect as that of the embodiment of the present invention can be obtained. Is obtained.

In the embodiment of the present invention described above, an ion implantation process for forming the N-type lightly doped layer 15 and the field stopper layer 19, and the P-type lightly doped layer 15 and the field stopper layer 19 After the ion implantation process for forming the light-doped layer 1
5 and a field stopper layer 19, a heat treatment was performed in a nitrogen atmosphere at a temperature of 1100 ° C. for about 15 hours.
The same effect as in the embodiment of the present invention can be obtained even when the ion implantation is performed only after the ion implantation step for forming the field stopper layer 19.

In the embodiment of the present invention described above, the ion implantation process for forming the N-type lightly doped layer 15 and the field stopper layer 19, and the P-type lightly doped layer 15 and the field stopper layer 19 After the ion implantation process for forming the light-doped layer 1
A heat treatment was performed in a nitrogen atmosphere at a temperature of 1100 ° C. for about 15 hours in order to diffuse the N.sub.5 and the field stopper layer 19, but ion implantation for forming the N-type lightly doped layer 15 and the field stopper layer 19 was performed. After the process,
A heat treatment at a temperature of 1100 ° C. for about 10 hours is performed in a nitrogen atmosphere. Further, after an ion implantation process for forming a P-type lightly doped layer 15 and a field stopper layer 19, the heat treatment is performed at a temperature of 1000 ° C. in a nitrogen atmosphere. Even when the heat treatment is performed for about 10 hours, the same effect as the embodiment of the present invention can be obtained.

In the embodiment of the present invention described above,
The electric field relaxation oxide film 41 and the lightly doped layer 15 are provided only at one end of the gate electrode 3 of the high breakdown voltage transistor 27. As shown in FIG. Even when the light-doped layer 41 and the light-doped layer 15 are provided, the same effects as those of the embodiment of the present invention can be obtained. As an application of the high breakdown voltage transistor having this structure, there is a transmission gate. Also, a method of manufacturing a high breakdown voltage transistor having this structure is described in FIG.
4, FIG. 15 and FIG.
Need only be patterned so as to form the electric field relaxation oxide film 41 and the lightly doped layer 15 at both ends of the gate electrode 3 of the high breakdown voltage transistor 27.

In the embodiment of the present invention described above, the low breakdown voltage transistor and the high breakdown voltage transistor are described as complementary transistors. However, the low breakdown voltage transistor is formed of a complementary transistor, and the high breakdown voltage transistor is N-type.
The same effect as in the embodiment of the present invention can be obtained also when the transistor is formed only with the channel type transistor.

In the embodiment of the present invention described above, the low breakdown voltage transistor and the high breakdown voltage transistor are described as complementary transistors. However, the low breakdown voltage transistor is formed of a complementary transistor, and the high breakdown voltage transistor is
The same effect as in the embodiment of the present invention can be obtained also when the transistor is formed only with the channel type transistor.

In the embodiment of the present invention described above, the low breakdown voltage transistor and the high breakdown voltage transistor are described as complementary transistors. However, the high breakdown voltage transistor is formed of a complementary transistor, and the low breakdown voltage transistor is N-type.
The same effect as in the embodiment of the present invention can be obtained also when the transistor is formed only with the channel type transistor.

In the embodiment of the present invention described above, the low breakdown voltage transistor and the high breakdown voltage transistor are described as complementary transistors. However, the high breakdown voltage transistor is formed of a complementary transistor, and the low breakdown voltage transistor is
The same effect as in the embodiment of the present invention can be obtained also when the transistor is formed only with the channel type transistor.

[0112]

As apparent from the above description, the semiconductor device and the method of manufacturing the same according to the present invention is a semiconductor device in which a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate. The ion implantation layers forming the lightly doped layer of the high breakdown voltage transistor and the field stopper layer of the element isolation region are formed to be the same.

When the semiconductor device of the present invention having this structure is used, the lightly doped layer and the field stopper layer of the same conductivity type can be formed in the same step and the same photomask, so that the number of steps and the number of photomasks can be reduced. Can be. At this time, the inversion voltage of the element isolation region does not fall below the power supply voltage, and the leakage current does not increase.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure and a manufacturing method of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a structure and a manufacturing method of a semiconductor device according to a conventional technique.

FIG. 3 is a cross-sectional view illustrating a structure and a manufacturing method of a semiconductor device according to an embodiment of the present invention and a conventional technique.

FIG. 4 is a cross-sectional view illustrating a structure and a manufacturing method of a semiconductor device according to an embodiment of the present invention and a conventional technique.

FIG. 5 is a cross-sectional view showing a structure and a manufacturing method of a semiconductor device according to an embodiment of the present invention and a conventional technique.

FIG. 6 is a cross-sectional view illustrating a structure and a manufacturing method of a semiconductor device according to an embodiment of the present invention and a conventional technique.

FIG. 7 is a cross-sectional view showing a structure and a manufacturing method of a semiconductor device according to a conventional technique.

FIG. 8 is a cross-sectional view illustrating a structure and a manufacturing method of a semiconductor device according to a conventional technique.

FIG. 9 is a cross-sectional view showing a structure and a manufacturing method of a semiconductor device according to a conventional technique.

FIG. 10 is a cross-sectional view illustrating a structure and a manufacturing method of a semiconductor device according to a conventional technique.

FIG. 11 is a cross-sectional view illustrating a structure and a manufacturing method of a semiconductor device according to a conventional technique.

FIG. 12 is a cross-sectional view illustrating a structure and a manufacturing method of a semiconductor device according to a conventional technique.

FIG. 13 is a cross-sectional view showing a structure and a manufacturing method of a semiconductor device according to a conventional technique.

FIG. 14 is a cross-sectional view showing a structure and a manufacturing method of the semiconductor device according to the embodiment of the present invention;

FIG. 15 is a cross-sectional view showing a structure and a manufacturing method of the semiconductor device according to the embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a structure and a manufacturing method of the semiconductor device according to the embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a structure and a manufacturing method of the semiconductor device according to the embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a structure and a manufacturing method of the semiconductor device according to the embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a structure and a manufacturing method of the semiconductor device according to the embodiment of the present invention;

FIG. 20 is a cross-sectional view showing a structure and a manufacturing method of the semiconductor device according to the embodiment of the present invention;

FIG. 21 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 3 Gate insulating film 5 Gate electrode 7 Source diffusion layer 9 Source electrode 11 Drain diffusion layer 13 Drain electrode 15 Lightly doped layer 17 Silicon oxide film 19 Field stopper layer 21 P-type well 23 N-type well 25 Photoresist 27 High voltage transistor Reference Signs List 29 low breakdown voltage transistor 31 N-type impurity 35 P-type impurity 37 silicon nitride film 39 field oxide film 41 electric field relaxation oxide film 43 insulating film

Claims (20)

[Claims] 1. A semiconductor device in which a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate, wherein the high breakdown voltage transistor includes a gate insulating film provided on the semiconductor substrate and a gate. A gate electrode provided above the insulating film; a source diffusion layer provided at an end of the gate electrode; a source electrode connected to the source diffusion layer; and a drain diffusion provided at an end of the gate electrode facing the source diffusion layer. Layer, a drain electrode connected to the drain diffusion layer, a lightly doped layer provided on the drain diffusion layer comprising an impurity diffusion layer having an impurity concentration lower than that of the drain diffusion layer, and a gate electrode and the lightly doped layer. The low voltage transistor includes a gate insulating film provided on a semiconductor substrate and an upper portion of the gate insulating film. A gate electrode, a source diffusion layer provided at one end of the gate electrode, a source electrode connected to the source diffusion layer, a drain diffusion layer provided at an end of the gate electrode facing the source diffusion layer, and a connection to the drain diffusion layer A semiconductor device, comprising: a drain electrode formed in a light-doped layer and a field stopper layer in an element isolation region. 2. A semiconductor device in which a high breakdown voltage transistor and a low breakdown voltage transistor driven by different power supply voltages are formed on the same semiconductor substrate, wherein the high breakdown voltage transistor includes a gate insulating film provided on the semiconductor substrate and a gate. A gate electrode provided above the insulating film; a source diffusion layer provided at an end of the gate electrode; a source electrode connected to the source diffusion layer; and a drain diffusion provided at an end of the gate electrode facing the source diffusion layer. A layer, a drain electrode connected to the drain diffusion layer, a lightly doped layer provided on the drain diffusion layer and the source diffusion layer comprising an impurity diffusion layer having an impurity concentration lower than that of the drain diffusion layer and the source diffusion layer, and a gate. An electric field relaxing oxide film provided between the electrode and the lightly doped layer is provided. A film, a gate electrode provided on the gate insulating film, a source diffusion layer provided at an end of the gate electrode, a source electrode connected to the source diffusion layer, and an end of the gate electrode facing the source diffusion layer. A semiconductor device, comprising: a drain diffusion layer provided in a portion; and a drain electrode connected to the drain diffusion layer, wherein an ion implantation layer constituting a lightly doped layer and a field stopper layer in an element isolation region is the same. apparatus. 3. A step of selectively implanting P-type impurity atoms into a semiconductor substrate to form a P-type well, and a step of selectively implanting N-type impurity atoms into an N-type well. Patterning the photoresist so that the regions for forming the lightly doped layer in the N-channel region and the field stopper layer in the P-channel region are opened, and using the photoresist as an ion implantation blocking film in the region for forming the lightly doped layer and the field stopper layer. A step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer by ion-implanting N-type impurity atoms and performing a heat treatment; a lightly doped layer of P-channel region and a field stopper of N-channel region Pattern the photoresist so that the area where the layer is to be formed is opened, and block the photoresist for ion implantation. A step of ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are formed as a stop film to simultaneously form a P-type light-doped layer and a field stopper layer; And a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor by performing photoetching processing Forming a silicon oxide film on the surface within the silicon nitride film opening by performing an oxidation process in an oxidizing atmosphere; etching the silicon nitride film to remove the silicon nitride film; A step of patterning the gate electrode by performing a photo-etching process, Forming a drain diffusion layer and a source diffusion layer of a high-voltage transistor and a low-voltage transistor by selectively ion-implanting impurity atoms of the same conductivity type as that of the light-doped layer; forming an insulating film on the entire surface; A step of forming a contact hole by performing, and a step of patterning the drain electrode and the source electrode by forming a drain electrode and a source electrode material on the entire surface and performing a photoetching process. Production method. 4. A step of selectively implanting P-type impurity atoms into a semiconductor substrate to form a P-type well, and a step of selectively implanting N-type impurity atoms into an N-type well. Patterning the photoresist so that the regions for forming the lightly doped layer in the N-channel region and the field stopper layer in the P-channel region are opened, and using the photoresist as an ion implantation blocking film in the region for forming the lightly doped layer and the field stopper layer. A step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer by ion-implanting N-type impurity atoms and performing a heat treatment; a lightly doped layer of P-channel region and a field stopper of N-channel region Pattern the photoresist so that the area where the layer is to be formed is opened, and block the photoresist for ion implantation. A step of ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are formed as a stop film to simultaneously form a P-type light-doped layer and a field stopper layer; And an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor by performing photoetching processing. A step of opening the silicon nitride film in the region, a step of forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere, and a step of etching and removing the silicon nitride film; A gate electrode material is formed on the entire surface and the gate electrode is patterned by photoetching. Forming a drain diffusion layer and a source diffusion layer of a high breakdown voltage transistor and a low breakdown voltage transistor by selectively ion-implanting impurity atoms of the same conductivity type as a lightly doped layer; and forming an insulating film over the entire surface. Forming a contact hole by performing a photo-etching process; and patterning a drain electrode and a source electrode by performing a photo-etching process by forming a drain electrode and a source electrode material on the entire surface. A method for manufacturing a semiconductor device. 5. A step of selectively implanting P-type impurity atoms into a N-type semiconductor substrate to form a P-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. Patterning the photoresist so that the region where the layer is formed is opened, ion-implanting N-type impurity atoms into the region where the light dope layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film, and performing heat treatment, Forming a lightly doped layer of N-type conductivity and a field stopper layer at the same time; patterning the photoresist so that a region for forming the lightly doped layer of the P channel region and the field stopper layer of the N channel region is opened; Light-doped layer and field stopper layer Ion-implanting P-type impurity atoms into a region to be formed, and simultaneously forming a lightly doped layer and a field stopper layer of P-type conductivity; and forming a silicon nitride film over the entire surface and performing photoetching. A step of opening a silicon nitride film in a region for forming an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a side of a drain diffusion layer of a gate electrode in an isolation region and a high breakdown voltage transistor; Forming a silicon oxide film on the surface in the opening of the silicon nitride film, etching the silicon nitride film, and removing the silicon nitride film. Patterning the electrode and selectively implanting impurity atoms of the same conductivity type as the lightly doped layer Forming a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor; forming an insulating film over the entire surface; and performing a photoetching process to form a contact hole; Patterning a drain electrode and a source electrode by forming an electrode material on the entire surface and performing a photoetching process. 6. A step of selectively implanting P-type impurity atoms into a N-type semiconductor substrate to form a P-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. Patterning the photoresist so that the region where the layer is formed is opened, ion-implanting N-type impurity atoms into the region where the light dope layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film, and performing heat treatment, Forming a lightly doped layer of N-type conductivity and a field stopper layer at the same time; patterning the photoresist so that a region for forming the lightly doped layer of the P channel region and the field stopper layer of the N channel region is opened; Light-doped layer and field stopper layer Ion-implanting P-type impurity atoms into a region to be formed, and simultaneously forming a lightly doped layer and a field stopper layer of P-type conductivity; and forming a silicon nitride film over the entire surface and performing photoetching. Opening the silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than the gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode in the isolation region and the high breakdown voltage transistor is formed; A step of forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation treatment in an atmosphere; a step of etching and removing the silicon nitride film; Performing a gate electrode patterning process and selecting impurity atoms of the same conductivity type as the lightly doped layer. Selectively implanting ions to form a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor; and forming a contact hole by forming an insulating film over the entire surface and performing photoetching. Patterning the drain electrode and the source electrode by forming a drain electrode and a source electrode material on the entire surface and performing a photoetching process. 7. A step of selectively ion-implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. Patterning the photoresist so that the region where the layer is formed is opened, ion-implanting N-type impurity atoms into the region where the light dope layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film, and performing heat treatment, Forming a lightly doped layer of N-type conductivity and a field stopper layer at the same time; patterning the photoresist so that a region for forming the lightly doped layer of the P channel region and the field stopper layer of the N channel region is opened; Light-doped layer and field stopper layer Ion-implanting P-type impurity atoms into a region to be formed, and simultaneously forming a lightly doped layer and a field stopper layer of P-type conductivity; and forming a silicon nitride film over the entire surface and performing photoetching. A step of opening a silicon nitride film in a region for forming an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a side of a drain diffusion layer of a gate electrode in an isolation region and a high breakdown voltage transistor; Forming a silicon oxide film on the surface in the opening of the silicon nitride film, etching the silicon nitride film, and removing the silicon nitride film. Patterning the electrode and selectively implanting impurity atoms of the same conductivity type as the lightly doped layer Forming a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor; forming an insulating film over the entire surface; and performing a photoetching process to form a contact hole; Patterning a drain electrode and a source electrode by forming an electrode material on the entire surface and performing a photoetching process. 8. A step of selectively implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. Patterning the photoresist so that the region where the layer is formed is opened, ion-implanting N-type impurity atoms into the region where the light dope layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film, and performing heat treatment, Forming a lightly doped layer of N-type conductivity and a field stopper layer at the same time; patterning the photoresist so that a region for forming the lightly doped layer of the P channel region and the field stopper layer of the N channel region is opened; Light-doped layer and field stopper layer Ion-implanting P-type impurity atoms into a region to be formed, and simultaneously forming a lightly doped layer and a field stopper layer of P-type conductivity; and forming a silicon nitride film over the entire surface and performing photoetching. Opening the silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than the gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode in the isolation region and the high breakdown voltage transistor is formed; A step of forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation treatment in an atmosphere; a step of etching and removing the silicon nitride film; Performing a gate electrode patterning process and selecting impurity atoms of the same conductivity type as the lightly doped layer. Forming a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor by ion implantation, forming an insulating film over the entire surface, and performing a photoetching process to form a contact hole; Forming a drain electrode and a source electrode material on the entire surface and patterning the drain electrode and the source electrode by performing a photoetching process. 9. A step of selectively implanting P-type impurity atoms into a semiconductor substrate to form a P-type well, and a step of selectively implanting N-type impurity atoms to form an N-type well. Patterning the photoresist so that the regions for forming the lightly doped layer in the N-channel region and the field stopper layer in the P-channel region are opened, and using the photoresist as an ion implantation blocking film in the region for forming the lightly doped layer and the field stopper layer. A step of ion-implanting N-type impurity atoms to simultaneously form a lightly doped layer of N-type conductivity and a field stopper layer, and a region for forming a lightly doped layer of a P channel region and a field stopper layer of an N channel region. Pattern the photoresist so as to open it, and use the photoresist as a light doping layer as an ion implantation blocking film. Ion implantation of P-type impurity atoms into a region where a field stopper layer is to be formed, and simultaneously forming a lightly doped layer of P-type conductivity and a field stopper layer; and forming a silicon nitride film on the entire surface and photoetching. Opening a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side of the gate electrode in the element isolation region and the high breakdown voltage transistor by performing the processing; A step of forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere, a step of etching and removing the silicon nitride film, and a step of forming a gate electrode material over the entire surface and photoetching Patterning the gate electrode by performing the process, and the same conductivity type as the lightly doped layer Steps of selectively implanting impurity atoms to form a drain diffusion layer and a source diffusion layer of a high breakdown voltage transistor and a low breakdown voltage transistor, and forming a contact hole by forming an insulating film over the entire surface and performing a photoetching process And a step of patterning the drain electrode and the source electrode by forming a material of the drain electrode and the source electrode over the entire surface and performing a photoetching process. 10. A step of selectively implanting P-type impurity atoms into a semiconductor substrate to form a P-type well, and a step of selectively implanting N-type impurity atoms to form an N-type well. Patterning the photoresist so that the region for forming the lightly doped layer in the N-channel region and the region for forming the field stopper layer in the P-channel region are opened; A step of ion-implanting N-type impurity atoms to simultaneously form a lightly doped layer of N-type conductivity and a field stopper layer, and a region for forming a lightly doped layer of a P channel region and a field stopper layer of an N channel region. Photoresist is patterned so as to open, and the photoresist is lightly doped as ion implantation stop film. Ion-implanting P-type impurity atoms into a region where a layer and a field stopper layer are to be formed to simultaneously form a lightly doped layer having a P-type conductivity and a field stopper layer; forming a silicon nitride film over the entire surface; By performing an etching process, a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a drain diffusion layer side and a source diffusion layer side of a gate electrode in an element isolation region and a high breakdown voltage transistor is formed. Forming a silicon oxide film on the surface within the silicon nitride film opening by performing an oxidation process in an oxidizing atmosphere; etching the silicon nitride film to remove the silicon nitride film; Patterning the gate electrode by photolithography and forming Forming a drain diffusion layer and a source diffusion layer of a high-breakdown-voltage transistor and a low-breakdown-voltage transistor by selectively ion-implanting impurity atoms of the same conductivity type as that of the conductive layer; Forming a drain hole and a source electrode material on the entire surface and patterning the drain electrode and the source electrode by performing a photoetching process. Manufacturing method. 11. A step of selectively implanting P-type impurity atoms into a N-type semiconductor substrate to form a P-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. The photoresist is patterned so that the region where the layer is formed is opened, and N-type impurity atoms are ion-implanted into the region where the light dope layer and the field stopper layer are to be formed using the photoresist as an ion implantation blocking film, and the conductivity type is N-type. A step of simultaneously forming a lightly doped layer and a field stopper layer; and a step of patterning a photoresist so as to open a region for forming a lightly doped layer in a P channel region and a field stopper layer in an N channel region, and using the photoresist as an ion implantation blocking film. P-type impurities are formed in the regions where the light dope layer and the field stopper layer are formed. A step of simultaneously implanting atoms to form a lightly doped layer of P-type conductivity and a field stopper layer, and a step of forming a silicon nitride film over the entire surface and performing photo-etching to form an element isolation region and a high breakdown voltage transistor. A step of opening a silicon nitride film in a region for forming an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a drain diffusion layer side of a gate electrode; A step of forming a silicon oxide film on the surface in the opening, a step of etching and removing the silicon nitride film, a step of forming a gate electrode material over the entire surface, and patterning the gate electrode by performing photoetching processing; High-voltage transistors with selective ion implantation of impurity atoms of the same conductivity type as the lightly doped layer Forming a drain diffusion layer and a source diffusion layer of a low-breakdown-voltage transistor, forming an insulating film over the entire surface and forming a contact hole by performing photoetching, and applying a drain electrode and a source electrode material over the entire surface. Forming a drain electrode and a source electrode by performing a photoetching process, and a method of manufacturing the semiconductor device. 12. A step of selectively implanting P-type impurity atoms into a N-type semiconductor substrate to form a P-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. The photoresist is patterned so that the region where the layer is formed is opened, and N-type impurity atoms are ion-implanted into the region where the light dope layer and the field stopper layer are to be formed using the photoresist as an ion implantation blocking film, and the conductivity type is N-type. A step of simultaneously forming a lightly doped layer and a field stopper layer; and a step of patterning a photoresist so as to open a region for forming a lightly doped layer in a P channel region and a field stopper layer in an N channel region, and using the photoresist as an ion implantation blocking film. P-type impurities are formed in the regions where the light dope layer and the field stopper layer are formed. A step of simultaneously implanting atoms to form a lightly doped layer of P-type conductivity and a field stopper layer, and a step of forming a silicon nitride film over the entire surface and performing photo-etching to form an element isolation region and a high breakdown voltage transistor. A step of opening a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode is formed; Forming a silicon oxide film on the surface inside the silicon nitride film opening, etching the silicon nitride film and removing the silicon nitride film, forming a gate electrode material on the entire surface, and performing photoetching to form the gate electrode. Patterning, and selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer, Forming a drain diffusion layer and a source diffusion layer of a high-voltage transistor and a low-voltage transistor, forming an insulating film over the entire surface and forming a contact hole by performing a photoetching process, and forming a drain electrode and a source electrode material. Forming a drain electrode and a source electrode by performing photoetching on the entire surface and performing a photoetching process. 13. A step of selectively ion-implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. The photoresist is patterned so that the region where the layer is formed is opened, and N-type impurity atoms are ion-implanted into the region where the light dope layer and the field stopper layer are to be formed using the photoresist as an ion implantation blocking film, and the conductivity type is N-type. Forming a lightly doped layer and a field stopper layer at the same time; patterning a photoresist so that a region for forming a lightly doped layer in a P channel region and a field stopper layer in an N channel region is opened; P-type impurities are formed in the regions where the light dope layer and the field stopper layer are formed. A step of simultaneously implanting atoms to form a lightly doped layer of P-type conductivity and a field stopper layer, and a step of forming a silicon nitride film over the entire surface and performing photo-etching to form an element isolation region and a high breakdown voltage transistor. A step of opening a silicon nitride film in a region for forming an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a drain diffusion layer side of a gate electrode; A step of forming a silicon oxide film on the surface in the opening, a step of etching and removing the silicon nitride film, a step of forming a gate electrode material over the entire surface, and patterning the gate electrode by performing photoetching processing; High-voltage transistors with selective ion implantation of impurity atoms of the same conductivity type as the lightly doped layer Forming a drain diffusion layer and a source diffusion layer of a low-breakdown-voltage transistor, forming an insulating film over the entire surface and forming a contact hole by performing photoetching, and applying a drain electrode and a source electrode material over the entire surface. Forming a drain electrode and a source electrode by performing a photoetching process, and a method of manufacturing the semiconductor device. 14. A step of selectively ion-implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. The photoresist is patterned so that the region where the layer is formed is opened, and N-type impurity atoms are ion-implanted into the region where the light dope layer and the field stopper layer are to be formed using the photoresist as an ion implantation blocking film, and the conductivity type is N-type. A step of simultaneously forming a lightly doped layer and a field stopper layer; and a step of patterning a photoresist so as to open a region for forming a lightly doped layer in a P channel region and a field stopper layer in an N channel region, and using the photoresist as an ion implantation blocking film. P-type impurities are formed in the regions where the light dope layer and the field stopper layer are formed. A step of simultaneously implanting atoms to form a lightly doped layer of P-type conductivity and a field stopper layer, and a step of forming a silicon nitride film over the entire surface and performing photo-etching to form an element isolation region and a high breakdown voltage transistor. A step of opening a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on the drain diffusion layer side and the source diffusion layer side of the gate electrode, and performing an oxidation treatment in an oxidizing atmosphere Forming a silicon oxide film on the surface inside the silicon nitride film opening, etching the silicon nitride film and removing the silicon nitride film, forming a gate electrode material on the entire surface, and performing photoetching to form the gate electrode. Patterning, and selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer, Forming a drain diffusion layer and a source diffusion layer of a high-voltage transistor and a low-voltage transistor, forming an insulating film over the entire surface and forming a contact hole by performing a photoetching process, and forming a drain electrode and a source electrode material. Forming a drain electrode and a source electrode by performing photoetching on the entire surface and performing a photoetching process. 15. A step of selectively implanting P-type impurity atoms into a semiconductor substrate to form a P-type well, and a step of selectively implanting N-type impurity atoms into an N-type well. Patterning the photoresist so that the regions for forming the lightly doped layer in the N-channel region and the field stopper layer in the P-channel region are opened, and using the photoresist as an ion implantation blocking film in the region for forming the lightly doped layer and the field stopper layer. A step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer by ion-implanting N-type impurity atoms and performing a heat treatment; a lightly doped layer of P-channel region and a field stopper of N-channel region Pattern the photoresist so that the area where the layer is formed is opened, and ion-implant the photoresist Ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are formed as a blocking film, and performing heat treatment to simultaneously form a P-type light-doped layer and a field stopper layer with a conductivity type; A silicon nitride film is formed on the entire surface, and a photoetching process is performed to form an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a drain diffusion layer side of a gate electrode in an element isolation region and a high breakdown voltage transistor. Forming a silicon oxide film on the surface within the silicon nitride film opening by performing an oxidation process in an oxidizing atmosphere; and etching and removing the silicon nitride film. A gate electrode material is formed on the entire surface, and the gate electrode is formed by photoetching. Patterning; selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer to form drain diffusion layers and source diffusion layers of high-voltage transistors and low-voltage transistors; and forming an insulating film over the entire surface Forming a contact hole by performing a photo-etching process; and patterning a drain electrode and a source electrode by performing a photo-etching process by forming a drain electrode and a source electrode material on the entire surface. A method for manufacturing a semiconductor device. 16. A step of selectively implanting P-type impurity atoms into a semiconductor substrate to form a P-type well, and a step of selectively implanting N-type impurity atoms to form an N-type well. Patterning the photoresist so that the regions for forming the lightly doped layer in the N-channel region and the field stopper layer in the P-channel region are opened, and using the photoresist as an ion implantation blocking film in the region for forming the lightly doped layer and the field stopper layer. A step of simultaneously forming a lightly doped layer of N-type conductivity and a field stopper layer by ion-implanting N-type impurity atoms and performing a heat treatment; a lightly doped layer of P-channel region and a field stopper of N-channel region Pattern the photoresist so that the area where the layer is formed is opened, and ion-implant the photoresist Ion-implanting P-type impurity atoms into a region where a light-doped layer and a field stopper layer are formed as a blocking film, and performing heat treatment to simultaneously form a P-type light-doped layer and a field stopper layer with a conductivity type; An electric field comprising a silicon oxide film thicker than a gate insulating film provided on a drain diffusion layer side and a source diffusion layer side of a gate electrode in an element isolation region and a high breakdown voltage transistor in a device isolation region and a high breakdown voltage transistor by forming a silicon nitride film on the entire surface and performing photoetching treatment. Opening a silicon nitride film in a region where a relaxed oxide film is to be formed, forming a silicon oxide film on the surface within the silicon nitride film opening by performing oxidation in an oxidizing atmosphere, and etching the silicon nitride film. And forming a gate electrode material on the entire surface and performing photo-etching. A step of patterning the gate electrode more, a step of selectively ion-implanting impurity atoms of the same conductivity type as the lightly doped layer, and a step of forming a drain diffusion layer and a source diffusion layer of the high breakdown voltage transistor and the low breakdown voltage transistor; Forming a contact hole by performing a photo-etching process on the entire surface, and patterning the drain electrode and the source electrode by performing a photo-etching process by forming a drain electrode and a source electrode material on the entire surface, A method for manufacturing a semiconductor device, comprising: 17. A step of selectively implanting P-type impurity atoms into a N-type semiconductor substrate to form a P-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. Patterning the photoresist so that the region where the layer is formed is opened, ion-implanting N-type impurity atoms into the region where the light dope layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film, and performing heat treatment, Forming a lightly doped layer of N-type conductivity and a field stopper layer at the same time; patterning the photoresist so that a region for forming the lightly doped layer of the P channel region and the field stopper layer of the N channel region is opened; A light-doped layer and a field stopper layer P-type impurity atoms are ion-implanted into a region to be formed and heat treatment is performed to simultaneously form a P-type lightly doped layer and a field stopper layer; and a silicon nitride film is formed on the entire surface, Opening a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a drain diffusion layer side of a gate electrode in an element isolation region and a high breakdown voltage transistor by performing an etching process; Forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere; etching and removing the silicon nitride film; forming a gate electrode material on the entire surface; A step of patterning the gate electrode by performing an etching process, and an impurity of the same conductivity type as the lightly doped layer. The process of forming the drain diffusion layer and the source diffusion layer of the high-voltage transistor and the low-voltage transistor by selectively ion-implanting material atoms, and forming a contact hole by forming an insulating film over the entire surface and performing photoetching. And a step of patterning the drain electrode and the source electrode by forming a material of the drain electrode and the source electrode over the entire surface and performing a photoetching process. 18. A step of selectively implanting P-type impurity atoms into a N-type semiconductor substrate to form a P-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. Patterning the photoresist so that the region where the layer is formed is opened, ion-implanting N-type impurity atoms into the region where the light dope layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film, and performing heat treatment, Forming a lightly doped layer of N-type conductivity and a field stopper layer at the same time; patterning the photoresist so that a region for forming the lightly doped layer of the P channel region and the field stopper layer of the N channel region is opened; A light-doped layer and a field stopper layer P-type impurity atoms are ion-implanted into a region to be formed and heat treatment is performed to simultaneously form a P-type lightly doped layer and a field stopper layer; and a silicon nitride film is formed on the entire surface, By performing an etching process, a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a drain diffusion layer side and a source diffusion layer side of a gate electrode in an element isolation region and a high breakdown voltage transistor is formed. Forming a silicon oxide film on the surface within the silicon nitride film opening by performing an oxidation process in an oxidizing atmosphere; etching the silicon nitride film to remove the silicon nitride film; Patterning the gate electrode by performing photo-etching on the light-doped layer; Forming a drain diffusion layer and a source diffusion layer of a high breakdown voltage transistor and a low breakdown voltage transistor by selectively ion-implanting impurity atoms of the same conductivity type as above, and forming an insulating film over the entire surface and performing a photoetching process. Forming a contact hole by using the method described above, and patterning the drain electrode and the source electrode by forming a drain electrode and a source electrode material on the entire surface and performing a photoetching process. . 19. A step of selectively ion-implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. Patterning the photoresist so that the region where the layer is formed is opened, ion-implanting N-type impurity atoms into the region where the light dope layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film, and performing heat treatment, Forming a light-doped layer and a field stopper layer of N-type conductivity at the same time; A light-doped layer and a field stopper layer P-type impurity atoms are ion-implanted into a region to be formed and heat treatment is performed to simultaneously form a P-type lightly doped layer and a field stopper layer; and a silicon nitride film is formed on the entire surface, Opening a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a drain diffusion layer side of a gate electrode in an element isolation region and a high breakdown voltage transistor by performing an etching process; Forming a silicon oxide film on the surface inside the silicon nitride film opening by performing an oxidation treatment in an oxidizing atmosphere; etching and removing the silicon nitride film; forming a gate electrode material on the entire surface; A step of patterning the gate electrode by performing an etching process, and an impurity of the same conductivity type as the lightly doped layer. The process of forming the drain diffusion layer and the source diffusion layer of the high-voltage transistor and the low-voltage transistor by selectively ion-implanting material atoms, and forming a contact hole by forming an insulating film over the entire surface and performing photoetching. And a step of patterning the drain electrode and the source electrode by forming a material of the drain electrode and the source electrode over the entire surface and performing a photoetching process. 20. A step of selectively implanting N-type impurity atoms into a P-type semiconductor substrate to form an N-type well, a lightly doped layer in an N-channel region and a field stopper in a P-channel region. Patterning the photoresist so that the region where the layer is formed is opened, ion-implanting N-type impurity atoms into the region where the light dope layer and the field stopper layer are formed using the photoresist as an ion implantation blocking film, and performing heat treatment, Forming a lightly doped layer of N-type conductivity and a field stopper layer at the same time; patterning the photoresist so that a region for forming the lightly doped layer of the P channel region and the field stopper layer of the N channel region is opened; A light-doped layer and a field stopper layer P-type impurity atoms are ion-implanted into a region to be formed and heat treatment is performed to simultaneously form a P-type lightly doped layer and a field stopper layer; and a silicon nitride film is formed on the entire surface, By performing an etching process, a silicon nitride film in a region where an electric field relaxation oxide film made of a silicon oxide film thicker than a gate insulating film provided on a drain diffusion layer side and a source diffusion layer side of a gate electrode in an element isolation region and a high breakdown voltage transistor is formed. Forming a silicon oxide film on the surface within the silicon nitride film opening by performing an oxidation process in an oxidizing atmosphere; etching the silicon nitride film to remove the silicon nitride film; Patterning the gate electrode by performing photo-etching on the light-doped layer; A step of selectively ion-implanting impurity atoms of the same conductivity type to form a drain diffusion layer and a source diffusion layer of a high-breakdown-voltage transistor and a low-breakdown-voltage transistor; and forming an insulating film over the entire surface and performing photoetching. A method for manufacturing a semiconductor device, comprising: a step of forming a contact hole; and a step of patterning a drain electrode and a source electrode by forming a drain electrode and a source electrode material over the entire surface and performing a photoetching process.