JPH11354326A - Laminated inductor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated chip inductor for which the frequency of disconnection failures is suppressed by increasing reliable connection with external electrodes, and which can be manufactured with high productivity. SOLUTION: A laminated chip conductor is constituted so that the areas of conductors exposed on the end faces of the chip may become the product of the thickness from the first conductor layer 81 to the final conductor layer 85 and the width and length of an element by successively printing internal conductor layers 81-85, after forming such a conductor exposing pattern 10 that exposes conductors on both end faces of the chip in each internal conductor layers 81-85 in addition to a coil pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer chip inductor formed by a multilayer printing method, and more particularly to a structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art A surface mount type multilayer chip inductor mounted on a printed wiring board or the like is manufactured by a screen printing method in which a magnetic paste and a conductor paste are alternately printed on a screen plate.

FIG. 7 shows an example of the internal structure of a conventional surface mount type multilayer chip inductor. FIG. 9 is an exploded perspective view showing the configuration of FIG. A magnetic sheet (green sheet) 6 formed by processing a magnetic material such as ferrite is used as a substrate, and conductor layers 81 'to 8 are formed on the upper surface thereof by a conductor pattern for forming a coil shape by screen printing.
5 'is formed by printing. At this time, the screen plate on which the conductor pattern is formed is formed such that a plurality of coils are arranged in a grid pattern on one platen. By cutting into
A chip inductor can be obtained.

Further, a magnetic layer 11 is printed on the upper surfaces of the conductor layers 81 'to 85' in a magnetic pattern. This process is repeated alternately a plurality of times, and finally the green sheet 6 is superimposed. At this time, the magnetic pattern
A cutout window 9 is provided to connect upper and lower conductor layers 81 'to 85' sandwiching the magnetic layer. Thus, the coil conductor 3 is formed inside the magnetic body 2 by the conductor layers 81 'to 85'.

To obtain a desired number of turns, the number of laminations may be increased or decreased. A part of the conductor pattern of the first conductor layer 81 'and a part of the conductor pattern of the final conductor layer 85' are arranged so that the conductor is exposed on the end face of the chip. Become. At this time, the exposed surfaces of both ends of the conductor are connected to the first conductor layer 81 '(or the final conductor layer 8).
5 ′) is the area of one layer thickness. A conductor paste is applied from the outside to the both ends of the chip where the start and end of the coil conductor portion 3 are exposed so as to be electrically connected to the start and end 41 of the exposed coil, thereby forming external electrodes. You.

FIG. 7 is a perspective view of the orbiting coil 3 formed inside the magnetic body 2. 8 (a) to 8 (c).
2 shows the start and end portions 41 of the internal coil exposed on the chip end surface before the external electrodes are formed.

[0007]

In the multilayer chip inductor, disconnection due to disconnection with an external electrode for electrically connecting to a coil conductor portion formed inside the magnetic body is caused by reliability. Is a fatal problem.

(1) In a sheet cutting process for cutting a sheet laminated and printed on a surface plate into a dice pattern, the accuracy of a cutting machine;
Alternatively, due to a cutting error caused by a human error in positioning the origin by an operator, the end of the internal coil conductor is not exposed at the chip end surface, becomes disconnected at the time of forming the external electrode, and a disconnection defect occurs. Had occurred.

Therefore, an object of the present invention is to form an exposed portion of an inner coil conductor end which can allow a cutting displacement in a cutting process, to increase the reliability of connection with an external electrode, and to suppress the frequency of occurrence of disconnection failure. An object of the present invention is to provide a multilayer chip inductor with high productivity.

[0010]

According to the present invention, in addition to the disadvantages, in addition to the coil pattern, the present invention forms in advance a pattern in which conductors are exposed at both ends of a chip, and forms each conductor layer. By successively printing, the area of the conductor exposed on the chip end surface can be made larger than the cross-sectional area of at least one conductor layer, and the exposed conductor portion of the adjacent coil pattern is continuous. By forming a conductor layer using such a printing screen plate, the probability of occurrence of unexposed products at the start and end portions of the internal conductor due to cutting displacement during the sheet cutting step is to be reduced.

Since the area of the exposed portion of the conductor at the end face of the chip is large, it is possible to cope with a cutting displacement such as a lateral parallel displacement, an oblique displacement, a vertical axis displacement, etc., to suppress the occurrence of unexposed conductors, and to make a disconnection when forming an external electrode. The occurrence of defects can be avoided.

That is, the present invention provides a multilayer chip inductor in which a magnetic layer and a conductor layer are alternately laminated and printed by a multilayer printing method, and a coil conductor portion is provided inside the magnetic layer. A multilayer chip inductor characterized in that the area of the exposed portion of the coil conductor leading conductor is the product of the thickness from the first conductor layer to the final conductor layer and the element width.

Further, the present invention provides a multilayer chip inductor wherein the conductor exposed portions are formed so that the conductor exposed portion patterns of each layer adjacent in the longitudinal direction are continuous. Is the way.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the multilayer chip inductor of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an internal structure of a multilayer chip inductor 1 according to an embodiment of the present invention, and FIG.
1 shows an external view of a multilayer inductor 1. FIG. 4 is an exploded perspective view showing the configuration of the multilayer chip inductor 1.

The multilayer chip inductor 1 is formed by forming a coil conductor portion 3 inside a magnetic body 2 by a multilayer printing method, firing this integrally at a high temperature, and forming external electrodes 5 on both end surfaces of the chip. is there. Using a magnetic sheet (green sheet) 6 formed by processing a magnetic material such as a Ni—Zn-based soft magnetic ferrite as a base material, a conductive pattern formed on a screen plate is used for an upper surface thereof, and Ag or Ag
-Screen printing is performed with a paste-like conductive ink (hereinafter, referred to as a conductor paste) having a certain viscosity, composed of a conductor metal powder such as Pd and an organic binder for dispersing the conductor metal powder.

This conductor pattern is composed of a plurality of fragmented coils each having a combination such that the coil conductor portion 3 is finally formed inside the magnetic material. Conductor pattern and final conductor layer 85
The conductor pattern is designed in advance so that the conductor portions are exposed at both end surfaces of the chip, and these are the start end and the end 4 of the coil conductor 3 existing inside the magnetic body 2. At this time, the area of the conductor exposed portion 4 that appears on the chip end face is the cross-sectional area of one end face of the chip corresponding to the conductor thickness of the first conductor layer 81 (the other end face is the cross-sectional area of the conductor thickness of the final conductor layer 85)
(FIG. 5).

On the upper surface of the first conductor layer 81, Ni-Zn
A first magnetic layer is formed by screen printing using a magnetic paste obtained by kneading a soft magnetic ferrite powder or the like and an organic binder. However, since the cutout window 9 is provided in this magnetic pattern, a part of the first conductor layer 81 is exposed after printing the first magnetic layer. This joins the conductor of the second conductor layer 82 to form a part of the coil conductor 3. The printing process of the magnetic layer and the conductor layer is alternately repeated until a desired number of turns is obtained. Finally, the green sheets 6 are overlapped to complete the printing and laminating step. Thus, the coil conductor 3 is formed inside the magnetic body.

In the lamination printing process at this time, each screen plate for forming the final conductor layer 85 from the first conductor layer 81 includes, in addition to each coil pattern, a conductor pattern for exposing the conductor on the chip end face. (Hereinafter, the conductor exposure pattern 10) is formed at the same time.

At this time, as shown in FIG. 5, the exposed conductor portions 4 of the elements adjacent in the longitudinal direction (the conductor end of the element A and the conductor start end of the adjacent element B) are continuous.
An exposed conductor pattern 10 is formed in advance. By performing the lamination printing using the conductor pattern including the coil pattern and the conductor exposure pattern 10, at the end of the lamination printing,
A conductor exposed portion 4 having a thickness corresponding to the number of times of printing of the conductor layer is formed at the end of the chip.

However, the magnetic pattern for forming the magnetic layer 11 at this time has notches 7 for connecting the conductor layers 10 formed by the conductor exposed patterns above and below the magnetic layer 11. Therefore, the conductor layers 10 formed by the conductor exposure patterns existing in the respective conductor layers are all electrically connected.

A cutting step of cutting a magnetic sheet having a plurality of coil conductor portions 3 arranged in a grid pattern on one platen, formed by lamination printing, into individual chips on a dice, thereby forming chip ends. The exposed conductor portion 4 formed by the conductor exposed pattern 10 appears in the portion (FIG. 4).

Each chip-shaped element is debindered at about 600 ° C. in a firing furnace and fired at about 900 ° C. to form a sintered body. A conductor paste for an external electrode is applied to the end face of the sintered body chip, and the exposed conductor portion 4 exposed on the chip end face is electrically connected to the external electrode 5.
To form

At this time, the exposed conductor portion 4 on the chip end face is
Since the exposed area is larger than that of the conventional product, the external electrode 5
Therefore, the frequency of disconnection due to disconnection between the internal coil conductor 3 and the external electrode 5 can be greatly reduced.

In particular, in the cutting step, the accuracy and variation of the cutting machine and the cutting displacement due to careless mistakes in the alignment of the origin by the operator make it difficult to secure the conductor exposure on the chip end face. However, by performing the lamination printing by the manufacturing method using the conductor pattern according to the present invention, as shown in FIG. 6, (a) horizontal parallel displacement, (b) oblique displacement, and (c) vertical axis displacement, etc. It is possible to cope with a cutting deviation, and it is possible to reduce the probability of occurrence of a conductor unexposed product.

That is, even if there is a cutting deviation, an electrode satisfying the characteristics can be formed in a later step of forming the electrode.

As described above, since the conductor exposed area of the lead portion of the internal conductor of the multilayer chip inductor is large, the unexposed conductor due to the cutting displacement is reduced, and the disconnection failure due to the disconnection with the external electrode is reduced, and the productivity is high. A multilayer chip inductor is obtained.

[0028]

As described above, according to the present invention, since the exposed portion of the inner coil conductor end which can allow the cutting displacement in the cutting step is formed, the reliability of connection with the external electrode is increased. An object of the present invention is to provide a multilayer chip inductor with high productivity in which the occurrence frequency of disconnection failure is suppressed.

[Brief description of the drawings]

FIG. 1 is a perspective view showing the internal structure of a multilayer chip inductor according to the present invention.

FIG. 2 is an external perspective view of the multilayer chip inductor of the present invention.

FIG. 3 is a diagram showing each state of the multilayer chip inductor according to the present invention before external electrodes are formed. FIG. 3A is a diagram showing one end face of a chip including a lead-out exposed portion of an internal conductor before forming an external electrode of the multilayer chip inductor of the present invention. FIG. 3 (b)
FIG. 2 is a cross-sectional view of the multilayer chip inductor of the present invention before external electrodes are formed. FIG. 3C is a diagram showing the other end surface of the chip including the lead-out exposed portion of the internal conductor before the formation of the external electrode of the multilayer chip inductor of the present invention.

FIG. 4 is an exploded perspective view showing the configuration of the multilayer chip inductor of the present invention.

FIG. 5 is a schematic cross-sectional view in the vertical axis direction showing a state of an exposed conductor portion between adjacent elements of the multilayer inductor of the present invention.

FIG. 6 is a schematic diagram showing an example of a cutting position shift of the multilayer inductor of the present invention. FIG. 6A is a vertical cross-sectional view of the element when it is shifted in parallel in the horizontal direction. FIG. 6B is a cross-sectional view in the horizontal direction (stacking direction) of the element when the element is shifted in an oblique direction. FIG.
(C) is a vertical cross-sectional view of the element when it is obliquely shifted in the vertical axis direction.

FIG. 7 is a perspective view showing the internal structure of a conventional multilayer chip inductor.

FIG. 8 is a diagram showing each state of a conventional multilayer chip inductor before external electrodes are formed. FIG. 8A is a diagram showing one end surface of a chip including a lead-out exposed portion of an internal conductor of a conventional multilayer chip inductor before an external electrode is formed. FIG. 8B is a cross-sectional view of a conventional multilayer chip inductor before external electrodes are formed.
FIG. 8C is a diagram showing the other end face of the chip including the lead-out exposed portion of the internal conductor before the formation of the external electrode of the conventional multilayer chip inductor.

FIG. 9 is an external perspective view of a conventional multilayer chip inductor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 laminated chip inductor 2 magnetic material part 3 coil conductor part 4 conductor exposed part (laminated inductor of the present invention) 5 external electrode 6 green sheet 7 cutout part (for connecting conductor exposed part) 9 cutout window (internal coil connection 10) Exposed conductor pattern (and conductor layer formed by the same pattern) 11 Magnetic layer 41 Exposed conductor (conventional multilayer inductor) 81-85 Internal conductor layer (coil portion) 81'-85 'Internal conductor layer

Claims (2)

[Claims] 1. A multilayer chip inductor in which a magnetic layer and a conductor layer are alternately laminated and printed by a multilayer printing method and a coil conductor portion is provided inside the magnetic layer, wherein the coil conductor lead-out conductor at the end of the inductor is provided. A multilayer chip inductor, wherein the exposed area is a product of the thickness from the first conductor layer to the final conductor layer and the element width. 2. The multilayer chip inductor according to claim 1, wherein the conductor-exposed portions are formed so that conductor-exposed portion patterns of respective layers adjacent in the longitudinal direction are continuous with each other. Method.