JPH11340342A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a highly reliable transistor in a region other than a memory cell, e.g. a peripheral circuit region, and a mask ROM for realizing shortening the period before delivery as a memory cell. SOLUTION: The semiconductor device comprises a mask ROM memory having a plurality of first gate electrodes formed in parallel on a semiconductor substrate through a first gate oxide film, a side wall insulation film formed on the side wall of the first gate electrode, and a plurality of second gate electrodes formed between the first gate electrodes through a second gate oxide film on the semiconductor substrate, and a transistor having a first gate electrode formed in a region other than the mask ROM memory cell, a side wall insulation film formed on the side wall of the first gate electrode, and a high breakdown strength source/drain region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a high density mask ROM memory cell using double poly gate electrodes and a so-called peripheral circuit, and a method of manufacturing the same. About.

[0002]

2. Description of the Related Art A mask ROM memory cell system is connected in parallel to a NAND type ROM for writing ROM data by selecting an enhancement type transistor and a depletion type transistor with respect to cell transistors connected in series. There is a NOR type ROM in which the threshold voltage is selectively set to be equal to or higher than the power supply voltage and the ROM data is written to the selected cell transistor. In particular, a high-density NOR type ROM excellent in high integration has recently become the mainstream of the NOR type ROM.

A NAND type R suitable for such high integration
In OM and high-density NOR-type ROMs, there is a method of increasing the density of memory cells by forming gate electrodes in a multilayer (multi-gate) structure in order to achieve higher integration. For example, Japanese Patent Application Laid-Open No. 53-41188 discloses a NAND type RO.
M, JP-A-1-31456 discloses a high-density NOR type R
There is a description about OM.

[0004] However, in order to further increase the density by using these high-density ROM memory cells having a multi-gate structure, the process of writing ROM data into the memory cells becomes a problem. That is, in the mask ROM, it is always required to shorten the delivery time from receipt of the ROM data from the user to shipment, and in the case of the conventional memory cell having the single-layer gate electrode, after the gate electrode is formed, etc. ROM
The data writing process is performed to shorten the delivery time.
Therefore, the same delivery date is required for a memory using a two-layer gate electrode.

On the other hand, with the miniaturization of semiconductor devices, various types of transistors other than memory cells, for example, transistors used in peripheral circuits of memory cells, such as a highly reliable LDD structure or an improved type thereof, are used. Became. In general, a configuration in which a sidewall insulating film is used for forming a source / drain region is often used in this transistor.

Therefore, an LD used in the above-mentioned peripheral circuit and the like
When a transistor having a D structure is combined with a memory cell, in a memory cell having a single-layer gate electrode, a ROM data writing step can be performed after a source / drain region forming step using a sidewall insulating film.

[0007]

However, in a memory cell having a two-layer gate electrode, in particular, in the case of a NAND-type ROM, cell transistors cannot be connected in series.
As described in JP-A-1-128564, a sidewall insulating film is not used for the first-layer gate electrode. If it is intended to be used, a sidewall and a source / drain forming step of the second-layer gate electrode are added, which causes a problem that the delivery time becomes long. Therefore, there is a problem that the transistor in the peripheral circuit section cannot have the LDD structure, and a highly reliable transistor cannot be used.

In addition, since the first-layer gate electrode and the second-layer gate electrode are formed so as to overlap with each other, when the ROM data is written and injected after the gate is formed, sufficient ions are implanted into the channel portion below the gate electrode. In particular, in the case of a NOR type cell, there is a problem that leakage is likely to occur.

[0009]

According to the present invention, a plurality of first gate electrodes are formed on a semiconductor substrate in parallel with each other via a first gate oxide film, and the first gate electrodes are formed on side walls of the first gate electrode. Mask R comprising a side wall insulating film formed on the semiconductor substrate and a plurality of second gate electrodes formed on the semiconductor substrate between the first gate electrodes with a second gate oxide film interposed therebetween.
An OM memory cell; a first gate electrode formed in a region other than the mask ROM memory cell; a sidewall insulating film formed on a side wall of the first gate electrode; and a high withstand voltage source / drain region. A semiconductor device including a transistor is provided.

According to the present invention, (i) forming a plurality of first gate electrodes via a first gate oxide film in a memory cell and a region other than the memory cell on the semiconductor substrate of the first conductivity type; (Ii) forming a sidewall insulating film on the first gate electrode; and (iii) forming a second gate oxide film on the memory cell on the obtained semiconductor substrate.
Forming a conductive film for a second gate electrode via the second gate oxide film; and (iv) forming a second conductive film between the first gate electrodes of the memory cell so as not to overlap the first gate electrode. Forming a gate electrode; and (v) forming a ROM data write ion implantation resist pattern on the first gate electrode and the second gate electrode, and using the resist pattern to form the first gate electrode and the second gate electrode. RO is selectively applied to the semiconductor substrate by energy passing through the gate electrode.
And a step of performing M data write ion implantation.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention has a memory cell (hereinafter, referred to as a "double poly gate structure") having a two-layer gate structure in which first gate electrodes and second gate electrodes are alternately formed. It can be used for a mask ROM, a logic circuit with a built-in mask ROM, an embedded memory, and the like), and circuits other than memory cells such as a decoder, a sense amplifier, and an address buffer, so-called peripheral circuits.

A memory cell of a semiconductor device according to the present invention has a plurality of first gate electrodes formed in parallel on a semiconductor substrate, for example, a silicon substrate, with a first gate insulating film interposed therebetween. . The first gate electrode has a sidewall insulating film on the side wall. In addition, a plurality of second gate electrodes extending through the second gate insulating film are formed on the semiconductor substrate between the first gate electrodes, and the first and second gate electrodes are respectively formed by a plurality of first gate electrodes. The first and second transistors are configured.

The first and second gate insulating films and side wall insulating films are not particularly limited as long as they are materials used as insulating films, and can be formed in desired thicknesses, sizes, and the like. For example, the first and second gate insulating films include a SiO ₂ film having a thickness of about 50 to 300 °. Further, as the sidewall insulating film, for example, a SiO ₂ film having a thickness of about 1000 to 3000 ° is exemplified.

As the first gate electrode, for example, 2000
Polysilicon of about 3000 °, thickness of 1000-2
A high melting point metal silicide (tungsten silicide, tantalum silicide, titanium silicide, etc.) with a thickness of about 000 °, a polycide film that is a laminated film of polysilicon with a thickness of about 1000 to 1500 ° and a silicide with a thickness of about 1000 to 1500 °, and the like. The same thing as the first gate electrode can be used for the second gate electrode. Note that it is preferable that the first gate electrode and the second gate electrode have the same film structure and the same thickness, because writing and injection of MOS data described later can be performed in the same step. Further, an insulating film may be further formed on the first gate electrode and the second gate electrode.
In this case, the same insulating film as the gate insulating film and the sidewall insulating film can be used, and there is no particular limitation as long as the insulating film can have sufficient insulating properties.

The memory cell of the semiconductor device according to the present invention has NO
It is configured as an R-type memory cell, a NAND-type memory cell, or a memory cell in which a NOR-type memory cell and a NAND-type memory cell are mixed. When configured as a NOR type memory cell, source / drain regions orthogonal to the first gate electrode and the second gate electrode are formed. Thereby, each NO composed of the first gate electrode and the source / drain region and the second gate electrode and the source / drain region is formed.
The R-type cell transistors are connected by connecting the source / drain regions to each other.

In the case where NOR type memory cells and NAND type memory cells are mixedly formed, they are formed in a self-aligned manner with respect to the first gate electrode and are orthogonal to the first gate electrode. Source / drain regions are formed in the directions. Thus, the NAND type memory cell transistor including the first gate electrode and the source / drain region and the NOR type memory cell transistor including the second gate electrode and the source / drain region have the same source / drain region. The connection is established by the connection.

Further, when configured as a NAND type memory cell, source / drain regions are formed in a self-aligned manner by impurity diffusion from a sidewall insulating film formed on the side wall of the first gate electrode. Thus, each NAND cell transistor including the first gate electrode and the source / drain region and the second gate electrode and the source / drain region are connected by connecting the source / drain regions to each other. .

The memory cells of the semiconductor device of the present invention may be formed on a flat semiconductor substrate. For example, a plurality of memory cells may be formed in the same direction as the direction in which the first and second gate electrodes extend or in a direction perpendicular to the direction. The book may be formed on a semiconductor substrate on which parallel grooves are formed. Further, the memory cell of the semiconductor device according to the present invention may include a desired first and / or second memory cell.
By implanting impurity ions of the same conductivity type or a different conductivity type as the semiconductor substrate into the channel region immediately below the gate electrode, the impurity concentration of the channel region is adjusted to make the enhancement type depletion type or the depletion type enhancement type. The low threshold enhancement type is converted to the high threshold enhancement type, the low threshold depletion type is converted to the high threshold depletion type,
An information storage transistor having two or more values can be used.

Further, in the semiconductor device of the present invention, the first gate electrode, the sidewall insulating film formed on the side wall of the first gate electrode, and the high breakdown voltage source /
A transistor including a drain region is provided as, for example, a peripheral circuit. High breakdown voltage source / drain region is LD
Although a source / drain region having a D structure can be used, the source / drain region of this LDD structure can be formed by a known method by utilizing a sidewall insulating film formed on the side wall of the first gate electrode.

Step (i) of the method of manufacturing a semiconductor device according to the present invention
In the method, a plurality of first gate electrodes are extended in parallel in a region other than the memory cell and the memory cell on the semiconductor substrate via a first gate insulating film. As the first gate insulating film, for example, a SiO ₂ film can be formed by thermal oxidation or the like. Further, the first gate electrode can be formed with a desired thickness from polysilicon or the like by a known formation method and processing method. This first gate electrode is preferably formed as thin as possible in order to realize high density. Note that an insulating film may be formed on the first gate electrode thus formed. The insulating film at this time can be formed by a known formation method and processing method.

After the first gate insulating film and the first gate electrode are formed and before the sidewall insulating film is formed on the first gate electrode, the first gate electrode and the optional A self-aligned high voltage source / resist
It is preferable to form a part of the drain region, for example, an LDD region. At this time, these regions can be formed by a known ion implantation method or the like in which the acceleration energy and the impurity concentration are appropriately adjusted.

In the step (ii), a side wall insulating film is formed on the first gate electrode formed in the memory cell and a region other than the memory cell. The formation of this sidewall insulating film is performed, for example, by forming Si on the first gate electrode (or insulating film).
An insulating film such as an O ₂ film can be formed, and the insulating film can be formed by anisotropic etching. The sidewall insulating film formed here is preferably set to a thickness such that ions implanted for writing ROM data of the second transistor described later do not diffuse to the channel region of the first transistor. .

After the sidewall insulating film is formed on the first gate electrode, and preferably before the ROM data writing ion implantation to be described later is performed, the first gate electrode and the sidewall insulating film are formed only in regions other than the memory cells. It is preferable to form the high breakdown voltage source / drain regions in a self-aligned manner using a resist pattern having a desired shape. At this time, these regions can be formed by a known ion implantation method or the like in which the acceleration energy and the impurity concentration are appropriately adjusted.

In step (iii), a second gate oxide film is formed on the obtained memory cell of the semiconductor substrate, and a second gate electrode conductive film is formed on the second gate oxide film. In this case, the second gate insulating film and the conductive film for the second gate electrode can be formed using substantially the same materials as those described as the first gate insulating film and the first gate electrode. . When the first gate electrode and the second gate electrode are formed with the same film material and the same thickness,
This is preferable because the ROM data write ion implantation to be described later can be performed only once, and a shorter delivery time can be realized, and the word line resistance that has an influence on the circuit can be set equally. The first gate electrode and the second gate electrode do not necessarily need to be formed of exactly the same material. At this time, an insulating film may be further stacked over the second gate electrode conductive film, or a planarization process may be performed after the insulating film is formed.

In this step, a transistor using a gate electrode without a sidewall insulating film in a region other than the memory cell, that is, a transistor having no high breakdown voltage transistor may be formed. In this case, after the formation of the second gate electrode, before the step (iv), in the step (iv), or thereafter, the source / drain regions are formed by self-aligned ion implantation into the second gate electrode. Is preferred.

In step (iv), a second gate electrode is formed between the first gate electrodes by the second gate electrode conductive film formed on the memory cell. Examples of a method of forming the second gate electrode include a method of patterning by a known photolithography and etching process, and a method of embedding a conductive film for the second gate electrode between the first gate electrodes and then etching back the first gate electrode. A method in which the gate electrode is formed in a self-aligned manner, a method in which patterning is performed after etch back, and the like are given. With such a method, the second gate electrode can be formed so as not to overlap the first gate electrode.

Subsequently, in step (v), a resist pattern for ROM data write ion implantation is formed on the first gate electrode and the second gate electrode, and the first gate electrode or the second gate electrode is formed by using the resist pattern. ROM data writing ions are selectively implanted into the semiconductor substrate with the energy penetrating the electrodes. The resist pattern for ROM data writing ion implantation can be formed so as to have an opening in a desired region by a known method such as a photolithography process and an etching process.
In this case, the resist pattern for ROM data writing injection for the first gate electrode and the R
Two resist patterns for OM data writing and injection may be formed in separate steps, or one resist pattern may be formed in the same step. You may.

The ROM data write ion implantation laser
Ion implantation is performed using the
Write data. Ion implantation at this time
The first gate electrode and the second gate electrode are formed by using a resist pattern.
When performing for each of the electrodes, one resist
Either of the cases where both are performed simultaneously using the
Also, in the case of the first gate electrode and / or the second gate electrode
Is preferably performed with an implantation energy penetrating through. this
The implantation energy depends on the material and film of the first and second gate electrodes.
A transistor that operates at any gate voltage depending on its thickness
Can be set as appropriate. 1st and 2nd game
When the gate electrodes have the same film structure and the same film thickness
Has an implantation energy of, for example, about 70 to 150 keV.
-. The ion dose at this time is 10 ¹³~
10¹⁴cm^-2The platform is mentioned.

The energy penetrating the first gate electrode means the energy that is injected into the semiconductor substrate surface when ions reach the semiconductor substrate surface via the first gate electrode and the first gate insulating film. I do. Also, the second
The energy penetrating the gate electrode means that the ions
It means energy that penetrates through the second gate electrode in a region formed on the semiconductor substrate directly through the gate insulating film and reaches the surface of the semiconductor substrate in that region, thereby being injected into the surface of the semiconductor substrate.

Further, using two resist patterns,
When ion implantation is performed on each of the first gate electrode and the second gate electrode, particularly when ion implantation is performed on the second gate electrode, multi-stage implantation performed by changing implantation energy twice or more, It is preferable to perform injection from two directions. In the multi-stage implantation, the implantation energy can be appropriately adjusted depending on the material or the film thickness of the second gate electrode, for example, about 50 to 100 keV and about 100 keV.
Two injections of about 300 keV may be mentioned. In addition, the injection from two oblique directions is performed in a direction substantially perpendicular to the gate electrode, and is one direction from the normal direction to the semiconductor substrate.
There is a method of injecting at an angle of about 5 to 45 °. By adopting such an implantation method, ion implantation is reliably performed to the end of the second gate electrode, that is, immediately below the end of the second gate adjacent to the end of the sidewall insulating film of the first gate, and the leakage is reduced. Can be prevented.

Further, in the above step, when an insulating film is provided on the first gate electrode and / or the second gate electrode, ROM data writing ion implantation may be performed through the insulating film. After the insulating film on the gate electrode is partially removed using the above resist mask, ROM data writing ion implantation may be performed. The semiconductor device formed by the above steps includes a NOR type cell transistor,
Or, in the case of a semiconductor device in which NOR-type and NAND-type cell transistors are mixed, a desired resist pattern is formed before the step (i) or before the step (ii) or (iii), respectively. It is necessary to form a plurality of source / drain regions parallel to each other so as to be orthogonal to the first and second gate electrodes. The source / drain regions can be formed by a usual ion implantation process. For example, in the case of arsenic ions, it is preferable to perform the treatment at a dose of the order of 10 ¹⁵ to 10 ¹⁶ cm ^{−2 and} an implantation energy of about 20 to 80 keV.

The semiconductor device may be a NAND type cell.
In the case of a semiconductor device including transistors, a NAND
Type cell transistors need to be connected in series,
A process to connect a transistor directly under the sidewall insulating film
It is necessary to add a process. Specifically, the sidewall
Impurities are included in the whole insulating film, and a thick device isolation insulating film etc.
Side wall insulation between transistors as a mask
For example, only 90
Furnace annealing at 0 ° C for about 30 minutes ¹⁹-10
²⁰cm^-2There is a method of diffusing a certain amount of impurities. Another
After the formation of the first gate electrode, the non-doped
Depositing an edge film, and then forming a strip perpendicular to the first gate electrode.
A resist pattern is formed, and this resist pattern is
A high concentration impurity is implanted into the insulating film as a mask. Further
Then, a side wall is formed on the first gate electrode by etch back.
An insulating film is formed. Non-doped sidewall insulation film
Areas and high-concentration areas are formed alternately, and
Diffusion of high-concentration impurities by
Source / drain regions.

In this manufacturing method, it is preferable to form an element isolation region in order to isolate elements between the first and / or second transistors and between the first and second transistors. The element isolation is performed on the semiconductor substrate by the first
This may be performed before or after forming the gate electrode, or after forming the first transistor. As a method of element isolation, a method of forming a LOCOS film may be mentioned, but it is more preferable to implant ions of the same conductivity type as that of the semiconductor substrate into a region to be an element isolation region. Note that this element separation can be performed in one or more steps by a known method, for example, by appropriately adjusting the dose, energy, and the like of the implanted ions.

In addition to the above steps, doping for adjusting the threshold values of the first and second transistors may be performed before or during the formation of the first gate electrode in step (i), or the CMOS structure may be used. If so, a well forming step, a reverse type transistor forming step, and the like may be added by a similar process. Note that, in the manufacturing method of the present invention, the data writing is performed later, so that the delivery time can be shortened. Therefore, before the writing of the second cell transistor, further, after the interlayer insulating film, the contact hole, the metal wiring, etc. A step may be performed.

Hereinafter, the present invention will be described in detail with reference to examples of a semiconductor device and a method of manufacturing the same. The present invention is not limited by these examples. Embodiment 1 FIGS. 1A to 1C show a memory cell portion of a semiconductor device according to this embodiment. FIG. 1B is a plan view of FIG.
FIG. 1A is a cross-sectional view taken along line AA ′, and FIG. 1C is a cross-sectional view taken along line BB ′. In FIG. 1A, a plurality of first gate electrodes 6 and a plurality of second gate electrodes 13 are alternately arranged in parallel with each other. In addition, these gate electrodes 6, 1
A source / drain region 4 is formed so as to intersect substantially at a right angle to the region 3.

The memory cell portion of this semiconductor device is
Both the first gate electrode 6 and the second gate electrode 13 are N
It is configured as an OR type memory cell transistor.
A method for manufacturing a semiconductor device including the memory cell section and the peripheral circuit section will be described with reference to FIGS. First, as shown in FIG. 2C, the LOCOS oxide film 2 is formed only in a region on the semiconductor substrate 1 to be a peripheral circuit portion by a known method. On the other hand, a LOCOS oxide film 2
Does not form. Next, as shown in FIGS. 2A to 2C, an oxide film 3 is formed on the entire surface of the semiconductor substrate 1.

Subsequently, as shown in FIGS. 2B and 2C, a resist pattern (not shown) for covering the peripheral circuit portion of the semiconductor substrate 1 and a desired region in the memory cell portion is formed. By using this resist pattern, ion implantation of impurities of a conductivity type opposite to that of the semiconductor substrate 1 is performed on the memory cell portion to form the source / drain regions 4. At this time, for example, in the case of NMOS, arsenic ions are implanted at a dose of the order of 10 ¹⁵ cm ^{−2 and} an implantation energy of 40 keV. Since the peripheral circuit portion is completely masked, no source / drain regions are formed by this ion implantation.

Next, as shown in FIGS. 3A and 3B, in the memory cell portion, a film thickness of 5
A first gate oxide film 5 of about 0 to 300 ° is formed, and a plurality of first gate electrodes 6 are arranged in parallel on the gate oxide film 5 in the memory cell portion. In the peripheral circuit section,
As shown in FIG. 3C, a first gate electrode 6 is formed in an active region defined by the LOCOS oxide film 2. The gate electrode 6 is made of, for example, N.sub.2 having a thickness of about 2000.degree.
⁺ Polysilicon film or lower layer N ^{+ having a} thickness of about 1000 °
A two-layer structure including a polysilicon film and an upper tungsten silicide film having a thickness of about 1000 ° can be used. An insulating film 7 is formed on the first gate electrode 6 as an etching mask for the first gate electrode 6. This insulating film 7 also functions as an interlayer insulating film between a second gate electrode described later.

Next, a resist pattern (not shown) is formed as shown in FIG.
Ions 8 are implanted. This ion implantation may be performed by a known method such as halo implantation. Then, FIG.
As shown in (a) to (c), a sidewall insulating film 9 is formed on the side wall of the first gate electrode 6 and the insulating film 7 formed thereon. This sidewall insulating film 9 also functions as an interlayer insulating film between the sidewall insulating film 9 and a second gate electrode described later. In the peripheral circuit portion, an LDD region 15 is formed in a region where the LDD ions 8 have been implanted.

Next, as shown in FIG. 6, in the memory cell portion, the first gate electrode 6 on the semiconductor substrate 1 is formed.
A second gate oxide film 10 is formed therebetween. Subsequently, a conductive film 11 serving as a second gate electrode is deposited on the second gate oxide film 10, and an insulating film 12 is further formed thereon.
At this time, the conductive film is, for example, 2000 to 3000 degrees.
It can be used a two-layer structure consisting of the degree of the thickness of the N ⁺ polysilicon film or 1000Å about the thickness of the lower N ⁺ polysilicon film and 1000Å about of the film thickness of the upper layer tungsten silicide film.

Subsequently, as shown in FIG. 7, in the memory cell portion, using a resist pattern (not shown),
The conductive film 11 and the insulating film 12 on the first gate electrode 6 are removed by etching to form a second gate electrode 13 between the first gate electrodes 6. After the insulating film 14 on the second gate electrode 13 is patterned with a resist mask,
It may be used alone as a mask for processing the second gate electrode 13. This insulating film 14 also functions as an interlayer insulating film between a metal wiring electrode described later.

The second gate electrode is not formed in the peripheral circuit section. Next, as shown in FIG. 8, a resist pattern (not shown) is formed on the memory cell portion of the semiconductor substrate 1 and a desired region in the peripheral circuit portion, and ions 16 are implanted into the source / drain regions. Do. At this time, for example, in the case of NMOS, the ion implantation is performed by implanting arsenic ions at a dose of the order of 10 ¹⁵ cm ^{−2 and} an implantation energy of 40 keV.

As a result, source / drain regions 17 are formed in the peripheral circuit section as shown in FIG. next,
As shown in FIG. 10, the ROM data write injection of the first cell transistor constituted by the first gate electrode 6 is performed. That is, the first to write the ROM data
Implantation mask 18 having an opening in the region of the cell transistor
Is formed, and ions 19 of the same conductivity type as that of the semiconductor substrate 1 are selectively implanted using the implantation mask 18, thereby selectively changing the impurity concentration of a desired channel region of the first cell transistor. In this case, for example, in the case of NMOS, B ⁺ ions are implanted with 10 ¹³
The implantation is performed at a dose of about 10 ¹⁴ cm ^{−2 and} an implantation energy of 100 keV.

Further, as shown in FIG. 11, R of the second cell transistor constituted by the second gate electrode 13
OM data write injection is performed. That is, a resist pattern 20 having an opening is formed in a region of the second cell transistor in which ROM data is to be written, and ions 19 of the same conductivity type as that of the semiconductor substrate 1 are selectively implanted using the resist pattern 20. And selectively changing the impurity concentration in the channel region of the desired second cell transistor. The data write injection at this time is performed by, for example, NMO.
In the case of S, B ⁺ ions are implanted at a dose of the order of 10 ¹³ to 10 ¹⁴ cm ^{−2 and} an implantation energy of 120 keV.

In the above method, implantation for controlling the threshold value of the transistor in the memory cell portion, element isolation ion implantation, and the like may be performed as appropriate. Also, the transistors in the peripheral circuit section are CMO
In the case of the S structure, a well formation step and a reverse type transistor formation step may be added by a similar process. Subsequently, through the formation of an interlayer insulating film with a metal wiring, the formation of a contact hole, the formation of a metal wiring, the formation of a protective film, and the like, the first half of the process of the semiconductor device is completed. Then, the semiconductor device is completed.

Embodiment 2 The semiconductor device of this embodiment is almost the same as Embodiment 1 except that the insulating film 14 is not provided on the second gate electrode 13 of the second transistor in the memory cell portion.

That is, as shown in FIG. 12, a second gate oxide film 10 and a conductive film 11 are deposited between the first gate electrodes 6 on the semiconductor substrate 1 in the memory cell portion, and as shown in FIG. As shown in (1), the conductive film 11 on the first gate electrode 6 is removed by etching to form the second gate electrode 13 between the first gate electrodes 6. Subsequently, as shown in FIG. 14, similarly to the first embodiment, the ROM data write injection of the first cell transistor constituted by the first gate electrode 6 is performed.

Further, as shown in FIG.
In the same manner as described above, the ROM data write injection of the second cell transistor constituted by the second gate electrode 13 is performed. As described above, since no insulating film is provided on the second gate electrode 13, a concave portion having a constant film thickness is formed on the second gate electrode 13. Therefore, ions are implanted through the concave portion of the second gate electrode 13 having a constant film thickness at the time of ROM data writing injection, and stable ROM data writing is performed and characteristics are stabilized.

Embodiment 3 In the semiconductor device of this embodiment, FIG.
After that, the resist pattern 20 having an opening is formed on the second gate electrode 13 on which ROM data is to be written, and the insulating pattern on the second gate electrode 13 is formed as shown in FIG. The film 14 is removed by etching.

Subsequently, by performing ion implantation through the second gate electrode 13 from which the insulating film 14 has been removed, ROM data is written in the same manner as in the first embodiment. According to such a process, as in the second embodiment, ions are implanted through the concave portion of the second gate electrode 13 having a constant film thickness at the time of ROM data write injection, and stable ROM data write is performed. The characteristics are stable.

Embodiment 4 In the semiconductor device of this embodiment, FIG.
The steps up to the step are substantially the same. Thereafter, as a step of writing ROM data in the second cell transistor, multi-stage implantation is adopted by changing at least the implantation energy.

That is, R for the second cell transistor
OM data write injection, especially the second gate electrode is NOR
When used as a type memory cell transistor, it is important that the ROM data write implant ions sufficiently reach the end of the second gate electrode. If the switch cannot be sufficiently turned off, a leak will occur, leading to a failure. Therefore, FIG.
As shown in FIG. 7, the same resist pattern 2 as in Example 2 was used.
For example, in the case of NMOS, B ⁺ ion is set to 1
0 ¹³ ~10 ¹⁴ cm ^-2 single dose, implantation energy of 100 keV, B ⁺ ions 10 ¹³ ~10 ¹⁴ cm ^-2 single dose, by multistage an implantation energy of 200 keV, a second cell transistor ROM data is written to

Embodiment 5 In the semiconductor device of this embodiment, the semiconductor device shown in FIG.
The steps up to this step are almost the same. Thereafter, as a step of writing ROM data in the second cell transistor, implantation from two oblique directions is employed.

That is, as shown in FIG. 18, a resist pattern 20 similar to that of the second embodiment is used. For example, in the case of an NMOS, B ⁺ ions are implanted at a dose of about 10 ¹³ to 10 ¹⁴ cm ⁻² and a dose of 140 keV. The semiconductor substrate 1 at the implantation energy
Is ion-implanted at an angle of 20 ° from the normal direction to the second cell transistor to write ROM data.

As a result, similarly to the fourth embodiment, the ROM data write injection into the second cell transistor is performed. In particular, when the second gate electrode is used as a NOR type memory cell transistor, the ROM data is sufficiently written to the end of the second gate electrode. Implanted ions can be performed, so that occurrence of leakage and failure of the semiconductor device can be prevented.

Embodiment 6 This embodiment is a method in which ROM data write injection to the first cell transistor and the second cell transistor is performed by multiple exposure and one injection step. That is, instead of performing the steps of FIGS. 14 and 15 in the second embodiment, after exposing using the exposure mask corresponding to the injection resist pattern for writing the ROM data to the first cell transistor, the ROM data writing to the second cell transistor is performed. A first cell transistor and a second cell transistor for writing ROM data by forming a ROM data writing resist pattern by exposing using an exposure mask corresponding to the At the same time, ion implantation is performed.

By such a process, a shorter delivery time can be realized. After performing processes such as interlayer film formation, contact hole opening, and barrier metal sputtering, the ROM
By performing the data write injection, a further shorter delivery time can be realized.

Embodiment 7 This embodiment is a method in which ROM data write / injection for the first cell transistor and the second cell transistor is performed by one photolithography and injection process.

That is, FIG. 14 and FIG.
Instead of the step 5, as shown in FIG. 19, a resist pattern 23 having an opening is formed for all the transistors for which the ROM data of the first cell transistor and the second cell transistor are to be written. Ion implantation is performed using the pattern 23 in the same manner as in the first embodiment. Such a process can further shorten the delivery time.

After performing processes such as interlayer film formation, contact hole opening, and barrier metal sputtering, the ROM
By performing the data write injection, a further shorter delivery time can be realized.

Embodiment 8 In this embodiment, a memory cell different from that of the above embodiment, that is, a memory cell in which the first gate electrode 6 constitutes a NAND type memory cell transistor and the second gate electrode 13 constitutes a NOR type memory cell transistor. FIG.

FIG. 20 shows a memory cell of the semiconductor device of this embodiment, and FIG. 21 shows an equivalent circuit diagram thereof. In addition, FIG. 22 shows each cross-sectional view in FIG. In FIG. 20, a plurality of first gate electrodes 6 and a plurality of second gate electrodes 13 are alternately arranged in parallel with each other. The source / drain region 4 is formed in a part below the second gate electrode 13. Further, an element isolation region 24 having the same conductivity type as the semiconductor substrate 1 is formed in a region below the first gate electrode 6 and not adjacent to the source / drain region 4.

In this embodiment, data writing to the first cell transistor, which is a NAND type memory cell transistor, is performed in substantially the same manner as in the above embodiment by implanting ions of the opposite type to the semiconductor substrate 1. Can be. The ions at this time are, for example, in the case of NMOS, phosphorus ions at a dose of about 10 ¹³ cm ⁻² ,
The implantation is performed at an implantation energy of about 0 to 400 keV.

Embodiment 9 This embodiment is different from the first gate electrode 6 and the second gate electrode 1 in FIGS.
Reference numeral 3 denotes a semiconductor device having memory cells constituting a NAND type memory cell transistor. FIG. 23 shows a memory cell of the semiconductor device of this embodiment, and FIG. 24 shows an equivalent circuit diagram thereof. FIG. 25 is a sectional view taken along the line BB 'in FIG. In FIG. 23, the first gate electrode 6
And a plurality of second gate electrodes 13 are alternately arranged in parallel with each other. Further, the source / drain region 4 is formed immediately below the sidewall insulating film 9 located between the first gate electrode 6 and the second gate electrode 13.

As a method for forming such source / drain regions 4, P ⁺ ions are contained in the sidewall insulating film 9 at a concentration of about 10 ²⁰ to 10 ²¹ cm ⁻³ , and the first gate is formed by heat treatment. Impurities are diffused from the sidewall insulating film located between the electrode 6 and the second gate electrode 13 into the semiconductor substrate 1 therebelow. In the present embodiment, N
Data writing to the first and second cell transistors, which are AND-type cells, can be performed substantially in the same manner as in the above embodiment by implanting ions of the opposite type to the semiconductor substrate 1. At this time, phosphorus ions are implanted with a dose of about 10 ¹³ cm ^{−2 and} an implantation energy of about 300 keV for the first cell transistor and about 300 keV for the second cell transistor.

[0066]

According to the semiconductor device of the present invention, in a high-density mask ROM memory cell using a so-called double poly gate electrode, a first structure having a sidewall insulating film is provided.
Since the gate electrode includes the gate electrode and the second gate electrode formed between the first gate electrodes, the overlap between the first gate electrode and the second gate electrode can be reduced by the width of the sidewall insulating film, and ROM data writing and injection can be performed. Can be reduced due to insufficient entry. That is, when there is no sidewall insulating film, the first gate and the second gate may overlap in order to secure the overlapping margin between the first gate electrode and the second gate electrode. When ROM data is written by ion implantation in such a mask ROM memory cell, the ROM data is not sufficiently injected into the first gate end, which is an overlap portion, and a writing failure occurs. On the other hand, when the sidewall insulating film is formed as in the present invention, the overlapping margin of the first gate electrode and the second gate electrode can be partially secured by the thickness of the sidewall insulating film. Accordingly, the overlap between the first gate electrode and the second gate electrode can be reduced. In addition, since the first gate electrode and the second gate electrode do not substantially overlap due to the existence of the sidewall insulating film, when ROM data is written by ion implantation, the ROM is also applied to the first gate end. Data is sufficiently injected, so that writing failure can be prevented.

In addition, since a so-called peripheral circuit has a high breakdown voltage transistor in addition to the high-density mask ROM memory cell, a highly reliable semiconductor device can be realized. Further, in the case where the first gate electrode and the second gate electrode have the same film configuration and film thickness, in particular, the data write ion implantation of the mask ROM, which is performed in a later step, is performed on the first gate electrode and the second gate electrode. Can be performed at the same time, the delivery time can be further shortened, and the word line resistance which has an influence on the circuit can be set to be equal.

As described above, since writing of ROM data can be performed in a relatively later step at the same time as cost reduction due to creation of a large-capacity ROM and reduction in chip size,
This is very effective for shortening the delivery time. Further, according to the method for manufacturing a semiconductor device of the present invention, a part of the manufacturing process of the memory cell can be performed together with a part of the manufacturing process of the transistor in the peripheral circuit. Reduction can be achieved.

Further, in the case where the write ion implantation of the ROM data into the first gate electrode and the second gate electrode is performed by using two masks in separate steps, it can be used as a dedicated mask for each gate electrode. Therefore, RO
The margin of the resist pattern for M data write injection can be made large. In addition, since ion implantation can be performed on each gate electrode under optimum conditions, it is easier to secure a margin. In particular, when data writing ion implantation is performed on the second gate electrode, the second
Since a part of the gate electrode may be formed up to the side wall spacer of the first gate electrode, the second gate electrode can be formed by oblique implantation from two directions or multiple times with different acceleration energies. Ions serving as ROM data sufficiently enter the semiconductor substrate just below the end of the channel, a uniform threshold value can be secured in the channel, and the occurrence of leaks and the like can be prevented.

When the ion implantation for writing the ROM data into the first gate electrode and the second gate electrode is performed by using one resist pattern, particularly, one resist pattern by multiple exposure, 1 Since only one ion implantation is required, the process can be further simplified, the delivery time can be shortened, and the manufacturing cost can be reduced. In this manner, a so-called peripheral circuit can be formed by partially utilizing the process of manufacturing a memory cell, and high reliability, high withstand voltage,
A transistor having a small size can be used for a peripheral circuit, so that reliability and cost reduction of a semiconductor device can be further realized.

[Brief description of the drawings]

1A is a schematic plan view showing one embodiment of the semiconductor device of the present invention, FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A, and FIG. FIG. 13 is a sectional view taken along line BB ′ of FIG.

FIG. 2 is a schematic cross-sectional view of a main part for describing a first step in a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic cross-sectional view of a main part for describing a second step in the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a schematic cross-sectional view of a main part for describing a third step in the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a schematic cross-sectional view of a main part for describing a fourth step in the method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a schematic cross-sectional view of a main part for describing a fifth step in the method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a schematic cross-sectional view of a main part for describing a sixth step in the method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a schematic cross-sectional view of a main part for describing a seventh step in the method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a schematic sectional view of a main part for describing an eighth step in the method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a ninth embodiment of the method of manufacturing a semiconductor device according to the present invention;
It is a schematic sectional drawing of the principal part for demonstrating a process.

FIG. 11 shows a first example of the method for manufacturing a semiconductor device according to the present invention.
It is a schematic sectional drawing of the principal part for demonstrating 0 process.

FIG. 12 is a schematic cross-sectional view of a main part for describing another embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 13 is a schematic cross-sectional view of a main part for describing another embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 14 is a schematic cross-sectional view of a main part for describing another embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 15 is a schematic cross-sectional view of a main part for describing another embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 16 is a schematic cross-sectional view of a main part for describing still another embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 17 is a schematic cross-sectional view of a main part for describing an example of multi-stage implantation in the method of manufacturing a semiconductor device according to the present invention.

FIG. 18 is a schematic cross-sectional view of a main part for describing an example of injection from two oblique directions in the method for manufacturing a semiconductor device of the present invention.

FIG. 19 is a schematic cross-sectional view of a main portion for describing an example of simultaneous implantation using one resist pattern in the method for manufacturing a semiconductor device of the present invention.

FIG. 20 is a schematic plan view showing another embodiment of the semiconductor device of the present invention.

FIG. 21 is an equivalent circuit diagram of the semiconductor device of FIG. 20;

FIG. 22 is a schematic sectional view of various main parts of the semiconductor device of FIG. 20;

FIG. 23 is a schematic plan view showing still another embodiment of the semiconductor device of the present invention.

FIG. 24 is an equivalent circuit diagram of the semiconductor device of FIG. 23;

FIG. 25 is a schematic cross-sectional view of a main part taken along line BB ′ of the semiconductor device of FIG. 23;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Locos oxide film 3 Oxide film 4 Source / drain region 5 First gate oxide film 6 First gate electrode 7, 12, 14 Insulating film 8 LDD ion 9 Side wall insulating film 10 Second gate oxide film 11 Conductivity Film 13 second gate electrode 15 LDD region 16 source / drain region ions 17 source / drain region 18 implantation mask 19, 21, 22, 25 ions 20, 23 resist pattern

Claims (12)

[Claims] A plurality of first gate electrodes formed on a semiconductor substrate in parallel with each other via a first gate oxide film;
A mask comprising: a sidewall insulating film formed on a side wall of the first gate electrode; and a plurality of second gate electrodes formed on the semiconductor substrate and between the first gate electrodes via a second gate oxide film. A ROM memory cell; a first gate electrode formed in a region other than the mask ROM memory cell; a sidewall insulating film formed on a side wall of the first gate electrode; and a high breakdown voltage source / drain region. A semiconductor device comprising a transistor. 2. The first gate electrode and the second gate electrode,
2. The semiconductor device according to claim 1, having the same film configuration and thickness. 3. The method according to claim 1, further comprising the step of:
3. The method according to claim 1, wherein an insulating film is formed on the gate electrode.
13. The semiconductor device according to claim 1. 4. The mask ROM memory cell further has a source / drain region orthogonal to a first gate electrode and a second gate electrode, wherein the source / drain region and the first gate electrode or the second gate electrode. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device comprises a NOR type memory cell transistor. 5. The mask ROM memory cell further includes a source / drain region formed in a self-aligned manner with respect to the first gate electrode and extending in a direction orthogonal to the first gate electrode. 4. The source / drain region and the first gate electrode constitute a NAND memory cell transistor, and the source / drain region and the second gate electrode constitute a NOR memory cell transistor. The semiconductor device according to any one of the above. 6. The mask ROM memory cell further includes a source / drain region formed in a self-aligned manner by impurity diffusion from a side wall insulating film formed on a side wall of the first gate electrode. 4. The semiconductor device according to claim 1, wherein said first gate electrode and said second gate electrode form a NAND memory cell transistor. 7. (i) forming a plurality of first gate electrodes via a first gate oxide film in a memory cell and a region other than the memory cell on a semiconductor substrate of a first conductivity type; Forming a sidewall insulating film on the first gate electrode; and (iii) forming a second insulating film on the memory cell on the obtained semiconductor substrate.
Forming a gate oxide film, via the second gate oxide film,
Forming a second gate electrode conductive film; and (iv) forming a second gate electrode between the first gate electrodes of the memory cell so as not to overlap the first gate electrode. ) ROM on the first gate electrode and the second gate electrode
Forming a resist pattern for data write ion implantation, and selectively implanting ROM data write ions into the semiconductor substrate with energy penetrating the first gate electrode and the second gate electrode using the resist pattern. A method for manufacturing a semiconductor device, comprising: 8. In step (i) and / or step (iii), an insulating film is formed on the first gate electrode and / or the second gate electrode, and in step (v), the first gate electrode or 8. The method of manufacturing a semiconductor device according to claim 7, wherein the data write ion implantation is performed after the insulating film on the second gate electrode is removed by etching using the ROM data write ion implantation resist pattern. 9. In a step (v), a resist pattern for ROM data write ion implantation is exposed to a resist, and a ROM data write ion implantation pattern for the first gate electrode is exposed to the resist.
A pattern for data writing ion implantation is formed by multiple exposure to expose the resist, and the ROM data writing ion implantation is simultaneously performed on the first gate electrode and the second gate electrode using the resist pattern for ROM data writing ion implantation. The method for manufacturing a semiconductor device according to claim 7, wherein the method is performed. 10. The method according to claim 5, wherein in step (v), the ROM corresponding to the ROM data of both the first gate electrode and the second gate electrode is provided.
9. The ROM data writing ion implantation is simultaneously performed on the first gate electrode and the second gate electrode using the data writing ion implantation resist pattern.
The manufacturing method of the semiconductor device described in the above. 11. The method for manufacturing a semiconductor device according to claim 7, wherein in the step (v), the ROM data write ion implantation for the second gate electrode is performed in two oblique directions with respect to the second gate electrode. 12. The method of manufacturing a semiconductor device according to claim 7, wherein in the step (v), the ROM data write ion implantation for the second gate electrode is performed by changing the implantation energy by two or more conditions.