JPH11307320A - Chip resistor and manufacture thereof - Google Patents
Chip resistor and manufacture thereofInfo
- Publication number
- JPH11307320A JPH11307320A JP10112316A JP11231698A JPH11307320A JP H11307320 A JPH11307320 A JP H11307320A JP 10112316 A JP10112316 A JP 10112316A JP 11231698 A JP11231698 A JP 11231698A JP H11307320 A JPH11307320 A JP H11307320A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- groove
- film
- chip resistor
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
【0001】[0001]
【発明が属する技術分野】本発明はチップ抵抗器の製造
方法に関し、特に配線基板のランドに対しチップ抵抗器
の端面電極側方向にはんだフィレットを設けることなく
はんだ結合可能な、いわゆるフィレットレス形のチップ
抵抗器を製造する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a chip resistor, and more particularly to a so-called filletless type which can be solder-bonded to a land of a wiring board in a direction toward an end face electrode of the chip resistor without providing a solder fillet. The present invention relates to a method for manufacturing a chip resistor.
【0002】[0002]
【従来の技術】チップ抵抗器では、従来から、配線基板
のランドと抵抗器の端面電極とをはんだフィレットによ
ってはんだ結合させているが、近年の電子機器の超小型
化、携帯化等に伴い電子部品の実装密度の高集積化の要
求が高まり、はんだ占有面積を極力減少させるべく、ラ
ンドに対しチップ抵抗器の端面電極側方向にはんだフィ
レットを設けることなく抵抗器の上面電極をはんだ結合
させるフィレットレス形のチップ抵抗器が切望されてい
る。2. Description of the Related Art In a chip resistor, a land of a wiring board and an end face electrode of the resistor have been conventionally soldered to each other by a solder fillet. The demand for higher integration of component mounting density has increased, and in order to reduce the solder occupation area as much as possible, a fillet that solders the upper electrode of the resistor without providing a solder fillet in the direction of the end face electrode side of the chip resistor with respect to the land There is a long-felt need for a chip-type chip resistor.
【0003】かかるフィレットレス形のチップ抵抗器で
は、電極の高さを、電極間の抵抗膜を覆う保護膜上面と
同程度とするか又はこれより若干突出させる必要がある
ため、その分、電極を厚くしなけらばならない。In such a filletless type chip resistor, the height of the electrodes needs to be equal to or slightly protrude from the upper surface of the protective film covering the resistive film between the electrodes. Must be thicker.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、チップ
抵抗器は、縦横の分割溝によって多数の絶縁基板が区画
される原板上に電極、抵抗膜及び保護膜を所要に配設し
た後、上記分割溝に沿って分割して製造されるが、分割
溝を跨いで電極が設けられるため、電極の厚さをを確保
すると、原板分割時の電極の分割が円滑に行われず、電
極の分割面にバリや欠けが生じるという問題がある。こ
のようなバリや欠けは、例えば製造工程でのシュートの
詰まりや実装機でのテーピングのキャビティからの吸着
ミスの要因となったり、はんだ結合面積の減少によるは
んだ結合の低下を招き、また、抵抗器を一層小型化する
に当たっての阻害要因ともなる。However, in the chip resistor, electrodes, a resistive film, and a protective film are provided on an original plate on which a large number of insulating substrates are divided by vertical and horizontal dividing grooves, and then the dividing grooves are formed. However, since the electrodes are provided across the dividing grooves, if the thickness of the electrodes is ensured, the division of the electrodes during the original plate division is not performed smoothly, and flash is formed on the divided surfaces of the electrodes. There is a problem that chipping occurs. Such burrs and chips may cause, for example, clogging of a chute in a manufacturing process, a suction error from a taping cavity in a mounting machine, or a decrease in a solder bonding area due to a decrease in a solder bonding area. It also becomes a hindrance factor in further downsizing the vessel.
【0005】本発明は、以上のような問題点に鑑みてな
されたものであり、その目的は、原板分割時に電極にバ
リや欠けが生じることがなく、フィレットレス形の抵抗
器としての電極の厚さを確保できるチップ抵抗器の製造
方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to prevent burrs or chips from being generated in an electrode when dividing an original plate, and to provide an electrode as a filletless type resistor. An object of the present invention is to provide a method for manufacturing a chip resistor capable of ensuring a sufficient thickness.
【0006】[0006]
【課題を解決するための手段】請求項1に記載した本発
明に係るチップ抵抗器の製造方法(以下、「本製造方法
」という。)は、配線基板のランドに対し電極の上面
をはんだ結合させるフィレットレス形のチップ抵抗器を
製造する方法であって、互いに直交する第1の分割溝及
び第2の分割溝によって多数の絶縁基板を区画する原板
上に当該第1の分割溝を跨いで当該絶縁基板の両端部に
おいて一対となる下層電極を配設する工程と、前記下層
電極間を連絡する抵抗膜を配設する工程と、前記抵抗膜
にトリミングを施す工程と、前記抵抗膜を保護膜で被覆
する工程と、前記第1の分割溝を比較的狭小に跨ぎ且つ
当該第1の分割溝に沿って延長する分離層を形成する工
程と、前記保護膜と前記分離層との間に上層電極を配設
する工程と、前記原板を前記第1の分割溝及び第2の分
割溝に沿って分割する工程と、前記上層電極上にめっき
膜を形成する工程とを含むことを特徴とする。According to a first aspect of the present invention, there is provided a method of manufacturing a chip resistor according to the present invention, in which an upper surface of an electrode is solder-bonded to a land of a wiring board. A method for manufacturing a filletless type chip resistor, comprising: a first division groove and a second division groove which are orthogonal to each other, and the first division groove straddles a large number of insulating substrates on an original plate. Arranging a pair of lower electrodes at both ends of the insulating substrate, arranging a resistive film communicating between the lower electrodes, trimming the resistive film, and protecting the resistive film A step of coating with a film, a step of forming a separation layer that straddles the first division groove relatively narrowly, and extends along the first division groove, and between the protection film and the separation layer. Disposing an upper layer electrode; A step of dividing along the first split groove and second split groove, characterized in that it comprises a step of forming a plating layer on the upper electrode.
【0007】即ち、本製造方法では、電極を下層電極
と上層電極とからなる二層構造として、下層電極に抵抗
膜を連接する一方、配線基板のランドにフィレットレス
形チップ抵抗器の上面電極をはんだ結合させるための電
極の厚さを上層電極によって確保し、このように厚膜と
した上層電極が第1の分割溝にかからないように第1の
分割溝に沿って分離層を先行形成することにより、原板
分割時に分離層は分割するものの、上層電極は分割され
ず、従って、上層電極におけるバリや欠けの発生を回避
するこができる。That is, in this manufacturing method, the electrode has a two-layer structure including a lower electrode and an upper electrode, and a resistive film is connected to the lower electrode, while the upper electrode of the filletless chip resistor is connected to the land of the wiring board. The thickness of the electrode for solder bonding is secured by the upper layer electrode, and the separation layer is formed in advance along the first division groove so that the upper layer electrode thus thickened does not cover the first division groove. Accordingly, when the original plate is divided, the separation layer is divided, but the upper layer electrode is not divided, so that the occurrence of burrs and chips in the upper layer electrode can be avoided.
【0008】上層電極の高さは、配線基板のランドに対
するはんだ結合を確実なものとするため、保護膜の上面
と同程度とするか又はこの上面より若干突出させる。ま
た、上層電極は第2の分割溝にかからないように各絶縁
基板毎に独立に配設してもよいし、第2の分割溝を跨ぎ
ながら隣接する各絶縁基板間に亘って連設してもよい。[0008] The height of the upper layer electrode is approximately the same as or slightly protrudes from the upper surface of the protective film in order to secure the solder connection to the land of the wiring board. In addition, the upper electrode may be provided independently for each insulating substrate so as not to cover the second dividing groove, or may be continuously provided between adjacent insulating substrates while straddling the second dividing groove. Is also good.
【0009】本製造方法では、保護膜は単層構造であ
っても二層構造であってもよく、二層構造の場合、抵抗
膜に対するトリミングを下層保護膜上から施した後、上
層保護膜を被覆する。尚、保護膜(二層構造にあっては
上層保護膜)と分離層とは逐次形成することも同時に形
成することもできる。In the present manufacturing method, the protective film may have a single-layer structure or a two-layer structure. In the case of the two-layer structure, after trimming the resistive film from above the lower protective film, the protective film is formed. Is coated. The protective film (the upper protective film in the case of the two-layer structure) and the separation layer can be formed sequentially or simultaneously.
【0010】請求項2に記載した本発明に係るチップ抵
抗器の製造方法(以下、「本製造方法」という。)
は、配線基板のランドに対し電極の上面をはんだ結合さ
せるフィレットレス形のチップ抵抗器を製造する方法で
あって、互いに直交する第1の分割溝及び第2の分割溝
によって多数の絶縁基板を区画する原板上に当該第1の
分割溝を跨いで当該絶縁基板の両端部において一対の下
層電極を配設する工程と、前記下層電極間を連絡する抵
抗膜を配設する工程と、前記抵抗膜にトリミングを施す
工程と、前記絶縁基板の両端部において一対となり、前
記第1の分割溝及び第2の分割溝より内側の非被覆部を
残して、当該絶縁基板の全表面を保護膜で被覆する工程
と、前記非被覆部に上層電極を配設する工程と、前記原
板を前記第1の分割溝及び第2の分割溝に沿って分割す
る工程と、前記上層電極上にめっき膜を形成する工程と
を含むことを特徴とする。[0010] A method of manufacturing the chip resistor according to the present invention described in claim 2 (hereinafter referred to as "the present manufacturing method").
Is a method of manufacturing a filletless type chip resistor in which an upper surface of an electrode is solder-bonded to a land of a wiring board, and a large number of insulating substrates are formed by a first divided groove and a second divided groove which are orthogonal to each other. Arranging a pair of lower electrodes at both ends of the insulating substrate over the first division groove on the original plate to be partitioned, arranging a resistive film communicating between the lower electrodes, Trimming the film, and forming a pair at both ends of the insulating substrate, and protecting the entire surface of the insulating substrate with a protective film except for an uncovered portion inside the first and second dividing grooves. Coating, arranging an upper electrode on the uncoated portion, dividing the original plate along the first and second division grooves, and forming a plating film on the upper electrode. Forming step To.
【0011】本製造方法は、第1の分割溝及び第2の
分割溝の内側の絶縁基板の両端部(非被覆部)を除く絶
縁基板上の全面に保護膜(二重構造にあっては上層保護
膜)を形成し、この工程に続き、上記非被覆部に上層電
極を配設する点が本製造方法と異なり、その他の基本
的な工程は本製造方法と同様である。In this manufacturing method, a protective film (in the case of a double structure) is formed on the entire surface of the insulating substrate except for both ends (uncovered portions) of the insulating substrate inside the first dividing groove and the second dividing groove. An upper protective film is formed, and an upper electrode is disposed on the uncovered portion following this step, which is different from the present manufacturing method. Other basic steps are the same as the present manufacturing method.
【0012】本製造方法では、保護膜(二重構造にあ
っては上層保護膜)の第1の分割溝を跨ぐ部分が本製造
方法における分離層の役割を果たす他、第1の分割溝
及び第2の分割溝より内側の非被覆部に上層電極が形成
されるので、本製造方法によって得た複数のチップ抵
抗器を基板実装する際、第2の分割溝の分割面から隣り
合わせて接触配列しても、抵抗器間の短絡が生じず、実
装面積を有効に活用できる。In the present manufacturing method, the portion of the protective film (the upper protective film in the case of the double structure) straddling the first division groove serves as a separation layer in the present production method, and the first division groove and the first division groove are formed. Since the upper electrode is formed on the uncovered portion inside the second division groove, when mounting a plurality of chip resistors obtained by this manufacturing method on a substrate, the contact arrangement is made adjacent to the division surface of the second division groove. However, no short circuit occurs between the resistors, and the mounting area can be effectively used.
【0013】[0013]
【本発明の実施の形態】以下、本発明の好適な実施形態
を添付図面に基づいて説明する。Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
【0014】図1は本製造方法によって得たチップ抵
抗器10の平面図であり、図2は図1のA−A’断面図
である。チップ抵抗器10は、矩形チップ形状の絶縁基
板1と、絶縁基板1上の左右両端部に配設された一対の
下層電極2と、各下層電極2間を連絡する抵抗膜3と、
抵抗膜3を被覆する下層保護膜4と、下層保護膜4を被
覆する上層保護膜5と、絶縁基板1上の左右両端の下層
電極上に形成された分離層6と、下層電極2上の上層保
護膜5と分離層6との間に配設された上層電極7と、上
層電極7上に形成されためっき膜8とを備える。FIG. 1 is a plan view of a chip resistor 10 obtained by the present manufacturing method, and FIG. 2 is a sectional view taken along the line AA 'of FIG. The chip resistor 10 includes a rectangular chip-shaped insulating substrate 1, a pair of lower-layer electrodes 2 disposed on both right and left ends of the insulating substrate 1, and a resistance film 3 communicating between the lower-layer electrodes 2.
A lower protective film 4 covering the resistive film 3; an upper protective film 5 covering the lower protective film 4; a separation layer 6 formed on the lower electrode on the left and right ends on the insulating substrate 1; An upper electrode 7 is provided between the upper protective film 5 and the separation layer 6, and a plating film 8 formed on the upper electrode 7.
【0015】チップ抵抗器10の製造工程は次のように
なる。The manufacturing process of the chip resistor 10 is as follows.
【0016】工程1(図3参照);互いに直交する第1
の分割溝としての縦溝lと第2の分割溝としての横溝w
とによって多数の分割前の絶縁基板1が縦横に区画され
る、例えばアルミナセラミック等からなる原板の上面に
縦溝lを跨いで厚膜グレーズ系の導電材料からなる下層
電極2を配設する。 Step 1 (see FIG. 3);
Vertical groove 1 as a dividing groove and horizontal groove w as a second dividing groove
The lower electrode 2 made of a thick-film glaze-based conductive material is disposed on the upper surface of an original plate made of, for example, alumina ceramic or the like, which divides a large number of insulating substrates 1 before and after division.
【0017】工程2(図4参照);各下層電極2間を連
絡する厚膜グレーズ系の抵抗膜3を配設する。 Step 2 (see FIG. 4): A thick glaze-based resistive film 3 for connecting the lower electrodes 2 is provided.
【0018】工程3(図5参照);抵抗膜3の全面を厚
膜グレーズ系ガラスの下層保護膜4によって被覆する。 Step 3 (see FIG. 5): The entire surface of the resistive film 3 is covered with the lower protective film 4 of the thick glaze glass.
【0019】工程4(図6参照);下層保護膜4上から
抵抗膜3に対し抵抗値修正のためのレザートリミングを
施し、これによってトリミング溝3’が形成される。 Step 4 (see FIG. 6): Laser trimming for correcting the resistance value is performed on the resistive film 3 from above the lower protective film 4, thereby forming a trimming groove 3 '.
【0020】工程5(図7参照);下層保護膜4を上層
保護膜5によって覆い、トリミング溝3’を埋める。上
層保護膜5は横溝wを跨ぎながら縦方向に隣接する各絶
縁基板1間に渡って連設される。 Step 5 (see FIG. 7): The lower protective film 4 is covered with the upper protective film 5 to fill the trimming groove 3 '. The upper protective film 5 is provided continuously between the adjacent insulating substrates 1 in the vertical direction while straddling the horizontal groove w.
【0021】工程6(図7参照);縦溝lを比較的(下
層電極2に比べ)狭小に跨ぐと共に縦溝lに沿って(下
層電極2上を含む。)各絶縁基板1間に延長する分離層
6を形成する。尚、工程6を工程5と同時に行うことも
できる。 Step 6 (see FIG. 7): The longitudinal groove 1 is straddled relatively narrowly (compared with the lower electrode 2) and is extended between the insulating substrates 1 along the longitudinal groove 1 (including on the lower electrode 2). A separation layer 6 is formed. Step 6 can be performed simultaneously with step 5.
【0022】工程7(図8参照);上層保護膜5と分離
層6との間に上層電極7を配設する。 Step 7 (see FIG. 8): An upper electrode 7 is provided between the upper protective film 5 and the separation layer 6.
【0023】上層電極7の高さは上層保護膜5上面と同
じか又はこれより若干突出するよう設定され、この際、
上層電極7の材料を複数回重ねて形成することができ
る。また、工程5〜7において、上層保護膜5の材料と
して厚膜グレーズ系ガラスを採用する場合、分離層6も
同様の厚膜グレーズ系ガラスとすると共に、上層電極7
を厚膜グレーズ系導電材料とし、この厚膜グレーズ系導
電材料を、上層電極7が分離層6上の全面に及ばないよ
うに上層保護膜5の焼成温度と同一又はこれより低い焼
成温度のものとする。また一方、上層保護膜5の材料と
して樹脂系塗料を採用する場合、分離層6も同様の樹脂
系塗料とし、上層電極7も樹脂系導電塗料とする。The height of the upper electrode 7 is set so as to be equal to or slightly protrude from the upper surface of the upper protective film 5.
The material of the upper electrode 7 can be formed by overlapping a plurality of times. In the case where thick glass glaze glass is used as the material of the upper protective film 5 in the steps 5 to 7, the separation layer 6 is also made of the same thick glass glaze glass and the upper electrode 7
Is a thick film glaze-based conductive material having a firing temperature equal to or lower than the firing temperature of the upper protective film 5 so that the upper electrode 7 does not cover the entire surface of the separation layer 6. And On the other hand, when a resin-based paint is used as the material of the upper protective film 5, the separation layer 6 is also made of the same resin-based paint, and the upper electrode 7 is also made of a resin-based conductive paint.
【0024】工程8;原板を縦溝lに次いで横溝wに沿
って逐次分割し、縦溝lの分割によって分離層6が分割
されるものの、上層電極7は分割されない。 Step 8: The original plate is successively divided along the vertical groove 1 and then along the horizontal groove w. The separation of the separation layer 6 by the division of the vertical groove 1 does not divide the upper layer electrode 7.
【0025】工程9;上層電極7上にニッケルめっきと
はんだめっき(錫−鉛)とで構成しためっき膜8を形成
して、チップ抵抗器10が得られる。 Step 9: A plating film 8 composed of nickel plating and solder plating (tin-lead) is formed on the upper electrode 7 to obtain a chip resistor 10.
【0026】以上の実施形態では、図8に示すように、
上層電極7の上下端を横溝wの内側に配しているため、
複数のチップ抵抗器10を横溝wの分割面から隣り合わ
せて接触配列しても抵抗器10間同士の短絡が回避さ
れ、抵抗器10の実装面積を有効に活用できる。その一
方、上層電極7を横溝wを跨ぎながら縦方向に延長させ
ることもでき、この場合、横溝wにかかる上層電極7の
幅が狭いため、横溝wの分割は容易であり、上層電極7
の横溝wからの分割面に悪影響を及ぼすようなバリや欠
けは生じない。In the above embodiment, as shown in FIG.
Since the upper and lower ends of the upper electrode 7 are arranged inside the lateral groove w,
Even if a plurality of chip resistors 10 are arranged side by side in contact with the divided surface of the lateral groove w, a short circuit between the resistors 10 is avoided, and the mounting area of the resistors 10 can be effectively utilized. On the other hand, the upper electrode 7 can be extended in the vertical direction while straddling the horizontal groove w. In this case, since the width of the upper electrode 7 over the horizontal groove w is narrow, the division of the horizontal groove w is easy, and
No burrs or chips that adversely affect the divided surface from the lateral groove w are generated.
【0027】図9は本製造方法によって得たチップ抵
抗器20の平面図であり、図10は図9のB−B’断面
図である。尚、チップ抵抗器10と共通する部分は同じ
参照番号を付す。チップ抵抗器20におけるチップ抵抗
器10と異なる点は、独立した分離層6を設けず、上層
保護膜15を未被覆部17’を残して絶縁基板1上全面
に形成し、この上層保護膜15の縦溝lを跨ぐ部分に分
離層6の役割を担わせる点と、未被覆部17’が縦溝l
及び横溝wの内側に設定されるため、非被覆部17’に
配設される上層電極7が横溝wにかかることはない点で
ある。上層電極7が横溝wにかからないことにより、チ
ップ抵抗器20では横溝分割面からの隣接配列時の短絡
回避が常に得られる。FIG. 9 is a plan view of the chip resistor 20 obtained by the present manufacturing method, and FIG. 10 is a sectional view taken along the line BB 'of FIG. Parts common to the chip resistor 10 are denoted by the same reference numerals. The difference between the chip resistor 20 and the chip resistor 10 is that the upper protective film 15 is formed on the entire surface of the insulating substrate 1 except for the uncovered portion 17 ′ without providing the independent separating layer 6. And the uncovered portion 17 ′ is formed between the portion that straddles the vertical groove 1 and the uncovered portion 17 ′.
In addition, since it is set inside the horizontal groove w, the upper electrode 7 provided in the uncovered portion 17 'does not cover the horizontal groove w. Since the upper layer electrode 7 does not cover the lateral groove w, the chip resistor 20 can always avoid short circuit in the adjacent arrangement from the lateral groove dividing surface.
【0028】チップ抵抗器20の製造工程は、まず、チ
ップ抵抗器10について上述した工程1〜4と同様の工
程を経た後、図11に示すように、上層保護膜15を縦
溝l及び横溝wの内側で左右一対の非被覆部17’を除
く絶縁基板1全表面に形成し、次いで、非被覆部17’
に上層電極7を配設する。その後は上述した工程8及び
9となる。In the manufacturing process of the chip resistor 20, first, after the same processes as the above-described processes 1 to 4 for the chip resistor 10, as shown in FIG. formed on the entire surface of the insulating substrate 1 except for the pair of left and right uncovered portions 17 ′ inside w, and then the uncovered portions 17 ′
The upper electrode 7 is provided. Thereafter, steps 8 and 9 described above are performed.
【0029】[0029]
【発明の効果】以上述べたように、本製造方法では、
第1の分割溝に沿って分離層を形成することによって、
厚さを確保させた上層電極が第1の分割溝にかからない
ようにし、原板分割時に上層電極へのバリや欠けを回避
することができ、また、フィレットレス形のチップ抵抗
器として要求される、上面電極と実装基板のランドとの
はんだ結合に必要な占有面積を確実に確保することがで
き、チップ抵抗器の一層の小型化にも寄与する。As described above, in the present manufacturing method,
By forming the separation layer along the first dividing groove,
The upper layer electrode having the ensured thickness is prevented from covering the first dividing groove, and it is possible to avoid burrs and chipping of the upper layer electrode at the time of dividing the original plate, and is required as a filletless type chip resistor. An occupied area required for the solder connection between the upper surface electrode and the land of the mounting board can be reliably secured, which contributes to further downsizing of the chip resistor.
【0030】本製造方法では、本製造方法による利
点を具備する他、常に電極が第2の分割溝の分割面にか
からないため、複数のチップ抵抗器を第2の分割溝分割
面から隣接して配列しても隣接間同士の短絡が回避さ
れ、隣接間隔を縮めて実装面積を有効に活用することが
できる。In the present manufacturing method, in addition to having the advantages of the present manufacturing method, since the electrodes do not always contact the dividing surface of the second dividing groove, a plurality of chip resistors are arranged adjacent to the second dividing groove dividing surface. Even if they are arranged, a short circuit between the adjacent members can be avoided, and the adjacent space can be reduced to effectively use the mounting area.
【図1】本発明によって得たチップ抵抗器を示す平面図
である。FIG. 1 is a plan view showing a chip resistor obtained according to the present invention.
【図2】図1のA−A’断面図である。FIG. 2 is a sectional view taken along line A-A 'of FIG.
【図3】本発明の工程1を略示する平面図である。FIG. 3 is a plan view schematically showing a step 1 of the present invention.
【図4】本発明の工程2を略示する平面図である。FIG. 4 is a plan view schematically showing step 2 of the present invention.
【図5】本発明の工程3を略示する平面図である。FIG. 5 is a plan view schematically showing a step 3 of the present invention.
【図6】本発明の工程4を略示する平面図である。FIG. 6 is a plan view schematically showing step 4 of the present invention.
【図7】本発明の工程5及び6を略示する平面図であ
る。FIG. 7 is a plan view schematically showing steps 5 and 6 of the present invention.
【図8】本発明の工程7を略示する平面図である。FIG. 8 is a plan view schematically showing step 7 of the present invention.
【図9】別の本発明によって得たチップ抵抗器を示す平
面図である。FIG. 9 is a plan view showing another chip resistor obtained according to the present invention.
【図10】図9のB−B’断面図である。FIG. 10 is a sectional view taken along line B-B 'of FIG.
【図11】別の本発明の上層保護膜形成工程を略示する
平面図である。FIG. 11 is a plan view schematically showing another upper protective film forming step of the present invention.
1 絶縁基板 2 下層電極 3 抵抗膜 3’ トリミング溝 4 下層保護膜 5,15 上層保護膜 6 分離層 7 上層電極 8 めっき膜 10,20 チップ抵抗器 17’ 非被覆部 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Lower electrode 3 Resistive film 3 'Trimming groove 4 Lower protective film 5, 15 Upper protective film 6 Separation layer 7 Upper electrode 8 Plating film 10, 20 Chip resistor 17' Uncovered part
【手続補正書】[Procedure amendment]
【提出日】平成11年8月2日[Submission date] August 2, 1999
【手続補正1】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】全文[Correction target item name] Full text
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【書類名】 明細書[Document Name] Statement
【発明の名称】 チップ抵抗器とその製造方法[Title of Invention] chip resistor and a method of manufacturing
【特許請求の範囲】[Claims]
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【発明が属する技術分野】本発明はチップ抵抗器と、そ
の製造方法に関し、特に配線基板のランドに対しチップ
抵抗器の端面電極側方向にはんだフィレットを設けるこ
となくはんだ結合可能な、いわゆるフィレットレス形の
チップ抵抗器と、その製造方法に関する。[0001] The present invention relates to a chip resistor and a chip resistor.
In particular, the present invention relates to a so-called filletless type chip resistor which can be solder-bonded to a land of a wiring board in a direction of an end face electrode side of the chip resistor without providing a solder fillet , and a method of manufacturing the same .
【0002】[0002]
【従来の技術】チップ抵抗器では、従来から、配線基板
のランドと抵抗器の端面電極とをはんだフィレットによ
ってはんだ結合させているが、近年の電子機器の超小型
化、携帯化等に伴い電子部品の実装密度の高集積化の要
求が高まり、はんだ占有面積を極力減少させるべく、ラ
ンドに対しチップ抵抗器の端面電極側方向にはんだフィ
レットを設けることなく抵抗器の上面電極をはんだ結合
させるフィレットレス形のチップ抵抗器が切望されてい
る。2. Description of the Related Art In a chip resistor, a land of a wiring board and an end face electrode of the resistor have been conventionally soldered to each other by a solder fillet. The demand for higher integration of component mounting density has increased, and in order to reduce the solder occupation area as much as possible, a fillet that solders the upper electrode of the resistor without providing a solder fillet in the direction of the end face electrode side of the chip resistor with respect to the land There is a long-felt need for a chip-type chip resistor.
【0003】かかるフィレットレス形のチップ抵抗器で
は、電極の高さを、電極間の抵抗膜を覆う保護膜上面と
同程度とするか又はこれより若干突出させる必要がある
ため、その分、電極を厚くしなけらばならない。In such a filletless type chip resistor, the height of the electrodes needs to be equal to or slightly protrude from the upper surface of the protective film covering the resistive film between the electrodes. Must be thicker.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、チップ
抵抗器は、縦横の分割溝によって多数の絶縁基板が区画
される原板上に電極、抵抗膜及び保護膜を所要に配設し
た後、上記分割溝に沿って分割して製造されるが、分割
溝を跨いで電極が設けられるため、電極の厚さをを確保
すると、原板分割時の電極の分割が円滑に行われず、電
極の分割面にバリや欠けが生じるという問題がある。こ
のようなバリや欠けは、例えば製造工程でのシュートの
詰まりや実装機でのテーピングのキャビティからの吸着
ミスの要因となったり、はんだ結合面積の減少によるは
んだ結合の低下を招き、また、抵抗器を一層小型化する
に当たっての阻害要因ともなる。However, in the chip resistor, electrodes, a resistive film, and a protective film are provided on an original plate on which a large number of insulating substrates are divided by vertical and horizontal dividing grooves, and then the dividing grooves are formed. However, since the electrodes are provided across the dividing grooves, if the thickness of the electrodes is ensured, the division of the electrodes during the original plate division is not performed smoothly, and flash is formed on the divided surfaces of the electrodes. There is a problem that chipping occurs. Such burrs and chips may cause, for example, clogging of a chute in a manufacturing process, a suction error from a taping cavity in a mounting machine, or a decrease in a solder bonding area due to a decrease in a solder bonding area. It also becomes a hindrance factor in further downsizing the vessel.
【0005】本発明は、以上のような問題点に鑑みてな
されたものであり、その目的は、原板分割時に電極にバ
リや欠けが生じることがなく、フィレットレス形の抵抗
器としての電極の厚さを確保できるチップ抵抗器とその
製造方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to prevent burrs or chips from being generated in an electrode when dividing an original plate, and to provide an electrode as a filletless type resistor. chip resistor which can ensure a thickness of and to provide a <br/> manufacturing method.
【0006】[0006]
【課題を解決するための手段】請求項1に記載した本発
明に係るチップ抵抗器(以下「本発明」という)は、
配線基板のランドに対し電極の上面をはんだ結合させる
フィットレス形のチップ抵抗器であって、該チップ抵抗
器が、絶縁基板の左右両端部に配設した一対の下層電極
と、前記下層電極間に連絡してトリミングを施こした抵
抗膜と、前記抵抗膜を被覆した保護膜と、前記絶縁基板
上の左右両端の下層電極上に形成した分離層と、前記下
層電極上の前記保護膜と前記分離層の間で、しかも前記
絶縁基板の上下両端より内側において、前記保護膜の上
面と同程度以上高く配設した上層電極と、を含むことを
特徴とする。上記本発明では、上層電極を絶縁基板端
に沿って設けた分離層の内側に配設したので、上層電極
自身の分割によるバリや欠けを防止し、また上層電極を
保護膜の上面より高くすることで配線基板へのはんだ結
合を確実なものとした。請求項2に記載した本発明に係
るチップ抵抗器の製造方法(以下、「本製造方法」と
いう)は、配線基板のランドに対し電極の上面をはんだ
結合させるフィレットレス形のチップ抵抗器を製造する
方法であって、互いに直交する第1の分割溝及び第2の
分割溝によって多数の絶縁基板を区画する原板上に当該
第1の分割溝を跨いで当該絶縁基板の両端部において一
対となる下層電極を配設する工程と、前記下層電極間を
連絡する抵抗膜を配設する工程と、前記抵抗膜にトリミ
ングを施す工程と、前記抵抗膜を保護膜で被覆する工程
と、前記第1の分割溝を比較的狭小に跨ぎ且つ当該第1
の分割溝に沿って延長する分離層を形成する工程と、前
記保護膜と前記分離層との間に上層電極を配設する工程
と、前記原板を前記第1の分割溝及び第2の分割溝に沿
って分割する工程と、前記上層電極上にめっき膜を形成
する工程とを含むことを特徴とする。Means for Solving the Problems The present invention according to claim 1
The chip resistor according to the present invention (hereinafter referred to as “the present invention”)
Solder the upper surface of the electrode to the land of the wiring board
A fitless type chip resistor, wherein the chip resistor
A pair of lower electrodes arranged on both left and right ends of the insulating substrate
And the trimmed contact between the lower electrodes
A resistive film, a protective film covering the resistive film, and the insulating substrate
A separation layer formed on the lower electrode on both ends on the upper and lower sides,
Between the protective film on the layer electrode and the separation layer, and
On the inner side of the upper and lower ends of the insulating substrate,
And an upper electrode disposed at least as high as the surface.
Features. In the present invention, the upper electrode is connected to the edge of the insulating substrate.
Because it was arranged inside the separation layer provided along
Prevents burrs and chipping due to its own division,
Solder to the wiring board by making it higher than the upper surface of the protective film
The combination was assured. According to a second aspect of the present invention, there is provided a chip resistor manufacturing method (hereinafter, referred to as "the present manufacturing method") for manufacturing a filletless chip resistor in which an upper surface of an electrode is soldered to a land of a wiring board. A first divisional groove and a second divisional groove, which are orthogonal to each other, form a pair at both ends of the insulating substrate over the first divisional groove on an original plate that partitions a large number of insulating substrates. Arranging a lower electrode, arranging a resistive film communicating between the lower electrodes, trimming the resistive film, covering the resistive film with a protective film, Of the first groove is relatively narrow.
Forming a separation layer extending along the division groove, arranging an upper layer electrode between the protective film and the separation layer, and dividing the original plate into the first division groove and the second division groove. The method includes a step of dividing along the groove and a step of forming a plating film on the upper electrode.
【0007】即ち、本製造方法では、電極を下層電極
と上層電極とからなる二層構造として、下層電極に抵抗
膜を連接する一方、配線基板のランドにフィレットレス
形チップ抵抗器の上面電極をはんだ結合させるための電
極の厚さを上層電極によって確保し、このように厚膜と
した上層電極が第1の分割溝にかからないように第1の
分割溝に沿って分離層を先行形成することにより、原板
分割時に分離層は分割するものの、上層電極は分割され
ず、従って、上層電極におけるバリや欠けの発生を回避
するこができる。That is, in this manufacturing method, the electrode has a two-layer structure including a lower electrode and an upper electrode, and a resistive film is connected to the lower electrode, while the upper electrode of the filletless chip resistor is connected to the land of the wiring board. The thickness of the electrode for solder bonding is secured by the upper layer electrode, and the separation layer is formed in advance along the first division groove so that the upper layer electrode thus thickened does not cover the first division groove. Accordingly, when the original plate is divided, the separation layer is divided, but the upper layer electrode is not divided, so that the occurrence of burrs and chips in the upper layer electrode can be avoided.
【0008】上層電極の高さは、配線基板のランドに対
するはんだ結合を確実なものとするため、保護膜の上面
と同程度とするか又はこの上面より若干突出させる。ま
た、上層電極は第2の分割溝にかからないように各絶縁
基板毎に独立に配設してもよいし、第2の分割溝を跨ぎ
ながら隣接する各絶縁基板間に亘って連設してもよい。[0008] The height of the upper layer electrode is approximately the same as or slightly protrudes from the upper surface of the protective film in order to secure the solder connection to the land of the wiring board. In addition, the upper electrode may be provided independently for each insulating substrate so as not to cover the second dividing groove, or may be continuously provided between adjacent insulating substrates while straddling the second dividing groove. Is also good.
【0009】本製造方法では、保護膜は単層構造であ
っても二層構造であってもよく、二層構造の場合、抵抗
膜に対するトリミングを下層保護膜上から施した後、上
層保護膜を被覆する。尚、保護膜(二層構造にあっては
上層保護膜)と分離層とは逐次形成することも同時に形
成することもできる。In the present manufacturing method, the protective film may have a single-layer structure or a two-layer structure. In the case of the two-layer structure, after trimming the resistive film from above the lower protective film, the protective film is formed. Is coated. The protective film (the upper protective film in the case of the two-layer structure) and the separation layer can be formed sequentially or simultaneously.
【0010】請求項3に記載した発明に係るチップ抵抗
器(以下「本発明」という)は、配線基板のランドに
対し電極の上面をはんだ結合させるフィットレス形のチ
ップ抵抗器であって、該チップ抵抗器が、絶縁基板の左
右両端部に配設した一対の下層電極と、前記下層電極間
に連絡してトリミングを施こした抵抗膜と、前記絶縁基
板上の左右及び上下両端より内側の前記下層電極上を非
被覆部として残して、当該絶縁基板の全表面を被覆した
保護膜と、前記保護膜に囲まれた非被覆部上に、前記保
護膜の上面と同程度以上に高く配設した上層電極と、を
含むことを特徴とする。そして、上記本発明では、上
記本発明と同じである上層電極を分割溝となる絶縁基
板端から引き離すことでバリや欠けを防止し、配線基板
へのはんだ付けを確実にするだけでなく、保護膜で囲ま
れた非被覆部上に上層電極を配設することで、上層電極
を絶縁基板端から距離を置くための分離層の形成を省く
ことができる。請求項4に記載した本発明に係るチップ
抵抗器の製造方法(以下、「本製造方法」という。)
は、配線基板のランドに対し電極の上面をはんだ結合さ
せるフィレットレス形のチップ抵抗器を製造する方法で
あって、互いに直交する第1の分割溝及び第2の分割溝
によって多数の絶縁基板を区画する原板上に当該第1の
分割溝を跨いで当該絶縁基板の両端部において一対の下
層電極を配設する工程と、前記下層電極間を連絡する抵
抗膜を配設する工程と、前記抵抗膜にトリミングを施す
工程と、前記絶縁基板の両端部において一対となり、前
記第1の分割溝及び第2の分割溝より内側の非被覆部を
残して、当該絶縁基板の全表面を保護膜で被覆する工程
と、前記非被覆部に上層電極を配設する工程と、前記原
板を前記第1の分割溝及び第2の分割溝に沿って分割す
る工程と、前記上層電極上にめっき膜を形成する工程と
を含むことを特徴とする。[0010] The chip resistor according to the third aspect of the present invention.
(Hereinafter referred to as "the present invention")
Fitless type chip that solders the upper surface of the counter electrode
Wherein the chip resistor is located on the left side of the insulating substrate.
A pair of lower electrodes disposed at both right ends, between the lower electrodes;
Contact the trimmed resistive film with the insulating substrate
Non-contact on the lower electrode inside the left, right, upper and lower ends of the plate
The entire surface of the insulating substrate was covered, leaving as a covering portion
The protective film and the uncovered portion surrounded by the protective film are covered with the protective film.
The upper electrode, which is arranged at least as high as the upper surface of the protective film,
It is characterized by including. In the present invention,
The same upper layer electrode as that of the present invention is used as an insulating base for forming a dividing groove.
Prevents burrs and chips by separating from the board edge,
Not only ensures soldering to
By disposing the upper layer electrode on the uncovered part
The formation of a separation layer to keep the distance from the edge of the insulating substrate
be able to. The manufacturing method of the chip resistor according to the present invention described in claim 4 (hereinafter referred to as “the present manufacturing method”).
Is a method of manufacturing a filletless type chip resistor in which an upper surface of an electrode is solder-bonded to a land of a wiring board, and a large number of insulating substrates are formed by a first divided groove and a second divided groove which are orthogonal to each other. Arranging a pair of lower electrodes at both ends of the insulating substrate over the first division groove on the original plate to be partitioned, arranging a resistive film communicating between the lower electrodes, Trimming the film, and forming a pair at both ends of the insulating substrate, and protecting the entire surface of the insulating substrate with a protective film except for an uncovered portion inside the first and second dividing grooves. Coating, arranging an upper electrode on the uncoated portion, dividing the original plate along the first and second division grooves, and forming a plating film on the upper electrode. Forming step To.
【0011】本製造方法は、第1の分割溝及び第2の
分割溝の内側の絶縁基板の両端部(非被覆部)を除く絶
縁基板上の全面に保護膜(二重構造にあっては上層保護
膜)を形成し、この工程に続き、上記非被覆部に上層電
極を配設する点が本製造方法と異なり、その他の基本
的な工程は本製造方法と同様である。In this manufacturing method, a protective film (in the case of a double structure) is formed on the entire surface of the insulating substrate except for both ends (uncovered portions) of the insulating substrate inside the first dividing groove and the second dividing groove. An upper protective film is formed, and an upper electrode is disposed on the uncovered portion following this step, which is different from the present manufacturing method. Other basic steps are the same as the present manufacturing method.
【0012】本製造方法では、保護膜(二重構造にあ
っては上層保護膜)の第1の分割溝を跨ぐ部分が本製造
方法における分離層の役割を果たす他、第1の分割溝
及び第2の分割溝より内側の非被覆部に上層電極が形成
されるので、本製造方法によって得た複数のチップ抵
抗器を基板実装する際、第2の分割溝の分割面から隣り
合わせて接触配列しても、抵抗器間の短絡が生じず、実
装面積を有効に活用できる。In the present manufacturing method, the portion of the protective film (the upper protective film in the case of the double structure) straddling the first division groove serves as a separation layer in the present production method, and the first division groove and the first division groove are formed. Since the upper electrode is formed on the uncovered portion inside the second division groove, when mounting a plurality of chip resistors obtained by this manufacturing method on a substrate, the contact arrangement is made adjacent to the division surface of the second division groove. However, no short circuit occurs between the resistors, and the mounting area can be effectively used.
【0013】[0013]
【本発明の実施の形態】以下、本発明の好適な実施形態
を添付図面に基づいて説明する。Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
【0014】図1は本製造方法によって得たチップ抵
抗器10の平面図であり、図2は図1のA−A’断面図
である。チップ抵抗器10は、矩形チップ形状の絶縁基
板1と、絶縁基板1上の左右両端部に配設された一対の
下層電極2と、各下層電極2間を連絡する抵抗膜3と、
抵抗膜3を被覆する下層保護膜4と、下層保護膜4を被
覆する上層保護膜5と、絶縁基板1上の左右両端の下層
電極上に形成された分離層6と、下層電極2上の上層保
護膜5と分離層6との間に配設された上層電極7と、上
層電極7上に形成されためっき膜8とを備える。FIG. 1 is a plan view of a chip resistor 10 obtained by the present manufacturing method, and FIG. 2 is a sectional view taken along the line AA 'of FIG. The chip resistor 10 includes a rectangular chip-shaped insulating substrate 1, a pair of lower-layer electrodes 2 disposed on both right and left ends of the insulating substrate 1, and a resistance film 3 communicating between the lower-layer electrodes 2.
A lower protective film 4 covering the resistive film 3; an upper protective film 5 covering the lower protective film 4; a separation layer 6 formed on the lower electrode on the left and right ends on the insulating substrate 1; An upper electrode 7 is provided between the upper protective film 5 and the separation layer 6, and a plating film 8 formed on the upper electrode 7.
【0015】チップ抵抗器10の製造工程は次のように
なる。The manufacturing process of the chip resistor 10 is as follows.
【0016】工程1(図3参照);互いに直交する第1
の分割溝としての縦溝lと第2の分割溝としての横溝w
とによって多数の分割前の絶縁基板1が縦横に区画され
る、例えばアルミナセラミック等からなる原板の上面に
縦溝lを跨いで厚膜グレーズ系の導電材料からなる下層
電極2を配設する。 Step 1 (see FIG. 3);
Vertical groove 1 as a dividing groove and horizontal groove w as a second dividing groove
The lower electrode 2 made of a thick-film glaze-based conductive material is disposed on the upper surface of an original plate made of, for example, alumina ceramic or the like, which divides a large number of insulating substrates 1 before and after division.
【0017】工程2(図4参照);各下層電極2間を連
絡する厚膜グレーズ系の抵抗膜3を配設する。 Step 2 (see FIG. 4): A thick glaze-based resistive film 3 for connecting the lower electrodes 2 is provided.
【0018】工程3(図5参照);抵抗膜3の全面を厚
膜グレーズ系ガラスの下層保護膜4によって被覆する。 Step 3 (see FIG. 5): The entire surface of the resistive film 3 is covered with the lower protective film 4 of the thick glaze glass.
【0019】工程4(図6参照);下層保護膜4上から
抵抗膜3に対し抵抗値修正のためのレザートリミングを
施し、これによってトリミング溝3’が形成される。 Step 4 (see FIG. 6): Laser trimming for correcting the resistance value is performed on the resistive film 3 from above the lower protective film 4, thereby forming a trimming groove 3 '.
【0020】工程5(図7参照);下層保護膜4を上層
保護膜5によって覆い、トリミング溝3’を埋める。上
層保護膜5は横溝wを跨ぎながら縦方向に隣接する各絶
縁基板1間に渡って連設される。 Step 5 (see FIG. 7): The lower protective film 4 is covered with the upper protective film 5 to fill the trimming groove 3 '. The upper protective film 5 is provided continuously between the adjacent insulating substrates 1 in the vertical direction while straddling the horizontal groove w.
【0021】工程6(図7参照);縦溝lを比較的(下
層電極2に比べ)狭小に跨ぐと共に縦溝lに沿って(下
層電極2上を含む。)各絶縁基板1間に延長する分離層
6を形成する。尚、工程6を工程5と同時に行うことも
できる。 Step 6 (see FIG. 7): The longitudinal groove 1 is straddled relatively narrowly (compared with the lower electrode 2) and is extended between the insulating substrates 1 along the longitudinal groove 1 (including on the lower electrode 2). A separation layer 6 is formed. Step 6 can be performed simultaneously with step 5.
【0022】工程7(図8参照);上層保護膜5と分離
層6との間に上層電極7を配設する。 Step 7 (see FIG. 8): An upper electrode 7 is provided between the upper protective film 5 and the separation layer 6.
【0023】上層電極7の高さは上層保護膜5上面と同
じか又はこれより若干突出するよう設定され、この際、
上層電極7の材料を複数回重ねて形成することができ
る。また、工程5〜7において、上層保護膜5の材料と
して厚膜グレーズ系ガラスを採用する場合、分離層6も
同様の厚膜グレーズ系ガラスとすると共に、上層電極7
を厚膜グレーズ系導電材料とし、この厚膜グレーズ系導
電材料を、上層電極7が分離層6上の全面に及ばないよ
うに上層保護膜5の焼成温度と同一又はこれより低い焼
成温度のものとする。また一方、上層保護膜5の材料と
して樹脂系塗料を採用する場合、分離層6も同様の樹脂
系塗料とし、上層電極7も樹脂系導電塗料とする。The height of the upper electrode 7 is set so as to be equal to or slightly protrude from the upper surface of the upper protective film 5.
The material of the upper electrode 7 can be formed by overlapping a plurality of times. In the case where thick glass glaze glass is used as the material of the upper protective film 5 in the steps 5 to 7, the separation layer 6 is also made of the same thick glass glaze glass and the upper electrode 7
Is a thick film glaze-based conductive material having a firing temperature equal to or lower than the firing temperature of the upper protective film 5 so that the upper electrode 7 does not cover the entire surface of the separation layer 6. And On the other hand, when a resin-based paint is used as the material of the upper protective film 5, the separation layer 6 is also made of the same resin-based paint, and the upper electrode 7 is also made of a resin-based conductive paint.
【0024】工程8;原板を縦溝lに次いで横溝wに沿
って逐次分割し、縦溝lの分割によって分離層6が分割
されるものの、上層電極7は分割されない。 Step 8: The original plate is successively divided along the vertical groove 1 and then along the horizontal groove w. The separation of the separation layer 6 by the division of the vertical groove 1 does not divide the upper layer electrode 7.
【0025】工程9;上層電極7上にニッケルめっきと
はんだめっき(錫−鉛)とで構成しためっき膜8を形成
して、チップ抵抗器10が得られる。 Step 9: A plating film 8 composed of nickel plating and solder plating (tin-lead) is formed on the upper electrode 7 to obtain a chip resistor 10.
【0026】以上の実施形態では、図8に示すように、
上層電極7の上下端を横溝wの内側に配しているため、
複数のチップ抵抗器10を横溝wの分割面から隣り合わ
せて接触配列しても抵抗器10間同士の短絡が回避さ
れ、抵抗器10の実装面積を有効に活用できる。その一
方、上層電極7を横溝wを跨ぎながら縦方向に延長させ
ることもでき、この場合、横溝wにかかる上層電極7の
幅が狭いため、横溝wの分割は容易であり、上層電極7
の横溝wからの分割面に悪影響を及ぼすようなバリや欠
けは生じない。In the above embodiment, as shown in FIG.
Since the upper and lower ends of the upper electrode 7 are arranged inside the lateral groove w,
Even if a plurality of chip resistors 10 are arranged side by side in contact with the divided surface of the lateral groove w, a short circuit between the resistors 10 is avoided, and the mounting area of the resistors 10 can be effectively utilized. On the other hand, the upper electrode 7 can be extended in the vertical direction while straddling the horizontal groove w. In this case, since the width of the upper electrode 7 over the horizontal groove w is narrow, the division of the horizontal groove w is easy, and
No burrs or chips that adversely affect the divided surface from the lateral groove w are generated.
【0027】図9は本製造方法によって得たチップ抵
抗器20の平面図であり、図10は図9のB−B’断面
図である。尚、チップ抵抗器10と共通する部分は同じ
参照番号を付す。チップ抵抗器20におけるチップ抵抗
器10と異なる点は、独立した分離層6を設けず、上層
保護膜15を未被覆部17’を残して絶縁基板1上全面
に形成し、この上層保護膜15の縦溝lを跨ぐ部分に分
離層6の役割を担わせる点と、未被覆部17’が縦溝l
及び横溝wの内側に設定されるため、非被覆部17’に
配設される上層電極7が横溝wにかかることはない点で
ある。上層電極7が横溝wにかからないことにより、チ
ップ抵抗器20では横溝分割面からの隣接配列時の短絡
回避が常に得られる。FIG. 9 is a plan view of the chip resistor 20 obtained by the present manufacturing method, and FIG. 10 is a sectional view taken along the line BB 'of FIG. Parts common to the chip resistor 10 are denoted by the same reference numerals. The difference between the chip resistor 20 and the chip resistor 10 is that the upper protective film 15 is formed on the entire surface of the insulating substrate 1 except for the uncovered portion 17 ′ without providing the independent separating layer 6. And the uncovered portion 17 ′ is formed between the portion that straddles the vertical groove 1 and the uncovered portion 17 ′.
In addition, since it is set inside the horizontal groove w, the upper electrode 7 provided in the uncovered portion 17 'does not cover the horizontal groove w. Since the upper layer electrode 7 does not cover the lateral groove w, the chip resistor 20 can always avoid short circuit in the adjacent arrangement from the lateral groove dividing surface.
【0028】チップ抵抗器20の製造工程は、まず、チ
ップ抵抗器10について上述した工程1〜4と同様の工
程を経た後、図11に示すように、上層保護膜15を縦
溝l及び横溝wの内側で左右一対の非被覆部17’を除
く絶縁基板1全表面に形成し、次いで、非被覆部17’
に上層電極7を配設する。その後は上述した工程8及び
9となる。In the manufacturing process of the chip resistor 20, first, after the same processes as the above-described processes 1 to 4 for the chip resistor 10, as shown in FIG. formed on the entire surface of the insulating substrate 1 except for the pair of left and right uncovered portions 17 ′ inside w, and then the uncovered portions 17 ′
The upper electrode 7 is provided. Thereafter, steps 8 and 9 described above are performed.
【0029】[0029]
【発明の効果】以上述べたように、本製造方法では、
第1の分割溝に沿って分離層を形成することによって、
厚さを確保させた上層電極が第1の分割溝にかからない
ようにし、原板分割時に上層電極へのバリや欠けを回避
することができ、また、フィレットレス形のチップ抵抗
器として要求される、上面電極と実装基板のランドとの
はんだ結合に必要な占有面積を確実に確保することがで
き、チップ抵抗器の一層の小型化にも寄与する。As described above, in the present manufacturing method,
By forming the separation layer along the first dividing groove,
The upper layer electrode having the ensured thickness is prevented from covering the first dividing groove, and it is possible to avoid burrs and chipping of the upper layer electrode at the time of dividing the original plate, and is required as a filletless type chip resistor. An occupied area required for the solder connection between the upper surface electrode and the land of the mounting board can be reliably secured, which contributes to further downsizing of the chip resistor.
【0030】本製造方法では、本製造方法による利
点を具備する他、常に電極が第2の分割溝の分割面にか
からないため、複数のチップ抵抗器を第2の分割溝分割
面から隣接して配列しても隣接間同士の短絡が回避さ
れ、隣接間隔を縮めて実装面積を有効に活用することが
できる。In the present manufacturing method, in addition to having the advantages of the present manufacturing method, since the electrodes do not always contact the dividing surface of the second dividing groove, a plurality of chip resistors are arranged adjacent to the second dividing groove dividing surface. Even if they are arranged, a short circuit between the adjacent members can be avoided, and the adjacent space can be reduced to effectively use the mounting area.
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明によって得たチップ抵抗器を示す平面図
である。FIG. 1 is a plan view showing a chip resistor obtained according to the present invention.
【図2】図1のA−A’断面図である。FIG. 2 is a sectional view taken along line A-A 'of FIG.
【図3】本発明の工程1を略示する平面図である。FIG. 3 is a plan view schematically showing a step 1 of the present invention.
【図4】本発明の工程2を略示する平面図である。FIG. 4 is a plan view schematically showing step 2 of the present invention.
【図5】本発明の工程3を略示する平面図である。FIG. 5 is a plan view schematically showing a step 3 of the present invention.
【図6】本発明の工程4を略示する平面図である。FIG. 6 is a plan view schematically showing step 4 of the present invention.
【図7】本発明の工程5及び6を略示する平面図であ
る。FIG. 7 is a plan view schematically showing steps 5 and 6 of the present invention.
【図8】本発明の工程7を略示する平面図である。FIG. 8 is a plan view schematically showing step 7 of the present invention.
【図9】別の本発明によって得たチップ抵抗器を示す平
面図である。FIG. 9 is a plan view showing another chip resistor obtained according to the present invention.
【図10】図9のB−B’断面図である。FIG. 10 is a sectional view taken along line B-B 'of FIG.
【図11】別の本発明の上層保護膜形成工程を略示する
平面図である。FIG. 11 is a plan view schematically showing another upper protective film forming step of the present invention.
【符号の説明】 1 絶縁基板 2 下層電極 3 抵抗膜 3’ トリミング溝 4 下層保護膜 5,15 上層保護膜 6 分離層 7 上層電極 8 めっき膜 10,20 チップ抵抗器 17’ 非被覆部[Description of Signs] 1 Insulating substrate 2 Lower electrode 3 Resistive film 3 'Trimming groove 4 Lower protective film 5, 15 Upper protective film 6 Separation layer 7 Upper electrode 8 Plating film 10, 20 Chip resistor 17' Uncovered portion
Claims (2)
んだ結合させるフィレットレス形のチップ抵抗器を製造
する方法であって、 互いに直交する第1の分割溝及び第2の分割溝によって
多数の絶縁基板を区画する原板上に当該第1の分割溝を
跨いで当該絶縁基板の両端部において一対となる下層電
極を配設する工程と、 前記下層電極間を連絡する抵抗膜を配設する工程と、 前記抵抗膜にトリミングを施す工程と、 前記抵抗膜を保護膜で被覆する工程と、 前記第1の分割溝を比較的狭小に跨ぎ且つ当該第1の分
割溝に沿って延長する分離層を形成する工程と、 前記保護膜と前記分離層との間に上層電極を配設する工
程と、 前記原板を前記第1の分割溝及び第2の分割溝に沿って
分割する工程と、 前記上層電極上にめっき膜を形成する工程とを含むこと
を特徴とするチップ抵抗器の製造方法。1. A method for manufacturing a filletless type chip resistor in which an upper surface of an electrode is solder-bonded to a land of a wiring board, wherein a plurality of first division grooves and a plurality of second division grooves orthogonal to each other are provided. Arranging a pair of lower electrodes at both ends of the insulating substrate over the first division groove on an original plate for partitioning the insulating substrate; and arranging a resistive film communicating between the lower electrodes. A step of trimming the resistance film; a step of covering the resistance film with a protective film; and a separation layer extending relatively narrowly over the first division groove and extending along the first division groove. Forming an upper electrode between the protective film and the separation layer; dividing the original plate along the first and second division grooves; Step of forming a plating film on the upper electrode Method of manufacturing a chip resistor which comprises a.
んだ結合させるフィレットレス形のチップ抵抗器を製造
する方法であって、 互いに直交する第1の分割溝及び第2の分割溝によって
多数の絶縁基板を区画する原板上に当該第1の分割溝を
跨いで当該絶縁基板の両端部において一対の下層電極を
配設する工程と、 前記下層電極間を連絡する抵抗膜を配設する工程と、 前記抵抗膜にトリミングを施す工程と、 前記絶縁基板の両端部において一対となり、前記第1の
分割溝及び第2の分割溝より内側の非被覆部を残して、
当該絶縁基板の全表面を保護膜で被覆する工程と、 前記非被覆部に上層電極を配設する工程と、 前記原板を前記第1の分割溝及び第2の分割溝に沿って
分割する工程と、 前記上層電極上にめっき膜を形成する工程とを含むこと
を特徴とするチップ抵抗器の製造方法。2. A method of manufacturing a filletless type chip resistor in which an upper surface of an electrode is solder-bonded to a land of a wiring board, wherein a plurality of first and second divisional grooves are orthogonal to each other. A step of disposing a pair of lower electrodes at both ends of the insulating substrate over the first division groove on an original plate that partitions the insulating substrate; and a step of disposing a resistive film communicating between the lower electrodes. Trimming the resistive film; and forming a pair at both end portions of the insulating substrate, leaving an uncovered portion inside the first and second divisional grooves,
A step of covering the entire surface of the insulating substrate with a protective film; a step of arranging an upper layer electrode on the uncovered portion; and a step of dividing the original plate along the first and second division grooves. And forming a plating film on the upper electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10112316A JP3041684B2 (en) | 1998-04-22 | 1998-04-22 | Chip resistor and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10112316A JP3041684B2 (en) | 1998-04-22 | 1998-04-22 | Chip resistor and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11307320A true JPH11307320A (en) | 1999-11-05 |
JP3041684B2 JP3041684B2 (en) | 2000-05-15 |
Family
ID=14583627
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10112316A Expired - Lifetime JP3041684B2 (en) | 1998-04-22 | 1998-04-22 | Chip resistor and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3041684B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015088533A (en) * | 2013-10-29 | 2015-05-07 | パナソニックIpマネジメント株式会社 | Method of manufacturing chip resistor |
-
1998
- 1998-04-22 JP JP10112316A patent/JP3041684B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015088533A (en) * | 2013-10-29 | 2015-05-07 | パナソニックIpマネジメント株式会社 | Method of manufacturing chip resistor |
Also Published As
Publication number | Publication date |
---|---|
JP3041684B2 (en) | 2000-05-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5604328A (en) | Multilayer electronic component | |
EP0637828B1 (en) | Multilayer electronic component, method of manufacturing the same and method of measuring characteristics of the same | |
JP3147666B2 (en) | Multilayer electronic component and method of manufacturing the same | |
US6760227B2 (en) | Multilayer ceramic electronic component and manufacturing method thereof | |
JP2976049B2 (en) | Multilayer electronic components | |
US20050039946A1 (en) | Electronic circuit unit and method of manufacturing same | |
US7660132B2 (en) | Covered multilayer module | |
JPH11288839A (en) | Laminated chip type electronic component and manufacture thereof | |
JP3257532B2 (en) | Method for manufacturing laminated electronic component and method for measuring characteristics thereof | |
JP2007234749A (en) | Manufacturing method of chip-shape solid electrolytic capacitor | |
JP3041684B2 (en) | Chip resistor and manufacturing method thereof | |
JP3855798B2 (en) | Multilayer ceramic electronic component and manufacturing method thereof | |
JP4605945B2 (en) | Multi-circuit board and method for manufacturing electronic device | |
JPH08241827A (en) | Multilayer electronic part and manufacture thereof | |
JP3257531B2 (en) | Multilayer electronic components | |
JP2003282303A (en) | Chip resistor | |
JP2003272901A (en) | Thick film resistor and its manufacturing method | |
JPH0945830A (en) | Chip electronic component | |
JPH10200257A (en) | Multi-layer circuit board and its manufacture | |
JPH11204313A (en) | Electronic component and manufacture thereof | |
JP3058999B2 (en) | Mejiro wiring board | |
JP2005159083A (en) | Multipiece wiring board | |
JP2005285866A (en) | Multiple wiring board | |
JPH05234702A (en) | Rectangular chip resistor, manufacture thereof, and string of taping parts therefor | |
JP2019125787A (en) | Chip-like metal resistor and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080310 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090310 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090310 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100310 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110310 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110310 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120310 Year of fee payment: 12 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120310 Year of fee payment: 12 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120310 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130310 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130310 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140310 Year of fee payment: 14 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |