JPH11274455A - Solid-state image pick up device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pick up device, which accurately reads out a signal charge from a photodiode even when a voltage is reduced, and also reduces generation of leak current. SOLUTION: A solid-state image pick up device is provided with a read transistor. The react transistor has an (n) type semiconductor layer 2, which is formed on a semiconductor substrate for photoelectric conversion, a (p) type semiconductor layer 3, which is formed to shield the upper surface of the (n) type semiconductor layer 2; and an (n) type semiconductor layer 4, which is formed on the surface of the semiconductor substrate and is connected electrically with the (n) type semiconductor layer 2 for reading a signal charge from the (n) type semiconductor layer 2. The read transistor reads the signal charge from the (n) type semiconductor layer 2 through the (n) type semiconductor layer 4. The (p) type semiconductor layer 3 and the (n) type semiconductor layer 4 are formed at a prescribed interval so as not to bring the depletion layer formed by the (p) type semiconductor layer 3 into contact with the depletion layer formed by the (n) type semiconductor layer 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having an amplifying function.

[0002]

2. Description of the Related Art A conventional CCD type solid-state imaging device requires three power supplies to drive elements. The power consumption of the CCD element is 500 mW. On the other hand, recently, a CMOS type amplification type solid-state imaging device (CM
OS image sensor) has been proposed and is being commercialized. One of the features of this CMOS image sensor is a single power supply, low-voltage driving, and low power consumption (50 mW).

A CMOS image sensor has a large number of pixels similarly to the CCD type, and has a configuration in which a photoelectric conversion element and a transistor are juxtaposed on the same substrate.
The signal charge generated by the photoelectric conversion element modulates the potential of the signal charge accumulating portion, and the potential modulates the amplifying transistor inside the pixel to provide an amplifying function inside the pixel.

Further, the CMOS image sensor is also a CCD.
Similarly to the type, a structure in which the photodiode of the photoelectric conversion unit is embedded in the substrate (embedded photodiode: S
3) is becoming mainstream. CM with such S3 structure
In the OS image sensor, the substrate surface of the photodiode is shielded by a p-type semiconductor layer. Thus, by providing the p-type semiconductor layer for shielding, the current (electrons) generated from the defect level on the substrate surface of the photodiode is obtained.
Can be prevented from flowing into the photodiode, whereby white scratches and unevenness in darkness can be significantly reduced.

In a CMOS image sensor, C
The feature of the element is that it is driven at a lower voltage than the CD type. However, when reading out signal charges from a photodiode that performs photoelectric conversion, a CCD applies a voltage of 10 V to the readout transistor and reads out the signal charge from the photodiode. The signal charge is being read. However, CMOS
In an image sensor, a voltage that can be applied to a read transistor to read a signal from a photodiode is about 3 V. Therefore, there is a problem that the signal charge cannot be read from the photodiode because the voltage that can be applied to the gate of the read transistor is low for reading the signal charge from the photodiode embedded in the substrate.

In order to read out signal charges even when the voltage applied to the readout transistor is low, P (phosphorus) is implanted near the readout transistor and connected to the n-type semiconductor layer forming the photodiode. A reading transistor having a structure in which a second n-type semiconductor layer is formed on the surface of a substrate has been proposed.

[0007]

However, in the above-mentioned photodiode having the conventional S3 structure, the n-type semiconductor layer for reading formed near the gate of the reading transistor and the substrate surface for shielding the photodiode are provided. Since the formed p-type semiconductor layer is close to the formed p-type semiconductor layer, there is a problem that the vicinity of the junction interface between the n-type semiconductor layer and the p-type semiconductor layer becomes a place where a generated current causing white flaws is generated.

The present invention has been made in view of such a problem, and an object of the present invention is to apply a signal charge from the photodiode to the gate of a read transistor in an S3 structure photodiode. Even if the voltage is reduced, the signal charge can be accurately read from the photodiode, and the generation of a leak current due to a current generated near the gate of the read transistor is reduced, so that there is less white flaw and unevenness in darkness. An object of the present invention is to provide a solid-state imaging device.

[0009]

In order to achieve the above object, a solid-state imaging device according to a first aspect of the present invention includes a semiconductor substrate and a first substrate which is formed on the semiconductor substrate and performs photoelectric conversion.
A first conductivity type semiconductor layer; a second conductivity type semiconductor layer opposite to the first conductivity type formed to shield an upper surface of the first first conductivity type semiconductor layer; A second first conductivity type semiconductor formed on the surface of the semiconductor substrate by being electrically connected to the first first conductivity type semiconductor layer in order to read signal charges from the first conductivity type semiconductor layer. A solid-state imaging device, comprising: a read transistor configured to read signal charges from the first first-conductivity-type semiconductor layer via the second first-conductivity-type semiconductor layer. The second conductive type semiconductor layer and the depletion layer formed by the second conductive type semiconductor layer do not come into contact with the depletion layer formed by the second first conductive type semiconductor layer. A second first conductivity type semiconductor layer is formed at a predetermined distance from the semiconductor layer.

Further, a solid-state imaging device according to a second aspect of the present invention comprises:
In the solid-state imaging device according to the first aspect, the readout transistor has a gate electrode formed on a surface of the semiconductor substrate with an insulator interposed therebetween, and the readout transistor includes the second first conductivity type semiconductor layer as the gate. By forming the semiconductor layer before forming the electrode, the second first conductivity type semiconductor layer is covered with the gate electrode.

Further, a solid-state imaging device according to a third aspect of the present invention comprises:
In the solid-state imaging device according to the first invention, at least a portion of the second conductivity type semiconductor is formed in a self-aligned manner with the gate electrode after the formation of the gate electrode. A solid-state imaging device according to a fourth invention is the solid-state imaging device according to the first invention, wherein a second conductivity type well region is formed in the semiconductor substrate.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the configuration of any one cell of a fixed imaging device to which the present invention is applied.
In FIG. 1, first, a voltage is applied to the reset line 14 to turn on the reset transistor 12, and the charge remaining on the wiring is discharged to the drain line 15. Next, the reset transistor 12 is turned off, and a predetermined voltage (here, about 3 V) is applied to the gate of the read transistor 10.
Is turned on by applying. As a result, carriers generated by the photoelectric conversion of the photodiode 2 flow into the amplification transistor 11 side. At this point, when the read transistor 10 is turned off, the charge lost to the escape path is accumulated in the gate of the amplification transistor 11, and the amplification transistor 11 is turned on. When a voltage is applied to the address line 13 to select the lines to be read at the same time and the selection transistor 17 is turned on, a signal is read on the signal line 16.

Hereinafter, a first embodiment of the present invention will be described.
FIG. 2 is a cross-sectional view of a solid-state imaging device including the above-described photodiode 2 and readout transistor 10 in the first embodiment of the present invention. As shown in FIG. 2, in the solid-state imaging device, an n-type semiconductor layer 2 as a photodiode is provided on the surface of a low-concentration p-type semiconductor layer 1 (p-well), and an upper surface of the n-type semiconductor layer 2 is shielded. A p-type semiconductor layer 3 is formed, and is further electrically connected to the n-type semiconductor layer 2 to form an n-type semiconductor layer 4 for reading signal charges from the n-type semiconductor layer 2. . At this time, the p-type semiconductor layer 3 and the n-type semiconductor layer 4 are separated in a pattern so that the depletion layer extending from the p-type semiconductor layer 3 and the n-type semiconductor layer 4 does not contact. further,
An n-type semiconductor layer 7 forming a drain is formed via the silicon oxide film 5, and a gate electrode 6 is formed between the n-type semiconductor layer 4 and the n-type semiconductor layer 7. The above-described p-type semiconductor layer 1, n-type semiconductor layer 2, n-type semiconductor layer 4, gate electrode 6, and n-type semiconductor layer 7 form a read transistor for reading signal charges from n-type semiconductor layer 2. Has formed. As described above, the present embodiment has a structure in which a signal is read from the n-type semiconductor layer 2 via the n-type semiconductor layer 4. As a result, signal charges from the n-type semiconductor layer 2 can be accurately read even when the voltage applied to the gate of the read transistor decreases.

Hereinafter, an example of a method of manufacturing the amplification type solid-state imaging device according to the present embodiment will be described with reference to FIG. here,
A method for manufacturing the read transistor and the photodiode portion, which are features of the present embodiment, will be mainly described.

First, in order to form a p-well (low-concentration p-type semiconductor layer 1) on a semiconductor substrate, for example, B (boron) is implanted at a dose of 3E13 / cm ^-2 by ion implantation. Thereafter, thermal diffusion is performed at about 1200 degrees for several hours to form a p-well. Thereafter, LOCOS is formed for element isolation.

Then, B or P (phosphorus) is ion-implanted in order to determine the threshold value of the read transistor (channel implantation step). Next, a polysilicon film is deposited by an LPCVD method or the like to form a gate electrode of the read transistor, and the resist is patterned into a desired shape. Then, the gate electrode 6 of the read transistor is formed by RIE (reactive ion etching) or the like.

Thereafter, the resist is patterned so that the n-type semiconductor layer 2 for performing photoelectric conversion is opened, and P is set to 2E13 / using an accelerator at an energy of, for example, 400 KeV.
Ions are implanted at a dose of cm ⁻² to form an n-type semiconductor layer 2. Further, the resist is patterned so as to patternally overlap with a part of the n-type semiconductor layer 2, and P (phosphorus) is implanted to form the read n-type semiconductor layer 4 electrically connected to the n-type semiconductor layer 2. Form. Thereafter, in order to shield the substrate surface of the n-type semiconductor layer 2 with the p-type semiconductor layer 3,
Pattern the resist.

At this time, since the n-type semiconductor layer 4 electrically connected to the n-type semiconductor layer 2 exists near the gate electrode 6 of the read transistor, the p-type for shielding the surface of the n-type semiconductor layer 2 is provided. The type semiconductor layer 3 has a pattern having a structure separated from the n-type semiconductor layer 4 by about 0.2 μm or more. The reason for this is to prevent the depletion layer formed by the n-type semiconductor layer 4 formed on the substrate surface from being in contact with the depletion layer formed by the p-type semiconductor layer 3 that shields the surface of the n-type semiconductor layer 2 as described above. It is. When the respective depletion layers come into contact with each other, it becomes a place where a dark current which causes white flaws is generated.

For this reason, as one method, the concentration of the p-type semiconductor layer 1 on which the n-type semiconductor layer 2 is formed is sufficiently increased so that the depletion layers of the p-type semiconductor layer 3 and the n-type semiconductor layer 4 are depleted. Avoid contact with layers. As a specific numerical value, p
When the concentration of the type semiconductor layer 1 is 1E17 / cm ⁻³ , the p-type semiconductor layer 3 (concentration 1E19 / cm ⁻³ ) and the n-type semiconductor layer 4
(Density: 1E17 / cm ⁻³ ), it is necessary to be separated by 0.2 μm or more in pattern.

FIG. 3 is a diagram showing a plane pattern of the solid-state imaging device manufactured by the above-described manufacturing process. As can be seen from FIG. 2, the p-type semiconductor layer 3 and the n-type semiconductor layer 4
It is separated by x (here, 0.2 μm or more) in pattern.

According to the first embodiment described above, the depletion layers extending from the n-type semiconductor layer 4 and the p-type semiconductor layer 3 are structured so as not to contact each other. The current generated at the junction interface of the semiconductor layer 3 can be reduced, thereby obtaining a captured image with low dark current and few white defects.

It should be noted that, in addition to the configuration shown in FIG. 3, a modified example shown in FIGS. 4 (A), 4 (B) and 4 (C) is conceivable. In the configuration of FIG. 4B, the peripheral length of the space between the p-type semiconductor layer 3 and the n-type semiconductor layer 4 is smaller than that of the configuration of FIG. 3, and the configuration of FIG. It is considered that the occurrence probability and the amount of occurrence of become smaller. As a result, a captured image with lower dark current and fewer white defects can be obtained.

Hereinafter, a second embodiment of the present invention will be described.
FIG. 5 shows an n-type semiconductor layer 2 according to a second embodiment of the present invention.
FIG. 2 is a cross-sectional view of a solid-state imaging device including a read transistor and a read transistor. In the second embodiment, in forming a read transistor similar to the first embodiment, after forming an active region (SDG) by a known method, the n-type semiconductor layer 2 and n
An n-type semiconductor layer 4 electrically connected to the type semiconductor layer 2 is formed by implanting P by ion implantation. Thereafter, the gate electrode 6 of the read transistor is formed. As a result, n
Part of the type semiconductor layer 2 and the N type semiconductor layer 4 are covered with the gate electrode 6. At this time, it is preferable that the ion implantation pattern of the n-type semiconductor layer 4 is slightly separated from the end of the gate electrode 6. Thereafter, B is ion-implanted to cover the surface of the n-type semiconductor layer 2 to form the p-type semiconductor layer 3 in a self-aligned manner with respect to the gate electrode 6.

FIG. 6 is a diagram showing a plane pattern of the solid-state imaging device manufactured by the above-described manufacturing process. As can be seen from FIG. 6, the p-type semiconductor layer 3 and the n-type semiconductor layer 4 are separated by x (here, 0.2 μm or more) in pattern.

According to the above-described second embodiment, in addition to the effects of the above-described first embodiment, p
Since the mold semiconductor layer 3 is formed in a self-aligned manner, there is an effect that misalignment is eliminated.

FIGS. 7A and 7B show the above-described second embodiment.
It is a figure showing a modification of an embodiment. In the configuration of FIG. 6, there is a current path over the entire length L of the n-type semiconductor layer 4, so that there is a possibility that a leak current may be generated correspondingly, but in the configuration of FIG. Since the current path exists only in a part of the periphery of No. 4, it is considered that the probability and the amount of generation of the leak current are further reduced. FIG.
In the configuration shown in FIG. 7B, since the current path exists at almost only one point around the n-type semiconductor layer 4, there is an effect that the generation probability and the generation amount of the leakage current are further reduced as compared with FIG.

Although the embodiment of the present invention has been described above, the present invention is not limited to this, and it is a matter of course that various improvements and modifications can be made without departing from the gist of the present invention.

[0028]

According to the present invention, in the photodiode having the S3 structure, even if the voltage applied to the gate of the reading transistor for reading out the signal charge from the photodiode is reduced, the signal charge is accurately read out from the photodiode. In addition, it is possible to provide a solid-state imaging device in which generation of a leakage current due to a current generated in the vicinity of the gate of the readout transistor is reduced and white scratches and unevenness in darkness are reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an arbitrary one cell of a fixed imaging device to which the present invention is applied.

FIG. 2 is a cross-sectional view of a solid-state imaging device including an n-type semiconductor layer 2 and a readout transistor 10 according to the first embodiment of the present invention.

FIG. 3 is a plan pattern diagram of the solid-state imaging device corresponding to the cross-sectional view of FIG. 2;

FIG. 4 is a diagram showing a modification of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of a solid-state imaging device including an n-type semiconductor layer 2 and a readout transistor 10 in a second embodiment of the present invention.

6 is a plan pattern diagram of the solid-state imaging device corresponding to the cross-sectional view of FIG.

FIG. 7 is a diagram showing a modification of the first embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor layer (p-well), 2 ... n-type semiconductor layer (photodiode), 3 ... p-type semiconductor layer (for shielding), 4 ... n-type semiconductor layer (for reading), 5 ... gate oxide film 6 ... Gate electrode 7 ... Drain of readout transistor 10 ... Readout transistor, 11 ... Amplification transistor, 12 ... Reset transistor, 13 ... Address line, 14 ... Reset line, 15 ... Drain line, 16 ... Signal line. 17 ... Selection transistor.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Ikuko Inoue 1st location, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Hiroshi Yamashita Hiroshi Yamashita Toshiba Komukai-shi, Kawasaki-shi, Kanagawa No. 1 in the town Toshiba R & D Center (72) Inventor Hiroshi Naruse No. 1 Komukai Toshiba-cho in Sachi-ku, Kawasaki-shi, Kanagawa Prefecture In-house Tamagawa Plant, Toshiba (72) Inventor Eiki Inokuma Sachi Kawasaki, Kanagawa 1 in Komukai Toshiba-cho, Ward Toshiba Tamagawa Plant (72) Inventor Hideki Shibata 1 in Komukai Toshiba-cho, Kawasaki-shi, Kawasaki, Kanagawa Prefecture In Toshiba Tamagawa Plant (72) Inventor Akira Makabe Kanagawa Prefecture (72) Inventor Seigo Abe, Komukai Toshiba-cho, Kawasaki-shi, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Tamagawa Plant (72) Inventor Eiko Nomachi 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Inside the Toshiba Tamagawa Plant Co., Ltd. Address Co., Ltd.Toshiba Tamagawa Plant (72) Inventor Mikiko Hori 1 Kosaka Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Co., Ltd.

Claims (3)

[Claims] 1. A semiconductor substrate, a first semiconductor layer of a first conductivity type formed on the semiconductor substrate and performing photoelectric conversion, and an upper surface of the semiconductor layer of the first first conductivity type is shielded. A semiconductor layer of a second conductivity type opposite to the first conductivity type formed in order to read signal charges from the semiconductor layer of the first first conductivity type; and a semiconductor layer of the first first conductivity type. And a second first conductivity type semiconductor layer formed on the surface of the semiconductor substrate by being electrically connected to the first first conductivity type semiconductor layer via the second first conductivity type semiconductor layer. A solid-state imaging device including a read transistor configured to read a signal charge from a semiconductor layer of one conductivity type, comprising: a depletion layer formed by the semiconductor layer of the second conductivity type; The half of the second conductivity type is used so that the depletion layer formed by the semiconductor layer does not come into contact with the semiconductor layer. A solid-state imaging apparatus characterized by the material layer and the semiconductor layer of the second first conductivity type is formed apart by a predetermined distance. 2. The read transistor has a gate electrode formed on a surface of the semiconductor substrate with an insulator interposed therebetween, and the second first conductive type semiconductor layer is formed before forming the gate electrode. The solid-state imaging device according to claim 1, wherein the semiconductor layer of the second first conductivity type is covered with the gate electrode by being formed. 3. The solid-state imaging device according to claim 2, wherein at least a part of the second conductivity type semiconductor is formed in a self-aligned manner with the gate electrode after the formation of the gate electrode. .