JPH11261408A - Phase interpolator, timing signal generating circuit, and semiconductor integrated circuit device and semiconductor integrated circuit system adopting the timing signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a timing signal with high accuracy synchronously with a reference clock and having a prescribed phase difference from a phase of the reference clock by providing a master circuit that generates with a same period or a same phase as an input reference signal through feedback control and a slave circuit that receives the internal signal and generates a signal in a prescribed timing. SOLUTION: A control signal CS outputted from a control signal generating circuit 13 in a master circuit 1 controls plural slave circuits 2. That is, each slave circuit 2 uses the control signal CS which is used to control a delay amount of a variable delay line 11 in a DLL circuit 10 in the master circuit l. Thus, even each slave circuit 2 can generate a timing a signal TS with a delay amount based on a reference of a period of a reference clock CKr. Furthermore, since the master circuit 1 and each slave circuit 2 use the control signal CS, a response frequency of each slave circuit 2 is controlled in response to a frequency of the reference clock CKr. Moreover, the timing signal TS with high accuracy and a wide frequency range is generated by changing a response speed of each slave circuit 2 in response to the frequency of the reference clock CKr.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a phase interpolator, a timing signal generating circuit, and a semiconductor integrated circuit device and a semiconductor integrated circuit system to which the timing signal generating circuit is applied, and more particularly, to signal transmission between LSI chips. Alternatively, the present invention relates to a timing signal generation circuit for speeding up signal transmission between a plurality of elements and circuit blocks in one chip.

Recently, LSI (Large Scale Integration)
Circuit) signal transmission between chips, for example, DRAM (Dyna
mic Random Access Memory) and processor (logic circuit)
, Or high-speed signal transmission between a plurality of elements or circuit blocks in one LSI chip (semiconductor integrated circuit device). There is a demand for a timing signal generation circuit that can generate a plurality of timing signals having a predetermined phase difference in synchronization with a reference clock with a simple configuration and with high accuracy.

[0003]

2. Description of the Related Art In recent years, the performance of components constituting computers and other information processing equipment has greatly improved.
AM and processor performance has greatly improved over time. That is, the processor has remarkably improved performance in terms of high-speed speed, while the DRAM has remarkably improved performance mainly in terms of capacity increase. However, D
The improvement in operating speed in RAM is not as great as the increase in capacity, and as a result, the speed gap between the DRAM and the processor has increased, and in recent years this speed gap has been hindering the improvement in computer performance. In addition to the signal transmission between these chips, the signal transmission speed between elements and constituent circuits (circuit blocks) in one LSI chip (semiconductor integrated circuit device) with the increase in the size of the chip has also increased. It has become a major factor limiting performance.

[0004] For example, in order to speed up signal transmission between LSI chips, it is necessary for a circuit for receiving a signal to operate at an accurate timing with respect to the signal. Locked Loop) and PLL (P
hase Locked Loop). FIG.
FIG. 1 is a block diagram showing an example of a conventional timing signal generation circuit, and shows an example of a timing signal generation circuit using a DLL circuit. In FIG. 1, reference numeral 10
0 denotes a DLL circuit, 111 denotes a variable delay line, 112 denotes a phase comparison circuit, 113 denotes a control signal generation circuit, 114 denotes a drive circuit (clock driver), 102 denotes a delay circuit, and 103 denotes a reception circuit.

The DLL circuit 100 includes a variable delay line 11
1, phase comparison circuit 112 and control signal generation circuit 1
13 is provided. The phase comparison circuit 112 includes a reference clock CKr and a clock driver 114.
(Internal clock CKin) is input, and the delay amount of the variable delay line 111 (the number of stages of the delay unit D) is controlled such that the phase difference between these clocks CKr and CKin is as small as possible. That is, the phase comparison circuit 11
2 supplies an up signal UP or a down signal DN to the control signal generating circuit 113 in accordance with the phase difference between the reference clock CKr and the internal clock CKin, and the control signal generating circuit 113 supplies the up signal UP or the down signal DN to the control signal generating circuit 113. The delay amount of the variable delay line 111 is controlled by a corresponding control signal (a signal for selecting the number of stages of the delay unit D) CS. Thus, the internal clock CKin synchronized with the reference clock CKr is generated.

The output of the clock driver 114 is an LSI
It is supplied as an internal clock CKin of a chip (semiconductor integrated circuit device), for example, a delay circuit (an appropriate delay stage)
The signal is used as a timing signal TS of the receiving circuit 103 via 102. That is, for example, the receiving circuit 103
Is the internal clock C supplied through the delay circuit 102
The signal SS given in accordance with Kin is taken (latched). Here, the delay circuit 102 includes, for example,
It is provided to generate a timing signal TS by adjusting the timing of the internal clock CKin that is delayed according to the drive capability of the clock driver 114, the load capacity of the signal line, and the like.

[0007]

The above-described timing signal generating circuit using the conventional DLL circuit shown in FIG. 1 or a timing signal generating circuit having a similar configuration in which the DLL circuit is replaced with a PLL circuit is a reference signal. Clock CK
r, the internal clock CKin having the same phase as that of the internal clock CKin
When used for high-speed signal transmission between chips, there is a problem to be solved.

First, in signal transmission between LSI chips (or between electronic devices), multi-bit transmission using a plurality of signal lines is often applied in order to obtain a necessary signal transmission band. Then, the optimum reception timing for each bit differs due to the variation in the delay characteristics of the respective signal lines. Therefore, for example, a plurality of DLL circuits are provided to adjust the timing of each bit, but in this case, there is a problem that the circuit scale becomes too large.

[0009] Even in the transmission of one bit width, the optimum receiving timing of the receiving circuit is usually different from the rising or falling of the reference clock CKr. To generate a clock for reception. However, even if the internal clock CKin which does not depend on the variation of the element characteristics is created by using the DLL circuit or the PLL circuit, a delay irrelevant to the cycle of the reference clock CKr occurs in the delay stage. When a change occurs in the clock frequency, there is a problem that reception at an optimal timing cannot be performed.

In view of the above-mentioned problems of the conventional timing signal generation circuit, the present invention is to generate a plurality of timing signals having a predetermined phase difference in synchronization with a reference clock with a simple configuration and with high accuracy. It is an object of the present invention to provide a timing signal generating circuit capable of performing the following.

[0011]

According to the present invention, a parent circuit for generating an internal signal having the same cycle or phase as an input reference signal by feedback control, an internal signal from the parent circuit and a control signal And a slave circuit for receiving a signal and generating a timing signal having a predetermined timing with respect to the reference signal.

According to the timing signal generating circuit of the present invention, the child circuit receives the internal signal and the control signal from the parent circuit and outputs a timing signal having a predetermined timing with respect to the reference signal. Here, a plurality of child circuits can be provided for one parent circuit. Further, the timing signal generation circuit is a single semiconductor integrated circuit device (LS
The present invention can be applied to a semiconductor integrated circuit system including a plurality of semiconductor integrated circuit devices.

Thus, a plurality of timing signals having a predetermined phase difference in synchronization with the reference signal can be generated with a simple configuration and with high accuracy.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle configuration of a timing signal generating circuit according to the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the principle configuration of the timing signal generation circuit according to the present invention. 2, reference numeral 1 denotes a parent circuit, 2 denotes a child circuit, 10 denotes a DLL circuit, 11 denotes a variable delay line, 12 denotes a phase comparison circuit, 13 denotes a control signal generation circuit, and 14 denotes a driving circuit (clock driver). Is shown.

As shown in FIG. 2, the timing signal generating circuit according to the present invention comprises a parent circuit 1 and a plurality of child circuits 2. The parent circuit 1 has the same configuration as the conventional timing signal generation circuit 111 shown in FIG.
The circuit includes a circuit 10 and a clock driver 14. Note that the parent circuit 1 is not limited to a circuit using a DLL circuit, but may be a circuit to which a PLL circuit is applied, for example.

The DLL circuit 10 includes a variable delay line 11,
A phase comparison circuit 12 and a control signal generation circuit 13 are provided. The phase comparison circuit 12 has a reference clock CKr
And the output of clock driver 14 (internal clock CK
in) is input and these clocks CKr and CKin
Are compared. Further, the control signal generation circuit 13
Generates a control signal (for example, an analog voltage or current) CS based on the result of the phase comparison. The delay amount of the variable delay line 11 is controlled by the control signal CS from the control signal generating circuit 13, and finally, the phase difference between the reference clock CKr and the internal clock CKin is minimized. Here, the output (CKin) of the clock driver 14 is not only fed back to the phase comparison circuit 12 but also supplied to each slave circuit 2, and the control signal CS from the control signal generation circuit 13 is also sent to each slave circuit 2. Is supplied to

As shown in FIG. 2, in the timing signal generation circuit of the present invention, the control of the plurality of child circuits 2 is also controlled by the control signal (output signal of the control signal generation circuit 13) CS used in the parent circuit 1. Is being done. That is, in each child circuit 2, the control signal CS used to control the delay amount of the variable delay line 11 in the DLL circuit 10 of the parent circuit 1 is used as it is, and the delay element ( By using essentially the same delay element as the delay unit D), a delay proportional to the period of the reference clock CKr can be provided.

Therefore, the slave circuit 2 also has a delay amount based on the period of the reference clock CKr (ie,
A timing signal (TS) (having a fixed phase difference relationship with respect to the reference clock) can be generated. Further, by using the control signal CS generated in the parent circuit 1 also in the child circuit 2, it is possible to control the response frequency characteristic of the child circuit 2 according to the frequency of the reference clock CKr. Specifically, for example, it becomes possible to make the characteristic frequency (for example, cutoff frequency) of the filter circuit used in the slave circuit 2 proportional to the frequency of the reference clock CKr. By utilizing this fact, for example, it is possible to generate a sine wave having a constant amplitude in the slave circuit 2 by passing a rectangular wave clock having a CMOS amplitude through a filter.

As described above, according to the timing signal generating circuit of the present invention, the timing signal synchronized with the reference clock CKr can be generated by the child circuit 2 having a configuration much simpler than that of the parent circuit 1. Also, the reference clock CK
By changing the response speed of the slave circuit 2 in accordance with the frequency r, it is possible to generate the timing signal TS with high accuracy over a wide frequency range.

Referring to the accompanying drawings, embodiments of a phase interpolator, a timing signal generating circuit, a semiconductor integrated circuit device to which the timing signal generating circuit is applied, and a semiconductor integrated circuit system according to the present invention will be described below. explain. FIG. 3 is a block diagram showing a configuration of the timing signal generation circuit according to the first embodiment of the present invention.

As shown in FIG. 3, the variable delay line 1
1 is composed of a plurality of delay units D and a control signal C
By selecting a predetermined number of delay units D of the variable delay line 11 in S, the amount of delay in the variable delay line 11 is controlled. The control signal generating circuit 13 includes a charge pump circuit 131 and a buffer amplifier 132, and outputs an up signal UP or a down signal DN from the phase comparison circuit 12 which is output in accordance with a phase difference between the reference clock CKr and the internal clock CKin.
Is generated in accordance with the control signal CS.

Further, as shown in FIG.
Has a variable delay line 21 provided with a plurality of delay units D which are the same as the delay units constituting the variable delay line 11 of the parent circuit 1, and the variable delay line 21 of the child circuit 2 The internal clock CKin which is the output of the first clock driver 14 is input. The slave circuit 2 is used, for example, to generate a timing signal (TS) having a predetermined delay with respect to a clock cycle.

The delay amount of the variable delay line 21 of the slave circuit 2 (the number of stages of the delay unit D) is controlled by a control signal CS which is an output of the control signal generation circuit 13 (buffer amplifier 132) of the parent circuit 1. Has become. As described above, the same delay unit D as that of the variable delay line 11 of the parent circuit 1 is used for the child circuit 2, and the reference clock CK
A plurality of timing signals (TS1, TS2,...) having a delay amount proportional to the period of r can be generated. These timing signals TS1, TS
Have a predetermined delay amount with respect to the reference clock CKr, for example, 1 to the reference clock CKr.
/ M, 2 / m,... Are signals delayed by the period. A plurality of child circuits 2 can be provided for one parent circuit 1. The variable delay line 21 of each child circuit 2 has a smaller circuit size than the variable delay line 11 of the parent circuit 1, for example. That is, the number of stages of the delay unit D can be reduced.

In the above, the parent circuit 1 and the plurality of child circuits 2 can be provided in one semiconductor integrated circuit device (LSI chip). However, the parent circuit 1 and each of the child circuits 2 are different from each other. May be provided. That is, the timing signal generation circuit can be applied to a semiconductor integrated circuit system having a plurality of semiconductor integrated circuit devices.

FIG. 4 is a circuit diagram showing an example of the delay unit D in the variable delay line of the timing signal generation circuit of FIG. Here, the circuit example of the delay unit D shown in FIG. 4 is common to the delay unit in the variable delay line 11 of the parent circuit 1 and the delay unit in the variable delay line 21 of the child circuit 2. As shown in FIG. 4, each delay unit D includes a p-channel type M provided between a high-potential power line (Vcc) and a low-potential power line (Vss).
OS (pMOS) transistor and n-channel type MO
The CMOS inverter DI includes an S (nMOS) transistor, an nMOS transistor DT provided between the output of the CMOS inverter DI and a low potential power supply line (Vss), and a capacitor DC. The variable delay line 11 (21) is provided with a plurality of delay units D
Are connected in tandem. FIG.
The delay unit D shown in (1) applies a control voltage Vcs (control signal CS) to the gate of the transistor DT. However, the present invention is not limited to this, and various delay units can be used. For example, a transistor (pMO) of a CMOS inverter DI as shown in FIG.
It is also possible to insert transistors operating in the constant current mode on the source side of S and nMOS, respectively, and control the delay by control voltages Vcn and Vcp to these transistors. In order to avoid inversion of logic, 2
One delay unit D may be configured as one unit (one stage).

FIG. 5 is a block circuit diagram showing an example of the phase comparator 12 in the timing signal generator of FIG. 3, and FIG. 6 is a timing chart for explaining the operation of the phase comparator of FIG. As shown in FIG. 5, the phase comparison circuit 12 includes a reference clock CKr and an internal clock CKin.
And outputs an up signal (/ UP) or a down signal (/ DN) according to the phase difference between these signals. The reference clock CKr and the internal clock C
The frequency of Kin is divided by 2 and the logic of the reference clock CKr 'and the internal clock CKin' having twice the period is taken to obtain a negative logic up signal (/ UP) and down signal (/
DN).

That is, as shown in FIG. 6, the timing at which the internal clock CKin 'divided by 2 changes from the low level "L" to the high level "H" occurs when the reference clock CKr' divided by 2 has the low level. If it is earlier than the timing of changing from "L" to high level "H", a low level "L" up signal / UP is output, while the reference clock CKr 'divided by 2 is changed from low level "L" to high level. If it is later than the timing of changing to the level "H", a low level "L" down signal / DN is output.

FIG. 7 is a circuit diagram showing an example of the charge pump circuit 131 in the timing signal generation circuit of FIG. As shown in FIG. 7, the charge pump circuit 131
Are the high potential power line (Vcc) and the low potential power line (Vss)
Provided between the up signal (up signal of inverted logic)
It is composed of a pMOS transistor whose gate is supplied with / UP and an nMOS transistor whose gate is supplied with a down signal DN. That is, when the low level "L" up signal / UP is being output, the potential of the output level Vco becomes high, while the high level "H" is output.
When the down signal DN (/ DN is low level "L") is output, the potential of the output level Vco is lowered.

The output Vco of the charge pump circuit 131
Becomes a control voltage Vcs (control signal CS) via the buffer amplifier 132, and is applied to the gate of the transistor DT of each delay unit D in FIG. When the potential of the control voltage Vcs increases, the load capacitance at the output of each CMOS inverter DI increases, the delay amount of the variable delay line 11 (21) increases, and the internal clock C
The phase of Kin is delayed. Conversely, when the potential of the control voltage Vcs decreases, the load capacitance at the output of each CMOS inverter DI decreases, the delay amount of the variable delay line 11 (21) decreases, and the phase of the internal clock CKin advances. Become.

FIG. 8 is a circuit diagram showing another example of the delay unit D in the variable delay line of the timing signal generating circuit of FIG. As shown in FIG. 8, the delay unit D
Is the transistor (pMOS) of the CMOS inverter DI
And a transistor operating in the constant current mode is inserted on the source side of the nMOS and the nMOS, and the delay is controlled by the control voltages Vcn and Vcp applied to this transistor. That is, a pMOS transistor DTp is provided between the high-potential power supply line (Vcc) and the source of the pMOS transistor of the CMOS inverter DI.
An nMOS transistor DTn is provided between the source of the nMOS transistor of the MOS inverter DI. Then, while applying the control voltage Vcp to the gate of the transistor DTp, the transistor DTn
The control voltage Vcn is applied to the gates of the gates. The delay unit D shown in FIG. 8 has an advantage that a variable range of the delay amount by one delay unit is wide. Note that, as described above, the two delay units D may be configured as one unit (one stage) in order to avoid logic inversion.

FIG. 9 is a block circuit diagram showing a configuration of a control signal generation circuit 13 in a timing signal generation circuit according to a second embodiment of the present invention. FIG. Current-voltage conversion circuit 13
FIG. 3 is a circuit diagram showing an example of No. 3; As shown in FIG.
The control signal generation circuit 13 includes a charge pump circuit 131 and a plurality of pMOS transistors 1321 and 1322 connected in a current mirror. Each p
The sources of the MOS transistors 1321 and 1322 are connected to a high potential power supply line (Vcc), and the gates are supplied with the output of the charge pump circuit 131, respectively.
These pMOS transistors 1321, 132
The control signal CS supplied to the parent circuit 1 and the child circuit 2 is output from the drain of the second circuit 2. That is, in the second embodiment, the current signal is used for delivering the control signal CS to the parent circuit 1 and the child circuit 2. Here, the pMOS transistor 1322 for the child circuit
May be provided, for example, in accordance with the number of child circuits 2.

Then, as shown in FIG. 10, in the parent circuit 1 and each child circuit 2, the control signal generation circuit 13
The control signal (current signal) CS from the (pMOS transistors 1321 and 1322) is converted into control voltages Vcn and Vcp by the current-voltage conversion circuit 133. The control voltages Vcn and Vcp are, for example,
This is applied to the gates of the transistors DTp and DTn of the delay unit shown in FIG. In order to control the delay unit shown in FIG. 4, the control voltage Vcn is used as the control voltage Vcs. Here, the current-voltage conversion circuit 133 includes the nMOS transistor 13
31 and 1333 and a pMOS transistor 1332, but the invention is not limited to this. The above-described second embodiment distributes the control signal CS by a current signal, so that, for example, the variation in the threshold value of the transistor caused by the parent circuit 1 and the child circuit 2 being separated far from each other in the chip can be prevented. There is an advantage that transmission of the control signal CS is not hindered.

FIG. 11 is a block diagram showing a main part of a timing signal generating circuit according to a third embodiment of the present invention. FIG. 12 shows a digital-analog conversion (D / A FIG. 2 is a block circuit diagram illustrating an example of a D / A converter that performs conversion. As is clear from the comparison between FIG. 11 and FIG. 3, in the third embodiment,
An up / down counter 134 is used in place of the charge pump circuit 131 in the first embodiment. That is, the up / down counter 134 outputs the up signal UP and the down signal DN from the phase comparison circuit 12.
, For example, a 6-bit count signal b0
b5 is supplied to a D / A converter 135 shown in FIG.

The D / A converter 135 is a current matrix cell type D / A converter. For example, the D / A converter 135 converts a 6-bit count signal b0 to b5 output from the up / down counter 134 into an analog signal and outputs a control signal CS. It is supposed to. FIG. 13 shows one current matrix cell (U) in the D / A converter 135 shown in FIG.
FIG. 3 is a circuit diagram showing a configuration example of the present invention.

As shown in FIG. 13, one current matrix cell U includes an AND gate UA, an OR gate UO,
And two nMOS transistors UT1 and UT2. The cells U are arranged in a matrix to form a current matrix section 1350, and count signals (b2, b
3; b4, b5) to each current matrix cell U. Note that the upper count signals b0, b
Reference numeral 1 denotes two nMOS transistors (13) provided in series between the output terminal and the low potential power supply line (Vss).
53, 1354; 1355, 1356) to the gate of one transistor (1353, 1355). Note that the other transistor (1
The control voltage Vc is applied to the gates (354, 1356). The control voltage Vc is
The voltage is also applied to the gate of the transistor UT2 in each current matrix cell U.

The third embodiment shown in FIGS.
Up / down counter 134 and D / A converter 1
By using the combinations of 35, the loop filter can be easily designed, and the delay amount can be kept constant even when the phase comparison operation of the loop to which the DLL circuit is applied is completely stopped. There is an advantage that can be made.

FIG. 14 is a block diagram showing a configuration of a timing signal generating circuit applied to a child circuit according to a fourth embodiment of the present invention. FIG. 15 is a circuit diagram showing an example of the phase interpolator 136 of FIG. It is. As shown in FIG. 14, in the fourth embodiment, an input clock (in2) and a signal (in1) delayed by one delay stage therefrom are passed through a phase interpolator (phase interpolator) 136. , The timing signal TS in the slave circuit 2 is generated.

As shown in FIG. 15, the phase interpolator 136 includes two sets of differential amplifier stages 1361 and 1362.
Input transistor pair bias current (Tail Current)
, The two inputs (in1, in2) are weighted and added, and two sets of differential amplification stages 1
By passing signals S1 and S2 from 361 and 1362 through comparator 1363, these two signals S1 and S2
An intermediate phase output (timing signal TS) between the two phases is obtained. Here, the weighting of the inputs in1 and in2 in each of the differential amplifier stages 1361 and 1362 is performed, for example, by using the control codes (C01, C02, ..., C0n; C1
, C12,..., C1n) and applying a control voltage (Vcs) to the gate of the other transistor (1365). The advantage of using such a phase interpolator 136 is that the output signal (timing signal T) has a finer resolution than the delay unit for one stage.
Since the timing of S) can be adjusted, the timing can be adjusted with high accuracy.

FIG. 16 is a circuit diagram showing another example of the phase interpolator 136 as the fifth embodiment of the present invention.
The phase interpolator 136 shown in FIG. 16 includes two voltage-current conversion circuits 136a and 136b,
Each voltage-current conversion circuit includes pMOS transistors 61 and 63 and nMOS transistors 62 and 64, respectively. Then, the voltage-current conversion circuits 136a and 136b convert the voltage inputs in1 and in2 into voltage-current, respectively, and output them. here,
Output transistor of voltage-current conversion circuit (65, 66)
Is controlled by the switch means 67 by an external signal, and as a result, the conversion coefficient of the voltage-current conversion changes.
The converted current is summed, and the result is input to a comparator to obtain a timing signal (TS).

FIG. 17 shows a simulation of the fifth embodiment of the present invention.
Timing signal generation circuit used to perform the
FIG. 9 is a circuit diagram showing a configuration of (phase interpolator 136).
FIG. 18 is a schematic diagram of the timing signal generation circuit shown in FIG.
Results (SPICE simulation results)
FIG. As shown in FIG.
The separator 136 receives the input signal (voltage signal) in1 and
And current conversion of voltage and current respectively
The circuit includes circuits 136a and 136b. What
The input of each voltage-current conversion circuit 136a and 136b
The delay unit D (used for the variable delay line 11)
Same delay unit: see FIG. 4 or FIG. 8)
And gradually change the input signals in1 and in2.
The signals in1 * and in2 * thus obtained are each expressed by a voltage-current
Supply to the conversion circuits 136a and 136b.
ing. Note that reference numeral W in FIG.₀~ W₇(/ W
₀~ / W₇) Indicates a transfer gate (switch means) 6
7 is an external signal for controlling the switching of
Part signal W₀~ W ₇(/ W₀~ / W₇) By transferage
The gate 67 is opened and closed, and the voltage-current conversion circuit 136a (1
36b) The number of output transistors (65, 66) is controlled.
Control. Thereby, as shown in FIG.
To change the timing of the output (Out)
Can be. That is, the current-voltage conversion circuit 136a,
136b, the two input signals i
By changing the weights of n1 and in2, the phase interpolator
136 is realized. Fifth implementation
The example phase interpolator is a fourth embodiment shown in FIG.
Because the current mirror differential amplifier stage is not used,
There is an advantage that further low voltage operation becomes possible.

FIG. 19 is a block diagram showing a configuration of a timing signal generating circuit according to a sixth embodiment of the present invention. As shown in FIG. 19, in the sixth embodiment, a DLL circuit is configured by a parent circuit 1 and a child circuit 2, and a coarse delay control unit for performing coarse delay control on the parent circuit 1 and a fine delay circuit are provided. A fine delay control unit for performing delay control is provided, and a circuit corresponding to the fine delay control unit of the parent circuit 1 is provided for the child circuit 2.

The coarse delay control section in the parent circuit 1 comprises the delay line 11, the phase comparison circuit 12a, the up / down counter 134a, the D / A converter 135, and the selector 15. The unit includes a phase interpolator 136 and, for example, two delay units D that delay the output of the coarse delay control unit (selector 15) by one stage and two stages and supply the delayed output to the phase interpolator 136. It is configured. Here, the reference clock C is applied to the phase comparison circuit 12a.
Kr and, for example, the output of the last stage of the delay line 11 composed of m stages of delay units D are input, and the output (current control signal) of the D / A converter 135 is supplied to the delay line 11. Then, a signal having a timing whose phase is equally divided according to the number of stages of the delay unit D from the delay line 11 is output to the selector 15. The selector 15 and the phase interpolator 136 include a phase comparison circuit 12b and an up / down counter 1
The control signal generated at 34b is supplied. That is, the coarse delay control unit takes out taps from the delay line 11 having a plurality of delay units, selects an output of each tap by the selector (selection unit) 15, and supplies the output signal to each fine delay control unit. It has become.

As shown in FIG. 19, each child circuit 2 includes a phase interpolator 236 and a coarse delay control unit (selector 15) of the parent circuit 1 in the same manner as the fine delay control unit of the parent circuit 1. Are provided with two delay units D each of which delays the output by one stage and two stages and supplies the delayed output to the phase interpolator 236. The configuration of the delay unit D in the fine delay control section can be changed variously.

As shown in FIG. 19, in the sixth embodiment, the coarse delay control unit of the parent circuit 1 and the fine delay control unit (the fine delay control unit of the parent circuit 1 or each child circuit 2) are connected in series. And a DLL loop is constituted by the coarse delay control unit itself.
Further, the fine delay control unit using the phase interpolator (136, 236) can obtain a delay with higher resolution than the delay stage (one delay unit D) of the parent circuit 1. Here, the delay unit used for the phase interpolator (136, 236) of the fine delay control unit is the same as the delay unit D in the delay line 11 of the coarse delay control unit. Note that the output (current control signal) of the D / A converter 135 is also supplied to each slave circuit 2.

As described above, according to the sixth embodiment, a delay having a higher resolution than the resolution of the delay line 11 can be set by a digital signal, and a highly accurate DLL signal can be obtained. Further, it is possible to realize a digitally controlled DLL circuit capable of stopping the phase comparison operation for a long time or returning from the sleep mode in a short time. Moreover, by arranging a plurality of fine delay control units (phase interpolators 236) as the sub-circuits 2, there is an advantage that a plurality of timing signals having a delay with a higher resolution than the resolution of the delay line 11 can be generated. .

FIG. 20 is a block diagram showing a configuration of a timing signal generating circuit according to a seventh embodiment of the present invention. In the seventh embodiment, not only the control signal CS (output of the control signal generation circuit 13) but also the three-phase internal clocks CK1 to CK3 (delay line 1
1 for each delay output). In the slave circuit 2, the phase interpolator 2 is controlled based on the three-phase clocks CK1 to CK3 supplied from the master circuit 1.
36 generates a timing signal (output clock) of an arbitrary phase.

That is, as shown in FIG. 20, in the slave circuit 2, for example, the three-phase clocks CK1 to CK3 are supplied to the switch unit 238 via the delay unit D for making the signal change gradual. A predetermined combination of three-phase clocks is selected by the switch unit 238 and supplied to the inputs of the operational amplifiers 237a and 237b. Then, each output of the operational amplifiers 237a and 237b is received and phase-divided, and a predetermined timing signal is output. The seventh embodiment has an advantage that the slave circuit 2 can generate a timing signal (output clock) having an arbitrary phase within 360 degrees.

FIG. 21 is a circuit diagram showing a configuration of a sine wave generating circuit according to an eighth embodiment of the present invention. In recent years, attention has been paid to using a sine wave as a clock waveform in order to reduce power consumption of a clock driver and to reduce clock noise by eliminating harmonic components. Note that the reason why the power consumption of the clock driver can be reduced when a sine wave clock is used is that it is not necessary to make the output waveform rise and fall steeply (slowly). This is because the transistor can be composed of a small one with small driving capability (a transistor with low power consumption). FIG. 21 shows an example of a sine-wave clock generation circuit applied to the slave circuit 2, for example.

As shown in FIG. 21, for example, FIG.
By passing the voltages (control voltages) Vcn and Vcp obtained by the current-voltage conversion circuit 133 shown in FIG. 8 through the delay unit D shown in FIG.
The S clock (rectangular wave) is converted into a triangular wave, and the triangular wave is converted into a constant current driver C having nonlinear input / output characteristics.
By passing through D, it is converted into a sine wave (pseudo sine wave). Here, a delay unit D operated by a control signal (CS) from the parent circuit 1 is used for a portion for generating a triangular wave, and the delay of the delay unit D is determined by the period of the reference clock (CKr). Since it is proportional, the amplitude of the triangular wave is kept constant even if the frequency of the reference clock changes. Therefore, the eighth embodiment has an advantage that a sine wave can be generated over a wide frequency range.

FIG. 22 is a diagram showing a simulation result (SPICE simulation result) of the sine wave generation circuit of FIG. 21. FIG. 22A shows a case where the input signal (clock) is 40 MHz, and FIG. Indicates that the input signal is 1
FIG. 22 (c) shows the case where the input signal is 400 MHz. Note that a simulation was performed by providing a resistor R having a resistance value that is half the characteristic impedance of the transmission line, for example, as the output of the sine wave generation circuit.

As is clear from FIGS. 22A to 22C, the sine wave generating circuit shown in FIG.
It can be seen that the input rectangular wave is converted into a substantially sinusoidal wave and output when the input rectangular wave is output. FIG.
FIG. 19 is a block diagram showing a configuration of a timing signal generation circuit as a ninth embodiment of the present invention, showing an example of a timing signal generation circuit to which a PLL circuit is applied.

In FIG. 23, reference numeral 12 is a phase comparison circuit, 134 is an up / down counter, and 135 is D / A.
Converter and 21 is a variable voltage oscillator (VCO)
Is shown. Here, the variable voltage oscillator 21 is composed of, for example, a ring oscillator in which circuits similar to those of the delay unit D shown in FIG. Control voltages Vcp and Vcn, which are outputs of the signal generation circuit (current-voltage conversion circuit 133), are applied, and thereby the oscillation frequency is controlled. Each slave circuit 2 includes a current-voltage conversion circuit 133 and a variable voltage oscillator 21.

As described above, in the ninth embodiment, the parent circuit 1
Uses a PLL circuit instead of a DLL circuit.
An output signal (timing signal) can be generated even when a completely periodic clock signal cannot be obtained. That is, for example, even when jitter is included in the input reference clock CKr, the jitter component can be removed by the variable voltage oscillator (ring oscillator) 21 or the like. It is preferred.

FIG. 24 is a block diagram showing a configuration of a timing signal generating circuit according to a tenth embodiment of the present invention.
In the tenth embodiment, the parent circuit 1 is a circuit to which a DLL circuit that outputs an internal clock (CKin) locked to a reference clock (CKr) is applied, and the child circuits 2a to 2
z is provided according to each bit of the multi-bit receiving circuits 3a to 3z. Here, the parent circuit 1 is shown in FIG.
Are not limited to those shown in FIG.

As shown in FIG. 24, each of the slave circuits 2a to 2a
2z (2a) is a selector (15), a delay line (11), a delay unit (D), and a selector 211, a delay line 215, and two delay units D corresponding to the phase interpolator (136) in FIG. , And a phase interpolator 236, and supplies timing signals TSa to TSz to the corresponding receiving circuits 3a to 3z, respectively, to determine the timing at which the receiving circuits 3a to 3z take in the signals SSa to SSz. Control.

In the tenth embodiment, each child circuit 2a
2 to 2z, the levels of the signals SSa to SSz in the corresponding receiving circuits 3a to 3z are sequentially detected, and the delay amount is controlled so that the capturing timing is optimized. That is, the signal (SSa) from the receiving circuit (for example, 3a) is sequentially switched by the switch means 210 and supplied to the A / D converter 220 that performs analog-to-digital conversion (A / D conversion), and the level thereof is maximized. (To increase the S / N ratio)
The selection by the selector 215 (the delay amount by the delay line 211) is controlled via the control circuit 230. Here, in each receiving circuit (3a), for example, when the signal SSa is fetched at the optimal timing TSa, the level of the signal SSa becomes maximum.
In the tenth embodiment, the timing signal T
The timing of Sa is defined.

That is, in the tenth embodiment, the amount of delay by the delay line 211 is controlled by, for example, a 6-bit digital signal, and the digital signal is adjusted so that the signal strength in each of the receiving circuits 3a to 3z becomes maximum. Control each. Then, the work of optimizing the signal strength is configured to be performed while a special signal (for example, a series such as “1010...”) For that purpose is being sent. According to the tenth embodiment, there is an advantage that the operation timing of the receiving circuit including the signal line delay between each bit can be optimized even in the case of multi-bit parallel signal transmission.

FIG. 25 is a block diagram showing a main configuration of a timing signal generating circuit according to an eleventh embodiment of the present invention. In the eleventh embodiment, similarly to the above-described tenth embodiment, the multi-bit reception timing is optimized for each bit. Is caused to occur. Here, as in the tenth embodiment, the sub-circuits 2 (2a to 2z) are multi-bit receiving circuits 3 (3a to 3z).
z) is provided for each bit. As shown in FIG. 25, each child circuit 2 is provided with a fine delay control unit using a phase interpolator 236. The input sampling timing (CL1, CL2) is controlled by the digital signal of (1).

In FIG. 25, reference numeral 212 is a combinational logic circuit, 234 is an up-down counter,
Reference numerals 241 and 242 denote reception latch circuits. The phase interpolator 236 includes a parent circuit 1
Output (φ1, / φ1, φ1) of the four-phase PLL circuit (250)
2, / φ2) are supplied, and the control clocks CL1 and C
By outputting L2, the sampling timing of each of the latch circuits 241 and 242 is controlled. here,
The latch circuits 241 and 242 each include two D-type flip-flops (D-FFs). The sampling of the two flip-flops in the latch circuit 241 is controlled by the control clock CL1. The sampling of the flip-flop is controlled by control clocks CL1 and CL2, respectively.

That is, each child circuit 2 of the eleventh embodiment is
In (2a to 2z), two reception latch circuits 241 and 242 are provided for one bit, and one latch circuit 241 receives an input at the center of a data reception window (also referred to as a bit cell). The sampling is performed, and the other latch circuit 242 samples the boundary between two adjacent bit cells.
Therefore, these two latch circuits 241 and 242
Is the control clock CL1 which is 180 degrees out of phase
And CL2, the input signal is sampled at twice the normal sampling rate. By using such two latch circuits 241, 242, when data transition from "0" to "1" or "1" to "0" occurs between adjacent bit cells, the sampling timing (control clock CL1
And the timing of CL2) are earlier or later than the data.

Specifically, first, the N-th data is "1"
When the data transition in which the (N + 1) th data becomes “0” occurs, the bit cell center sampling latch circuit 2
Assuming that the output of the bit 41 is D (N) and the output of the bit cell boundary sampling latch circuit 242 is B (N), the series of “D (N), B (N), D (N + 1)” is “1”. , 0,0 "or" 1,1,0 ". here,
The series "1,0,0" indicates that the timing of the sampling control clocks (CL1, CL2) is later than the data, and the series "1,1,0" indicates that the timing of the control clock is longer than the data. It indicates that it was early.

Next, the N-th data is "0", and N + 1
When a data transition occurs in which the data of the 1st becomes “1”,
“D (N), B (N), D (N + 1)” is the series “0,
"0, 1" indicates that the timing of the control clocks (CL1, CL2) for sampling is earlier than the data, and in the series "0, 1, 1", the control clock is later than the data. It is shown that.

Then, the two latch circuits 241 and 2
By passing the output of 42 to the combinational logic circuit 212, it is possible to obtain a determination signal (up signal UP, down signal DN) as to whether the control clocks CL1 and CL2 should be made slower or faster. This determination signal (U
P, DN) are counted by an up / down counter 234, and the contents are counted as 6-bit signals (C00, C01, C0).
2; C10, C11, C12) and supply them to the phase interpolator 236 to control the control clocks CL1 and C2.
By controlling the timing of L2, the timing of signal reception can be optimized and the S / N ratio can be increased.

Here, the processing for optimizing the signal reception timing in the eleventh embodiment is performed, for example, by using a signal dedicated to this timing optimization (a special signal, for example,
This can be performed while the “101010...” Sequence is being sent. As described above, according to the eleventh embodiment, the A / D converter 220 for evaluating the signal reception strength as an analog quantity as in the above-described tenth embodiment can be omitted, and the switch can be switched. There is an advantage that timing optimization processing can be performed in multiple bits in parallel without successive selection by means 210. Therefore,
In each bit, when a transition from "0" to "1" or "1" to "0" is guaranteed at a certain frequency (for example, when data is coded by a method such as 10B / 8B) In this case, the process of optimizing the reception timing for each bit can be performed in parallel with the data transmission and reception.

FIG. 26 shows a phase interpolator (phase adjuster) 23 in the timing signal generating circuit of FIG.
FIG. 6 is a circuit diagram showing an example of the sixth embodiment. As shown in FIGS. 25 and 26, the phase interpolator 236 has a 6-bit signal (C0) from the up / down counter 234.
0, C01, C02; C10, C11, C12) and outputs (φ1, / φ1, φ2, / φ2) of the four-phase PLL circuit (250) provided in the parent circuit 1. With these 6-bit signals, the differential inputs in each of the differential amplifier stages 2361 and 2362 are weighted. Here, the outputs (φ1,
/ Φ1, φ2, / φ2) are switched and supplied. Then, as in FIG.
The control clocks CL1 and CL2 are generated by passing the signals from the pair of differential amplifier stages 2361 and 2362 to an output stage (comparator) 2363.

FIG. 27 is a circuit diagram showing an example of a four-phase PLL circuit 250 that can be used in the timing signal generation circuit of FIG. As shown in FIG. 27, the four-phase PLL circuit 25
0 denotes a four-stage differential amplifier 2511 to 2514, four signal converters 2521 to 2524, and an inverter 25.
31 to 2534 are provided. That is, 4
Stage differential amplifiers 2511 to 2514 are connected in cascade, a predetermined signal is supplied to each signal converter 2521 to 2524, and level inversion and waveform shaping are performed by inverters 2531 to 2534 to output four-phase output signals φ1, / φ1. , Φ2, / φ2.

FIG. 28 is a circuit diagram showing an example of the signal conversion unit 252 (2521 to 2524) in the four-phase PLL circuit of FIG. 27. FIG. 29 is a circuit diagram showing the differential amplifier unit 251 (2511) in the four-phase PLL circuit of FIG. FIG. 252 is a circuit diagram illustrating an example. As shown in FIG. 27 and FIG. 28, two input signals (A, B) are supplied to the signal conversion unit 252 (2521 to 2524), and one output signal (Z) is output. . That is, each of the signal conversion units 252 (2521 to 2524) is provided with the second-stage differential amplifier unit 25 of the four-stage differential amplifier units connected in cascade.
Two output signals of the twelfth or fourth stage differential amplifier 2514 are supplied as inputs A and B, respectively, and these two inputs A and B are processed to generate one output Z. The output Z is output from the inverter 253.
(2531 to 2534), and are output from the four-phase PLL circuit 250 as outputs φ1, φ2, / φ1, / φ2, respectively. Here, when the signal INH is at the high level “H”, the signal conversion unit 252 always outputs the signal (Z) at the high level “H”, the signal INH is at the low level “L”, and the control signal CTL. Is high level "H", a signal (Z) corresponding to the input signals A and B is output.

As shown in FIGS. 27 and 29, the differential amplifiers 251 (2511 to 2514) are connected in cascade, and the output signals (OUT1, OUT2) of the differential amplifiers 2511, 2512, and 2513 in the preceding stage are output in the subsequent stage. Differential amplifier 2
Input signals IN1, IN2 of 512, 2513, 2514
It is supplied as. The first-stage differential amplifier 2511 has a final-stage (fourth-stage) differential amplifier 2
An output signal of 514 is provided. Here, the differential amplifier 2
Reference numeral 51 is activated when the control signal CTL is at a high level "H".

FIG. 30 is a diagram showing output signals of the four-phase PLL circuit of FIG. 4 configured by applying the signal conversion unit 252 and the differential amplification unit 251 shown in FIG. 28 and FIG.
By the phase PLL circuit 250, four-phase output signals φ1, φ2, / φ1,
/ Φ2 is obtained. These signals φ1, φ2, / φ1,
For example, / φ2 is supplied to the phase interpolator 236 in the slave circuit 2 as shown in FIG.

The configurations of the four-phase PLL circuit 250, the signal converter 252, and the differential amplifier 251 are not limited to those described above, and various circuit configurations can be employed. Not even. As described above, according to the timing signal generation circuit according to each embodiment of the present invention, a timing signal synchronized with a reference clock can be generated by a child circuit having a configuration much simpler than that of a parent circuit. Further, by changing the response speed of the slave circuit in accordance with the frequency of the reference clock, it is possible to generate a highly accurate timing signal over a wide frequency range.
That is, timing pulses having a fixed phase difference relationship can be generated by a large number of child circuits having a simple structure in synchronization with the reference clock signal. It can be generated by an occupied area circuit.

The parent circuit and the plurality of child circuits can be provided in one semiconductor integrated circuit device (LSI chip). However, the parent circuit and each of the child circuits are provided in different semiconductor integrated circuit devices. May be. That is, the timing signal generation circuit according to each embodiment of the present invention can be applied to a semiconductor integrated circuit system having a plurality of semiconductor integrated circuit devices, a multi-chip module (MCM), and the like.

Next, an embodiment of the phase interpolator according to the present invention will be described with reference to the accompanying drawings. FIG. 31 is a block diagram showing the principle configuration of the phase interpolator according to the present invention, and FIG. 32 is a waveform diagram for explaining the operation of the phase interpolator of FIG.

In FIG. 31, reference numerals 41 and 42
Is an analog periodic waveform generator, 43 is a weight controller, 4
Reference numeral 4 denotes an addition waveform generator, and reference numeral 45 denotes an analog / digital converter. As shown in FIG. 31, the analog periodic waveform generator 41 receives the first digital periodic signal DIS1 and generates a first analog periodic waveform (f1: see FIG. 32) having an analog value. In addition, the analog periodic waveform generator 42 receives the second digital periodic signal DIS2 and generates a second analog periodic waveform (f2: see FIG. 32) having an analog value. Here, the first digital periodic signal DIS1 and the second digital periodic signal DI
S2 is a signal shifted in time axis (a signal having a different phase). It should be noted that the phase interpolator is, for example, such digital signals DIS1 and D
A digital signal having an arbitrary arbitrary intermediate phase is generated from IS2.

The first analog periodic waveform f1 and the second analog periodic waveform f2 are weighted by the weight control section 43, added by the addition waveform generating section 44, and added to the third analog periodic waveform (f3: FIG. 32) is generated. That is, if x is 0 ≦ x ≦ 1, f3 =
The third analog periodic waveform f3 as (1−x) f1 + xf2 is obtained as the output of the added waveform generation unit 44.

The analog / digital converter 45
As a result, the third analog periodic waveform f3 is converted into a third digital periodic signal DO having a predetermined phase and output. Here, the analog / digital conversion unit 45 is, for example, an example. It is configured by a comparator that compares the third analog periodic waveform f3 with the reference voltage Vr and outputs “0” or “1”.

The phase interpolator according to the present invention is, for example, a phase interpolator 136, 236 (see FIGS. 14 and 19) in the above-described timing signal generating circuit.
And FIG. 20, etc.), but it goes without saying that it can be widely applied to various other circuits. FIG. 33 is a circuit diagram showing a configuration example of a phase interpolator as a twelfth embodiment of the present invention.
FIG. 34 is a circuit diagram showing a configuration example of a weight control unit in the phase interpolator of FIG. 33, reference numerals 41a, 41b and 42a, 42b denote sine wave generation circuits, 430 denotes a weight control circuit (weight control unit), 440 denotes an operational amplifier circuit (addition waveform generation circuit),
Reference numeral 450 denotes a comparison circuit (analog / digital conversion circuit).

As described above with reference to FIG. 21,
The phase interpolator of the twelfth embodiment shown in FIG. 33 includes digital signals (square waves) DIS1 and DIS2.
Is passed through delay circuits 41a and 42a to convert a rectangular wave into a triangular wave, and is further passed through driver circuits (nonlinear amplifier circuits) 41b and 42b to convert the triangular wave into a sine wave (pseudo sine wave). It has become. Further, these sine waves (f1 and f2) are supplied to the weight control circuit 430, and are weighted by the weight control sections (4301 and 4302), respectively, and then added by the operational amplifier circuit 440.
The signal is supplied to the comparator 450.

As shown in FIG. 34, the weight control section 4301 (4302) comprises a plurality (n) of transfer gates provided in parallel between the input and the output. The connection transfer of these n (for example, 16) transfer gates is controlled by control signals C41 to C4n, respectively, and the sine wave f
1 (f2) is weighted.
That is, in the circuit example of FIG. 34, the control signals C41 to C4
By making any number of n high level "H",
A corresponding number of transfer gates are turned on to change the conductance (the conductance on the input side of the operational amplifier circuit 440).

In FIG. 34, the nMOS and pMOS transistors forming each transfer gate are all configured to have the same size. However, the size of the nMOS and pMOS transistors in each transfer gate is changed (for example, the minimum transistor size). The gate width is set to 1, and the gate widths of the other transistors are set to 1.1, 1.2, 1.3,...), And any transfer gate is turned on, or any combination of a plurality of transfer gates is turned on. Accordingly, the sine wave f1 (f2) may be weighted by conducting at least one transfer gate.

FIG. 35 is a circuit diagram showing a configuration example of a phase interpolator according to a thirteenth embodiment of the present invention. FIG.
5, reference numeral 4101 denotes a selector circuit, 411
1 to 411n indicate CMOS inverters, 4103 indicates a capacitive load, and 4104 indicates a comparison circuit (comparator). The selector circuit 4101 includes k CMOS inverters 4111 to 411k to which the first digital periodic signal DIS1 is input, and a second digital periodic signal D
Nk CMOS inverters 41 to which IS2 is input
1k to 411n are selectively controlled. That is,
The digital signal DIS1 is output by the selector circuit 4101.
, And the number (nk) of CMOS inverters receiving the digital periodic signal DIS2 are controlled.
Here, for example, 16 CMOS inverters 4111 to 411n are provided. The outputs of the CMOS inverters 4111 to 411n are commonly connected and supplied to a terminal (input terminal of the comparator 4104) to which the capacitive load 4103 is connected. Then, the comparator 410
4, the digital periodic signal DO of "0" or "1" is output in comparison with the reference voltage Vr (1 / 2.Vcc).

Each of the CMOS inverters 4111 to 411n
Is a digital signal DIS1 or DIS which is a square wave.
2 is directly input, but each CMOS inverter 4111
To 411n become analog periodic waveforms each having an analog value due to the capacitive load 4103. In the phase interpolator of the thirteenth embodiment, the digital signals (DIS1, DIS2) are controlled by controlling the number of CMOS inverters connected to the first and second digital periodic signals DIS1, DIS2, respectively.
And the control of weighting the analog waveform. The phase interpolator of the thirteenth embodiment has the advantage that a sine wave generation circuit is not required and the linearity of weight control is high.

FIG. 36 is a circuit diagram showing a configuration example of a phase interpolator according to a fourteenth embodiment of the present invention. In the phase interpolator of the fourteenth embodiment, each of the digital signals DIS1 and DIS2 is received by two inverters 4211, 4212 and 4221 and 4222, respectively, and these inverters 4211, 4212 and 422
The pMOS and nMOS transistors of the output stages 4231 to 423n and 4241 to 424n of a plurality of CMOS inverters are driven by the outputs of 1,4222. Here, each output stage 4231 to 423n
The outputs of (4241 to 424n) are control signals C4
The signals are taken out via transfer gates that are connected and controlled by 11 to C41n (C421 to C42n), connected in common, and supplied to the input of a comparator 4250.

That is, the phase interpolator of the fourteenth embodiment uses a plurality of CMOS inverters for weighting control, as in the thirteenth embodiment.
Only the output stage controls the number of connections by a control signal, and the input circuits (inverters 4211 and 4212 and 4221 and 4222) are common. Here, each output stage (and each transfer gate) 4231 to 423
n and nMOS and pMOS transistors constituting 4241 to 424n are configured to have the same size,
The number of output stages for connection control is, for example, 16 or 32.

In the phase interpolator of the fourteenth embodiment, since the input capacitance of the circuit is constant irrespective of the weight value, the input digital signal DIS caused by the loading effect is obtained.
There is an advantage that a digital signal DO having a more accurate timing (phase difference) can be generated without generating a phase shift between DIS1 and DIS2. FIG. 37 shows the first embodiment of the present invention.
FIG. 38 is a circuit diagram showing a configuration example of a phase interpolator as a fifth embodiment, and FIG. 38 is a circuit diagram showing an example of a transconductor in the phase interpolator of FIG.

As shown in FIG. 37, the phase interpolator according to the fifteenth embodiment includes digital input signals DI
S1 and DIS2 are converted into triangular waves by an integrating circuit including inverters 4301 and 4302 and capacitive loads 4303 and 4304, respectively, and transconductors (variable transconductors) 4305 and 430 are converted.
6 Here, the integration circuit is obtained by switching a constant current by a digital signal. However, various other integration circuits can be used, and a filter that attenuates high frequency components of the digital signal instead of the integration circuit is used. It may be a circuit.

As shown in FIGS. 38 (a) and 38 (b), transconductors 4305 (4306)
Extracts a current output corresponding to the input voltage. First, the transconductor 4305 in FIG.
Are pMOS transistors 4351 and 4354, nMO
The transistor 4351 includes an S transistor 4352 and a resistor 4353, and outputs a current corresponding to an input voltage (IN) applied to the gate of the transistor 4352 to the transistor 4351.
, And a current flowing through a transistor 4354 that is connected to the transistor 4351 in a current mirror connection is extracted as a current output.

The transconductor 4305 shown in FIG. 38B is composed of pMOS transistors 4361 and 436
4,4366 and nMOS transistor 436
2, 4363 and 4365, and an input voltage (IN) applied to one input (gate of the transistor 4362) of the differential circuit and a reference voltage applied to the other input
The current flowing through the transistor 4364 according to (1/2 · Vcc) is taken out as a current output from the transistor 4366 that is current mirror connected to the transistor 4364.

The transconductor 4305 (43
For 06), various transconductor circuits known in the field of continuous-time analog processing other than those shown in FIG. 38 can be applied. As shown in FIG.
After the triangular wave is converted into a current signal by the transconductors 4305 and 4306, and output to the resistive load 4307, a weighted sum is realized. Then, a digital signal DO having a predetermined phase is generated by comparison with a reference voltage (1/2 · Vcc) by a comparator 4308.

The phase interpolator of the fifteenth embodiment has the advantage that a circuit for converting into a triangular wave and a circuit for forming a sum can be separately optimized, so that a highly accurate circuit can be designed. FIG. 39 is a circuit diagram showing a configuration example of a phase interpolator as a sixteenth embodiment of the present invention. In FIG. 39, reference numeral V1 + denotes a first digital periodic signal DIS.
1 and V1- is the first digital periodic signal DIS
1, V2 + corresponds to the second digital periodic signal DIS2, and V2-
Is an inverted signal of the second digital periodic signal DIS2 (/ D
IS2).

As shown in FIG. 39, in the phase interpolator of the sixteenth embodiment, the analog periodic waveform generation section and the addition waveform generation section have constant current sources with switches (4401, 4403 and 4402, 4404). Are connected to capacitive loads (4405 and 4406). That is, the first input digital signal D
When IS1 (V1 +) is at the high level “H”, the nMOS transistor 4414 in the constant current source 4401 with a switch is turned on and the pMOS transistor 4411 is turned off, and the constant current source 440 with a switch is turned on.
2, the pMOS transistor 4421 is turned on and the pMOS transistor 4421 is turned on, a current flows through the capacitive load 4405 through the nMOS transistors 4413 and 4414, and the capacitive load 4440
A current flows through 6 through pMOS transistors 4421 and 4422. Conversely, when the first input digital signal DIS1 is at a low level “L”, the capacitive load 4405
, Current flows through pMOS transistors 4411 and 4412, and the capacitive load 4406
Current flows through transistors 4423 and 4424. The second input digital signal DI having a different phase
The same applies to S2 (V2 +). The other end of the capacitive load 4405 whose one end is connected to the positive logic input of the comparator 4407 is set to the intermediate potential (1/2 · Vcc). Similarly, the capacitive load whose one end is connected to the negative logic input of the comparator 4407 The other end of 4406 is also at the intermediate potential (1 / 2.Vcc).

Then, the positive logic digital periodic signal DI
S1, DIS2 (V1 +, V2 +), an analog addition waveform (a waveform at one end of the capacitive load 4405) and a negative logic digital periodic signal / DIS1, / DIS2 (V
1-, V2-) analog addition waveform (capacitive load 4
406) and the comparator 4407
, And a digital periodic signal DO corresponding to the comparison result is output.

In the phase interpolator of the sixteenth embodiment, the weighting is controlled by the bias signal (Vc
(p1, Vcn1; Vcp2, Vcn2). The circuit for generating the bias signal will be described later with reference to FIGS. 40 and 41. As described above, in the phase interpolator of the sixteenth embodiment, the analog periodic waveform generation unit and the addition waveform generation unit output the first digital periodic signal DIS1 (V1
+, V1-) from the constant current sources (4412, 4413 and 4422, 4423) to the common capacitive load (440).
Current polarity switching means (4411, 4414 and 4421) for switching the polarity of the current flowing through
4424) and current value control means (4412, 4413 and 4422, 442) for controlling the current value of the current source
3) is provided. Note that the second digital periodic signal DIS2 has the same configuration.

The constant current source 4401 with switch (4402)
To 4404) are pMOs constituting a CMOS inverter.
S transistor 4411 and nMOS transistor 4
414 has a structure in which a pMOS transistor 4412 and an nMOS transistor 4413 biased in a constant current mode are inserted on each drain side. In addition, CM
The source side, not the drain side, of the transistor constituting the OS inverter (between the source of the pMOS transistor 4411 and the high potential power supply line Vcc, and between the source of the nMOS transistor 4414 and the low potential power supply line Vss)
A pMOS transistor and an nMOS transistor biased in the constant current mode may be inserted into the IGBT.

The phase interpolator of the sixteenth embodiment has a function of converting a digital input signal into an analog signal (function of an analog periodic waveform generation unit) and a function of generating a sum (function of an addition waveform generation unit). Can be realized on one terminal, and the circuit configuration can be simplified to reduce power consumption. FIG. 40 is a circuit diagram showing an example of a circuit for generating a bias signal in the phase interpolator of FIG. 39, and FIG. 41 is a circuit showing another example of a circuit for generating a bias signal in the phase interpolator of FIG. FIG.

As described above, the phase interpolator shown in FIG. 39 uses the digital periodic signals DIS1, DIS
2; control of the weighting of / DIS1, / DIS2 is performed by changing the voltage level of bias signals Vcp1, Vcn1; Vcp2, Vcn2. FIG. 40 and FIG.

As shown in FIG. 40, as an example of the bias signal generation circuit 4408, a plurality of sets of two pMOS transistors 4481 and 4482 connected in series are provided in parallel, In addition to applying a reference voltage (Vr), control signals (digital signals) C431 to C43n are supplied to the gates of the other transistors 4482 to perform switching control.

Here, a set of two transistors (448
1, 4482) are all nMOS transistors 4483
Of the control signals C431 to C4
The sum of the currents flowing through the set of transistors selected (conducted) by 3n is the nMOS transistor 44
83. Further, the current flowing through the transistor 4483 is equal to the current mirror-connected n
MOS transistor 4484 and pMOS transistor 4 connected in series with transistor 4484
485. Then, the bias signal Vcp1 is supplied via the transistors 4485 and 4484 (4483).
(Vcp2) and Vcn1 (Vcn2) are obtained. The phase interpolator of FIG. 39 requires two bias signal generation circuits, one for generating bias signals Vcp1 and Vcn1 and the other for generating bias signals Vcp2 and Vcn2.
Positive logic control signals C431 to C43 for the bias signal generation circuit for generating the bias signals Vcp1 and Vcn1
n, the bias signals Vcp2 and Vcn
2 is supplied to the bias signal generating circuit for generating the control signal 2 to control the weighting by supplying the control signal (/ C431 to / C43n) of the inverted logic.

As described above, the bias signal generating circuit 4408 shown in FIG. 40 is configured as a current output type D / A converter, and the current source on the controlled side receives the current received from the D / A converter by the current mirror circuit. A variable constant current is obtained by mirroring, and the control signals C431 to C43n
Signal Vcp having a predetermined voltage level according to
1 (Vcp2) and Vcn1 (Vcn2). This bias signal generation circuit has an advantage that it can be realized with a small amount of circuit because the current source on the controlled side has a simple configuration.

FIG. 41 is a circuit diagram showing another example of a circuit for generating a bias signal in the phase interpolator of FIG. As shown in FIG. 41, as another example of the bias signal generation circuit 4408, a control signal (digital signal) C4
PMOS switching-controlled by 41 to C44n
One end (source) of the transistors 4487 and 4488 is connected. Here, the gate of each set of transistors 4487 has a corresponding control signal C44
1 to C44n, and each set of transistors 4
The control signals (/ C441 to / C44n) inverted by the inverter 4489 are respectively supplied to the gates 488. Therefore, in each set, one of the transistors 4487 and 4488 is turned on and the other is turned off.

The other end (drain) of each set of transistors 4487 is connected in common, and the transistors 4487 in the ON state are connected.
The sum of the currents flowing through 87 is nMOS transistor 448
Similarly, the other end of each set of transistors 4488 is connected in common, so that the total current flowing through the transistor 4488 in the ON state flows through the nMOS transistor 44832. Then, as described with reference to FIG. 40, the current flowing through transistors 44831 and 44832 is converted into current mirror-connected nMOS transistors 44841 and 44842 and transistor 44841.
To the pMOS transistors 44851 and 44852 connected in series with the bias signals Vcp1, Vcn1 and Vcp2, Vcn2, respectively.
Is obtained.

As described above, in the bias signal generation circuit 4408 shown in FIG. 41, the output of the current control type D / A converter for controlling the output value of the current source is switched and connected to the complementary output node. It has become so. Here, since the output current itself of the D / A converter is always kept constant, the voltage of the output transistor of the D / A converter is kept constant, and a spike-like transient as seen when the current is interrupted. There is an advantage that there is no response.
Further, the current consumption of the current output type D / A converter can be reduced (about half).

FIG. 42 is a circuit diagram showing a configuration example of a variable current source (4500) as a modification of the sixteenth embodiment of FIG. 39. 4401 to 4404). In the current source 4500 shown in FIG. 42, the bias signals (bias voltages) Vcp and Vcn are signals of a constant voltage level, and the control signals C451 to C4
5n controls the weighting.

As shown in FIG. 42, the variable current source 4500 of the present modification is different from the constant current source 4401 of FIG. 39 in that the bias signals Vcp (Vcp1) and Vcn (Vcn
cn1) are supplied to the transistors 4501 and 45
03 (corresponding to 4412 and 4413) are provided in plural sets,
A pMOS transistor 4506 and an nMOS transistor 4508 are provided between these sets of transistors 4501 and 4503, respectively. Here, control signals C451 to C45n of positive logic are supplied to the gates of the transistors 4508 of each set, and the control signals (/ C451 to / C451 to
/ C45n). And 450 of each set
The connection nodes 6 and 4508 are commonly connected to take out an output (output terminal) out. Note that this output terminal out is, as shown in FIG.
For example, it is connected to one end of the capacitive load (4405 or 4406) and one input terminal of the comparator (4407).

As described above, the variable current source of this modification shown in FIG. 42 controls the number of output transistors (4506, 4508) of the current mirror in order to obtain a variable current source. Transistor (450
2,4503) gate bias (bias signal Vc)
p, Vcn) is always kept constant.
The current stability can be increased. Further, the variable current source according to the present modification has an advantage that the linearity is improved because the current is controlled by the number of transistors.

FIG. 43 is a circuit diagram showing a partial configuration example of a phase interpolator according to a seventeenth embodiment of the present invention. In the phase interpolator shown in FIG. 39, a clamp is provided between two input terminals of a comparator 4407. Circuit 4600
Is provided. As shown in FIG. 43, for example, by providing a clamp circuit 4600 between two input terminals (a node generated by adding an analog waveform) of the comparator 4407 in the phase interpolator of FIG. Even when the values are unbalanced, the common mode potential of these nodes is kept constant by the clamp circuit 4600, so that the comparison operation by the next-stage comparator 4407 can always be performed in a constant state, and the timing Accuracy can be improved.

The clamp circuit 4600 shown in FIG. 43 comprises two nMOS transistors 4601 and 4 connected in series.
A voltage of 1 / 2.Vcc (reference voltage) is applied to each gate of the transistor 602, and a voltage of 1 / 2.Vcc is also applied to a connection point of the transistors 4601 and 4602, so that two input terminals of the comparator 4407 are connected. Is clamped. As the clamp circuit 4600, those having various configurations other than those shown in FIG. 43 can be applied.

FIG. 44 is a view for explaining a configuration example of the phase interpolator according to the eighteenth embodiment of the present invention. In FIG. 44, the horizontal axis shows the D / A input code, that is, the number of transistors selected (connected) by the control signal, and the vertical axis shows the output current as the total flowing through these selected transistors. Is shown. As described above, the phase interpolator of the present invention selects, for example, a plurality of transistors of the same size by a control signal (digital signal) in order to realize weighting control for controlling weighting of each analog periodic waveform. The current output is adjusted by controlling the number of transistors to be connected.

The characteristic curve LL1 in FIG. 44 shows the relationship between the number of connected transistors and the output current when a transistor of the same size is selected by a control signal, and is a non-linear curve. Therefore, in the eighteenth embodiment, as shown by a characteristic curve LL2 in FIG. 44, the relationship between the number of transistors controlled by the control signal and the output current becomes a linear curve (straight line). This is for adjusting the size of the transistor.

For example, in the bias signal generating circuit shown in FIG. 40, the number of transistors 4482 that are turned on (connected) is controlled according to control signals C431 to C43n, and the current flowing through all the transistors 4482 that are turned on is controlled. The sum flows through the transistor 4483. In such a case, by applying the eighteenth embodiment, the number of transistors 4482 that are turned on according to the control signals C431 to C43n and the current flowing through the transistor 4483 (output current ) And the size of each transistor 4482 (4481) is adjusted so that a linear relationship is maintained. The adjustment of the transistor size
In addition to the transistors in the current D / A converter, transistors related to the current mirror circuit and the like (for example, transistors 4483, 4484, 4
485 etc.) can also be adjusted.

As described above, by applying the eighteenth embodiment, the timing accuracy of the signal output from the phase interpolator can be further improved.

[0111]

As described above, according to the present invention, it is possible to generate a plurality of timing signals having a predetermined phase difference in synchronization with a reference clock with a simple configuration and with high accuracy. . That is, according to the present invention, it is possible to generate timing pulses having a fixed phase difference relationship in synchronization with the reference clock signal by a plurality of child circuits having a simple structure. Therefore, a high-precision timing signal required for transmitting and receiving a high-speed signal can be generated with a small circuit area.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a conventional timing signal generation circuit.

FIG. 2 is a block diagram showing a principle configuration of a timing signal generation circuit according to the present invention.

FIG. 3 is a block diagram illustrating a configuration example of a timing signal generation circuit according to a first embodiment of the present invention;

FIG. 4 is a circuit diagram showing an example of a delay unit in a variable delay line of the timing signal generation circuit of FIG. 3;

FIG. 5 is a block circuit diagram illustrating an example of a phase comparison circuit in the timing signal generation circuit of FIG. 3;

FIG. 6 is a timing chart for explaining the operation of the phase comparison circuit of FIG. 5;

FIG. 7 is a circuit diagram illustrating an example of a charge pump circuit in the timing signal generation circuit of FIG. 3;

8 is a circuit diagram showing another example of the delay unit in the variable delay line of the timing signal generation circuit of FIG.

FIG. 9 is a block circuit diagram illustrating a configuration example of a control signal generation circuit in a timing signal generation circuit according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating an example of a current-voltage conversion circuit that converts an output of the control signal generation circuit of FIG. 9;

FIG. 11 is a block diagram illustrating an example of a main configuration of a timing signal generation circuit according to a third embodiment of the present invention;

FIG. 12 shows the output of the up / down counter of FIG.
FIG. 3 is a block circuit diagram illustrating an example of a D / A converter that performs A-conversion.

13 is a circuit diagram showing a configuration example of one current matrix cell in the D / A converter shown in FIG.

FIG. 14 is a block diagram showing a configuration example of a timing signal generation circuit applied to a slave circuit as a fourth embodiment of the present invention.

FIG. 15 is a circuit diagram showing an example of the phase interpolator of FIG.

FIG. 16 is a circuit diagram showing a configuration example of a phase interpolator as a fifth embodiment of the present invention.

FIG. 17 is a circuit diagram showing a configuration example of a timing signal generation circuit used for performing a simulation according to a fifth embodiment of the present invention.

18 is a diagram illustrating a simulation result of the timing signal generation circuit of FIG. 17;

FIG. 19 is a block diagram showing a configuration example of a timing signal generation circuit as a sixth embodiment of the present invention.

FIG. 20 is a block diagram illustrating a configuration example of a timing signal generation circuit according to a seventh embodiment of the present invention;

FIG. 21 is a circuit diagram showing a configuration example of a sine wave generation circuit as an eighth embodiment of the present invention.

FIG. 22 is a diagram illustrating a simulation result of the sine wave generation circuit of FIG. 21;

FIG. 23 is a block diagram illustrating a configuration example of a timing signal generation circuit according to a ninth embodiment of the present invention.

FIG. 24 is a block diagram illustrating a configuration example of a timing signal generation circuit according to a tenth embodiment of the present invention.

FIG. 25 is a block diagram illustrating an example of a main configuration of a timing signal generation circuit according to an eleventh embodiment of the present invention.

26 is a circuit diagram showing an example of a phase interpolator (phase adjuster) in the timing signal generation circuit of FIG.

FIG. 27 is a circuit diagram showing an example of a four-phase PLL circuit that can be used for the timing signal generation circuit of FIG.

FIG. 28 is a circuit diagram illustrating an example of a differential amplifier in the four-phase PLL circuit of FIG. 27;

FIG. 29 is a circuit diagram showing an example of a signal converter in the four-phase PLL circuit of FIG. 27;

FIG. 30 is a diagram illustrating output signals of the four-phase PLL circuit of FIG. 27;

FIG. 31 is a block diagram showing the principle configuration of a phase interpolator according to the present invention.

FIG. 32 is a waveform chart for explaining the operation of the phase interpolator in FIG. 31.

FIG. 33 is a circuit diagram showing a configuration example of a phase interpolator as a twelfth embodiment of the present invention.

FIG. 34 is a circuit diagram illustrating a configuration example of a weight control unit in the phase interpolator of FIG. 33;

FIG. 35 is a circuit diagram showing a configuration example of a phase interpolator as a thirteenth embodiment of the present invention.

FIG. 36 is a circuit diagram showing a configuration example of a phase interpolator as a fourteenth embodiment of the present invention.

FIG. 37 is a circuit diagram showing a configuration example of a phase interpolator according to a fifteenth embodiment of the present invention.

FIG. 38 is a circuit diagram showing an example of a transconductor in the phase interpolator of FIG. 37.

FIG. 39 is a circuit diagram showing a configuration example of a phase interpolator as a sixteenth embodiment of the present invention.

40 is a circuit diagram illustrating an example of a circuit that generates a bias signal in the phase interpolator of FIG. 39.

FIG. 41 is a circuit diagram showing another example of a circuit for generating a bias signal in the phase interpolator of FIG. 39;

FIG. 42 is a circuit diagram showing a configuration example of a variable current source as a modification of the sixteenth embodiment of FIG. 39;

FIG. 43 is a circuit diagram showing a configuration example of a part of a phase interpolator as a seventeenth embodiment of the present invention.

FIG. 44 is a diagram illustrating a configuration example of a phase interpolator according to an eighteenth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Parent circuit 2 ... Child circuit 10 ... DLL circuit 11 ... Variable delay line 12, 12a, 12b ... Phase comparison circuit 13 ... Control signal generation circuit 14 ... Driving circuit (clock driver) 15 ... Selector 21 ... Voltage controlled oscillator (VCO) 131 ... charge pump circuit 132 ... buffer amplifier 133 ... current-voltage conversion circuit 134,134a, 134b, 234 ... up / down counter 135 ... D / A converter 136,236 ... phase interpolator 212 ... combinational logic circuit 210 ... selection Means 220 A / D converter 230 Control circuit 241, 242 Latch circuit 250 Four-phase PLL circuit CKr Reference clock CKin Internal clock CS Control signal D Delay unit (delay stage) 41, 42 Analog periodic waveform Generation unit 43: weight control unit 44 Added waveform generator 45 ... analog / digital converter unit DIS1 ... first digital periodic signal DIS2 ... second digital periodic signal DO ... digital output signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hisakatsu Araki 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shigetoshi Wakayama 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Inside Fujitsu Limited

Claims (38)

[Claims] 1. A parent circuit for generating an internal signal having the same cycle or phase as an input reference signal by feedback control, receiving an internal signal and a control signal from the parent circuit,
And a slave circuit for generating a timing signal having a predetermined timing with respect to the reference signal. 2. The timing signal generating circuit according to claim 1, wherein a plurality of said child circuits are provided for one parent circuit. 3. The timing signal generating circuit according to claim 1, wherein the parent circuit includes a circuit corresponding to the child circuit, and the parent circuit itself outputs a timing signal. A timing signal generating circuit. 4. The timing signal generation circuit according to claim 1, wherein said parent circuit compares a cycle or a phase of said reference signal and said internal signal, and said comparison circuit. A control signal generating circuit that changes the control signal in accordance with the output of the control signal, and a variable delay line that controls the delay amount of the reference signal by the control signal and outputs the internal signal. Signal generation circuit. 5. The timing signal generation circuit according to claim 4, wherein said parent circuit is a DLL circuit.
The circuit has a coarse delay control unit for performing coarse delay control and a fine delay control unit for performing fine delay control, and the slave circuit includes a circuit corresponding to the fine delay control unit. Generator circuit. 6. The timing signal generating circuit according to claim 5, wherein said coarse delay control section takes out taps from a delay line having a plurality of delay units and selects an output of each of said taps to perform coarse delay control. And the fine delay control unit receives a signal for controlling the DLL circuit in the coarse delay control unit and a signal subjected to the coarse delay control from the coarse delay control unit, and A timing signal generating circuit for performing fine delay control on a signal using a phase interpolator. 7. The timing signal generation circuit according to claim 1, wherein the parent circuit compares a cycle or a phase of the reference signal and the internal signal, and the comparison circuit. A timing signal generating circuit comprising: a control signal generating circuit that changes the control signal in accordance with an output of the control signal; and a voltage controlled oscillator that generates an internal signal corresponding to the reference signal in accordance with the control signal. . 8. The timing signal generating circuit according to claim 7, wherein said child circuit includes a voltage controlled oscillator for outputting said timing signal in response to a control signal from said parent circuit. Timing signal generation circuit. 9. The timing signal generation circuit according to claim 4, wherein said control signal generation circuit controls a voltage level of an output according to an up signal and a down signal from said comparison circuit. A timing signal generating circuit, comprising: 10. The timing signal generating circuit according to claim 4, wherein said control signal generating circuit includes an up / down counter for counting an up signal and a down signal from said comparison circuit; D / D for digital-to-analog conversion of the output of the up / down counter
A timing signal generation circuit comprising an A converter. 11. The timing signal generating circuit according to claim 1, wherein said child circuit outputs said timing signal by delaying said internal signal by a control signal from said parent circuit. A timing signal generation circuit comprising a variable delay line. 12. The timing signal generating circuit according to claim 1, wherein said child circuit receives a plurality of different input signals and outputs a finer intermediate phase timing signal. A timing signal generation circuit comprising a poller. 13. The timing signal generating circuit according to claim 12, wherein the input signals of the plurality of phases are three-phase or four-phase clocks. 14. The timing signal generating circuit according to claim 12, wherein the phase interpolator converts a plurality of input voltage signals into current signals, respectively, and a converted current signal. Current-voltage conversion means for changing a voltage conversion coefficient into a voltage signal again, and a comparison means for adding the obtained current signal and comparing the obtained current signal with the reference signal. Timing signal generation circuit. 15. The timing signal generation circuit according to claim 1, wherein the control signal sent from the parent circuit to the child circuit is a control current signal. 16. The timing signal generation circuit according to claim 15, wherein a control current signal generation circuit for generating the control current signal is provided in the parent circuit, and the control current signal is converted to a voltage signal in the child circuit. A timing signal generation circuit, comprising a current-voltage conversion circuit for conversion. 17. The timing signal generating circuit according to claim 1, wherein said slave circuit includes an amplifier circuit whose response speed changes in response to a signal from said parent circuit, A timing signal generating circuit for generating a sine wave signal as a signal. 18. The timing signal generating circuit according to claim 1, wherein said child circuit comprises:
It is used to generate a timing signal for controlling the timing of an input or output signal of one or more bits, and the timing signal generating circuit is provided in common for each of the slave circuits to transmit and receive the timing signal. A timing signal generating circuit comprising timing signal adjusting means for adjusting the S / N ratio of a signal to increase. 19. The timing signal generating circuit according to claim 18, wherein said timing signal adjusting means selects an input or output signal of a circuit controlled by a timing signal from each slave circuit, and said selecting means. A timing signal generating circuit comprising timing signal generating means for detecting the level of an input or output signal of a circuit selected by the means and controlling the output timing of the timing signal. 20. The timing signal generating circuit according to claim 1, wherein said child circuit comprises:
Each of the slave circuits is used to generate a timing signal for controlling the timing of an input or output signal of one or more bits, and each of the slave circuits is configured to increase the S / N ratio of a signal transmitted and received by the timing signal. A timing signal generation circuit comprising timing signal adjustment means for adjusting. 21. A semiconductor integrated circuit device to which the timing signal generation circuit according to claim 1 is applied, wherein said parent circuit and said child circuit constitute one chip. A semiconductor integrated circuit device provided in an integrated circuit device. 22. A semiconductor integrated circuit system to which the timing signal generation circuit according to claim 1 is applied, wherein said parent circuit and said child circuit are a plurality of different semiconductor chips. A semiconductor integrated circuit system provided in an integrated circuit device. 23. Analog periodic waveform generating means for generating an analog periodic waveform having an analog value from a digital periodic signal having a digital value amplitude, and weight control means for controlling weighting of each analog periodic waveform. Adding waveform generating means for adding a plurality of analog periodic waveforms obtained by the analog periodic waveform generating means from a digital periodic signal shifted in time axis to generate an added waveform; and an analog / digital converter for converting the added waveform into a digital waveform. A phase interpolator comprising: digital conversion means. 24. The phase interpolator according to claim 23, wherein the analog periodic waveform generation means includes a sine wave generation circuit, and the weight control means includes a plurality of transfer gates connected in parallel, A phase interpolator for controlling connection of the transfer gate. 25. The phase interpolator according to claim 24, wherein each transfer gate of the weight control means has a transistor of the same size.
A phase interpolator, wherein the weight of the analog periodic waveform is controlled by controlling the number of conduction of the transfer gate. 26. The phase interpolator according to claim 24, wherein each transfer gate of the weight control means has a transistor of a different size, and at least one of the transfer gates has a transistor of a predetermined size.
A phase interpolator characterized in that weighting of the analog periodic waveform is controlled by conducting two transfer gates. 27. The phase interpolator according to claim 23, wherein said analog periodic waveform generating means includes a plurality of CMOS inverters, and said weighting control means controls the number of connected CMOS inverters. A phase interpolator characterized in that: 28. The phase interpolator according to claim 23, wherein said analog periodic waveform generating means includes an output stage of a plurality of CMOS inverters, and said weight control means controls an output stage of said plurality of CMOS inverters. A phase interpolator, wherein the number of output transistors to be configured is controlled. 29. The phase interpolator according to claim 23, wherein the analog periodic waveform generating means is a high frequency component attenuating circuit for attenuating a high frequency component of the digital periodic signal, and wherein the weighting control means includes: A phase interpolator, wherein an output of a component attenuating circuit is converted into a current by a variable transconductor and the converted current is applied to a common terminal. 30. The phase interpolator according to claim 29, wherein said analog periodic waveform generating means is an integrating circuit. 31. The phase interpolator according to claim 23, wherein the analog periodic waveform generating means and the added waveform generating means switch the polarity of a current flowing from a constant current source to a common capacitive load according to the digital periodic signal. A phase interpolator comprising: a current polarity switching unit; and a current value control unit that controls a current value of the current source. 32. The phase interpolator according to claim 31, wherein said current value control means controls a current value of said current source by an output of a D / A converter. Phase interpolator. 33. The phase interpolator according to claim 23, wherein said analog / digital conversion means comprises:
A phase interpolator, which is a comparator for comparing the added waveform with a reference level and converting the digital waveform into a digital waveform. 34. The phase interpolator according to claim 23, wherein said weight control means includes a current output D.
/ A converter, and the output of the D / A converter is:
A phase interpolator characterized in that connection is controlled by being switched to one of a capacitor-connected terminal and its complementary terminal. 35. The phase interpolator according to claim 23, wherein said weight control means is configured to switch the number of current sources connected to a load capacitance terminal. Lator. 36. The phase interpolator according to claim 23, wherein said weight control means includes a clamp circuit for setting a voltage level of a terminal to a predetermined range. . 37. The phase interpolator according to claim 23, wherein the phase interpolator has a size of a transistor that can be switched and a D / A in order to make a linearity of a timing output with respect to a control signal a desired characteristic. A phase interpolator wherein the quantization step of the converter is made variable. 38. A timing signal generating circuit according to claim 12, wherein said phase interpolator is the phase interpolator according to any one of claims 23 to 37. Generator circuit.