JPH1126719A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent such a defect that an insulating film on a sidewall of a groove of a large area formed in a thick insulating film is peeled off. SOLUTION: After a SOG film 57 having a sufficient thickness to fill a groove 55 and a slot 59 formed in a silicon oxide film 53 is deposited, the SOG film 57 is etched back to expose a polycrystalline silicon film 56 for a lower electrode. Then, this polycrystalline silicon film 56 is etched back to leave only the groove 55 and the slot 59. At this point, an upper part of a groove 80 of a large area is covered with a photoresist film 81, thus preventing the SOG film 57 inside of the groove 80 from being etched back.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a DRAM (Dynamic Random Access Memory).
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having an access memory.

[0002]

2. Description of the Related Art A memory cell of a DRAM is arranged at an intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix on a main surface of a semiconductor substrate. Insulator Semiconductor Fie
ld Effect Transistor) and one information storage capacitor (capacitor) connected in series to the ld effect transistor.
The memory cell selecting MISFET is formed in an active region surrounded by an element isolation region, and mainly includes a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions forming a source and a drain. Is done. The bit line is arranged above the memory cell selecting MISFET, and is electrically connected to one of a source and a drain shared by two memory cell selecting MISFETs adjacent in the extending direction. The information storage capacitance element is similarly disposed above the memory cell selection MISFET, and is electrically connected to the other of the source and the drain.

[0003] Japanese Patent Application Laid-Open No. 7-7084 discloses a capacitor over bit line (Capacitor Over Bitline) structure in which an information storage capacitor is arranged above a bit line.
A RAM is disclosed. DRAM described in this publication
The lower electrode (storage electrode) of the information storage capacitor disposed above the bit line is formed in a cylindrical shape in order to compensate for the decrease in the storage charge (Cs) of the information storage capacitor accompanying the miniaturization of the memory cell. The capacitance insulating film and the upper electrode (plate electrode) are formed thereon.

Further, the DRAM described in this publication is
By forming a frame-shaped long groove (channel) surrounding the memory array at the boundary between the memory array and the peripheral circuit region and depositing a thick insulating film on the peripheral circuit region outside the memory array, the memory array and the peripheral circuit region are separated from each other. The step is eliminated and the peripheral circuit region is flattened. This long groove is formed at the same time as the step of processing the lower electrode of the information storage capacitor into a cylindrical shape, and its inner wall is made of the same material (polycrystalline silicon film) as the lower electrode.

[0005]

SUMMARY OF THE INVENTION The present inventor has studied a method of forming a lower electrode of an information storage capacitor in a memory array surrounded by a long groove as described above. The contents are as follows.

In order to form the cylindrical lower electrode as described above, first, a bit line is formed above a memory cell selecting MISFET and a MISFET of a peripheral circuit, and an information storage capacitor is formed above the bit line. An insulating film having a thickness corresponding to the height of the insulating film is deposited. Next, a groove is formed in the memory array by opening the insulating film by dry etching using a photoresist film as a mask, and at the same time, a long groove surrounding the memory array is formed at the boundary between the memory array and the peripheral circuit region. I do.

Next, a conductive film for a lower electrode is deposited on the insulating film including the inside of the groove and the long groove, and a thick second insulating film for filling the groove and the long groove is deposited thereon. Then, the second insulating film is etched back to expose the conductive film above the insulating film, and then the conductive film exposed above the insulating film is etched to leave the conductive film only inside the groove and the long groove. .

After that, using the photoresist film covering the peripheral circuit region as a mask, the insulating film remaining in the gap between the grooves and the second insulating film inside the groove are wet-etched to form a cylindrical lower electrode. I do.

In the above process, a groove is formed in the thick insulating film of the memory array by dry etching using a photoresist film as a mask, and at the same time, a long groove surrounding the memory array is formed in the insulating film at the boundary between the memory array and the peripheral circuit region. To form The photomask (reticle) that transfers the groove and long groove pattern to the photoresist film used at this time includes:
Since a pattern having a larger area than a groove or a long groove is formed, such as an alignment mark or a TEG pattern used for aligning a photomask (reticle) with a semiconductor substrate, the alignment mark or the TEG is formed.
A large-area and deep groove corresponding to these large-area patterns is simultaneously formed in the thick insulating film in a region corresponding to the pattern.

[0010] Therefore, in the next step, a conductive film for a lower electrode is deposited on the insulating film including the inside of these grooves (and the long grooves), and then these grooves (and the long grooves) are formed thereon.
When a second insulating film having a thickness large enough to bury the second insulating film is deposited, the second insulating film is not sufficiently embedded in the large-area deep groove corresponding to the alignment mark or the TEG pattern described above. When the second insulating film is etched back to expose the conductive film, the central portion of the large-area groove, that is, the portion where the thickness of the second insulating film is small is deeply shaved.

As a result, the conductive film at the bottom of the large-area groove is peeled off when the insulating film remaining in the gap between the grooves or the second insulating film inside the groove is wet-etched in a later step. There is a problem that the particles are scattered and become foreign matters, which lowers the manufacturing yield of the DRAM.

An object of the present invention is to provide a technique for preventing a defect that a conductive film at the bottom of a large-area groove is peeled off.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a method of manufacturing a semiconductor integrated circuit device according to the present invention, a memory cell is constituted by a memory cell selecting MISFET and an information storage capacitor connected in series to the MISFET. For the memory cell selection M
A method for manufacturing a semiconductor integrated circuit device having a DRAM disposed above an ISFET, comprising: (a) forming a MISFET for selecting a memory cell in a memory array on a main surface of a semiconductor substrate; (B) depositing a first insulating film having a thickness corresponding to the height of an information storage capacitor formed in a later step, on the memory cell selecting MISFET and the MISFET of the peripheral circuit; (C) opening the first insulating film of the memory array by etching using a photoresist film as a mask to form a groove, and forming the first insulating film at the boundary between the memory array and the peripheral circuit region. Forming a long groove surrounding the memory array, and opening the insulating film in another region of the semiconductor substrate, the second groove having a larger area than the groove and the long groove; Forming a groove in the upper part of the first insulating film including the inside of the groove and the longitudinal groove (d),
Depositing a first conductive film constituting a lower electrode of the information storage capacitor, and then depositing a second insulating film filling the groove and the long groove on the first conductive film; 2) etching back the insulating film and the first conductive film above the first insulating film to leave the first conductive film only inside the groove and the long groove; A cylinder having an opening above by etching the first insulating film and the second insulating film inside the groove in the gap between the groove and the groove adjacent to the groove using the photoresist film as a mask as a mask (G) forming a third insulating film and a second
After depositing a conductive film, the second conductive film and the second insulating film are patterned to form a lower electrode made of the first conductive film, a capacitor insulating film made of the third insulating film, (E) forming an information storage capacitive element composed of an upper electrode made of a conductive film.
When etching back the second insulating film and the first conductive film on the first insulating film in a process, the upper portion of the second groove is covered with a photoresist film.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the second groove is an alignment mark or a TEG pattern.

(3) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the first insulating film is a silicon oxide film, and the second insulating film is an SOG film.

(4) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the first conductive film is a polycrystalline silicon film.

(5) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the etching in the step (f) is wet etching.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM of the present embodiment is formed. As shown in the drawing, the main surface of the semiconductor chip 1A made of single crystal silicon has X
A large number of memory arrays MARY are arranged in a matrix along the direction (the long side direction of the semiconductor chip 1A) and the Y direction (the short side direction of the semiconductor chip 1A). A sense amplifier SA is arranged between memory arrays MARY adjacent to each other along the X direction. In the center of the main surface of the semiconductor chip 1A, control circuits such as a word driver WD and a data line selection circuit, input / output circuits, and bonding pads are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM. As shown, the memory array of this DRAM (MA
RY) includes a plurality of word lines W arranged in a matrix.
L (WLn-1, WLn, WLn + 1...), A plurality of bit lines BL, and a plurality of memory cells (MC) arranged at their intersections. One memory cell for storing one bit of information is composed of one information storage capacitor C
And one memory cell selecting MI connected in series
SFET Qs. M for memory cell selection
One of a source and a drain of the ISFET Qs is electrically connected to the information storage capacitor C, and the other is a bit line BL.
Is electrically connected to One end of the word line WL is connected to a word driver WD, and one end of the bit line BL is
It is connected to the sense amplifier SA.

Next, a method of manufacturing the DRAM of this embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 3, a p-type semiconductor substrate 1 having a specific resistance of about 10 Ωcm is wet-oxidized at about 850 ° C. to form a thin silicon oxide film 2 having a thickness of about 10 nm on its surface. CV is formed on the silicon oxide film 2
A silicon nitride film 3 having a thickness of about 140 nm is deposited by a D (Chemical Vapor Deposition) method. Silicon oxide film 2
Is formed to alleviate the stress applied to the substrate when sintering (burning) a silicon oxide film embedded in the element isolation groove in a later step. Since the silicon nitride film 3 has the property of being hardly oxidized, it is used as a mask for preventing the oxidation of the substrate surface below (the active region).

Next, as shown in FIG. 4, the silicon nitride film 3, the silicon oxide film 2 and the semiconductor substrate 1 are dry-etched using the photoresist film 4 as a mask, so that the semiconductor substrate 1 in the element isolation region is deeply etched. 300-400
A groove 5a of about nm is formed. In order to form the groove 5a, the silicon nitride film 3 is dry-etched using the photoresist film 4 as a mask, the photoresist film 4 is removed, and then the silicon oxide film 2 and the semiconductor substrate are etched using the silicon nitride film 3 as a mask. 1 may be dry-etched.

Next, after removing the photoresist film 4,
As shown in FIG. 5, in order to remove a damaged layer formed on the inner wall of the groove 5a by the above-described etching, the semiconductor substrate 1 is wet-oxidized at about 850 to 900 ° C. and the inner wall of the groove 5a has a film thickness of about 10 nm. A thin silicon oxide film 6 is formed.

Next, as shown in FIG. 6, after a silicon oxide film 7 having a thickness of about 300 to 400 nm is deposited on the semiconductor substrate 1, the semiconductor substrate 1 is dry-oxidized at about 1000.degree. Silicon oxide film 7 embedded in
(Sintering) is performed to improve the film quality. The silicon oxide film 7 is deposited by, for example, a thermal CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 7, a silicon nitride film 8 having a thickness of about 100 nm is deposited on the silicon oxide film 7 by the CVD method, and then, as shown in FIG. Then, the silicon nitride film 8 is dry-etched to leave the silicon nitride film 8 only on the upper portion of the groove 5a having a relatively large area such as the boundary between the memory array and the peripheral circuit. When the silicon nitride film 8 remaining on the groove 5a is planarized by polishing the silicon oxide film 7 by a CMP method in the next step, the silicon oxide film 7 inside the groove 5a having a relatively large area is removed. It is formed in order to prevent a phenomenon (dishing) that is polished deeper than the silicon oxide film 7 inside the groove 5a having a relatively small area.

Next, after removing the photoresist film 9,
As shown in FIG. 9, the element isolation groove 5 is formed by polishing the silicon oxide film 7 by a CMP method using the silicon nitride films 3 and 8 as stoppers and leaving the silicon oxide film 7 inside the groove 5a.

Next, after removing the silicon nitride films 3 and 8 by wet etching using hot phosphoric acid, as shown in FIG. 10, an n-type semiconductor substrate 1 in a region (memory array) where a memory cell is to be formed is formed. An n-type semiconductor region 10 is formed by ion-implanting an impurity, for example, P (phosphorus), and a p-type impurity, for example, B (boron) is added to a part of the memory array and peripheral circuits (a region for forming an n-channel MISFET). The p-type well 11 is formed by ion implantation, and n is formed in another part of the peripheral circuit (the region where the p-channel MISFET is formed).
An n-type well 12 is formed by ion implantation of a type impurity, for example, P (phosphorus). Subsequent to the ion implantation, impurities for adjusting the threshold voltage of the MISFET, for example, BF ₂ (boron fluoride) are ion-implanted into the p-type well 11 and the n-type well 12. The n-type semiconductor region 10 is formed to prevent noise from entering the p-type well 11 of the memory array from the input / output circuit and the like through the semiconductor substrate 1.

Next, the p-type well 11 and the n-type well 1
After removing the silicon oxide film 2 on each surface of the semiconductor substrate 1 using a HF (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is wet-oxidized at about 850 ° C. to form a p-type well 11 and an n-type well 1.
Then, a clean gate oxide film 13 having a thickness of about 7 nm is formed on each surface of No. 2.

Although not particularly limited, after the gate oxide film 13 is formed, the semiconductor substrate 1 is subjected to a heat treatment in an NO (nitrogen oxide) atmosphere or an N ₂ O (nitrogen oxide) atmosphere to thereby form the gate oxide film. Nitrogen may be segregated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 (oxynitriding treatment). When the thickness of the gate oxide film 13 is reduced to about 7 nm, distortion generated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 due to a difference in thermal expansion coefficient becomes apparent, and hot carriers are generated. Nitrogen segregated at the interface with the semiconductor substrate 1 relaxes this distortion.
The above oxynitriding process can improve the reliability of the ultra-thin gate oxide film 13.

Next, as shown in FIG. 11, gate electrodes 14A, 14B and 14C are formed on the gate oxide film 13. The gate electrode 14A is provided with a memory cell selecting MISF.
It forms a part of the ET, and is used as a word line WL in a region other than the active region. The width of the gate electrode 14A (word line WL), that is, the gate length is the minimum dimension (for example, within an allowable range) in which the short channel effect of the memory cell selecting MISFET can be suppressed and the threshold voltage can be secured to a certain value or more. (About 0.24 μm). The distance between the adjacent gate electrodes 14A (word lines WL) is the minimum dimension (for example, 0.2) determined by the resolution limit of photolithography.
2 μm). The gate electrode 14B and the gate electrode 14C constitute each part of the n-channel MISFET and the p-channel MISFET of the peripheral circuit.

For the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C, a polycrystalline silicon film having a thickness of about 70 nm doped with an n-type impurity such as P (phosphorus) is formed on the semiconductor substrate 1 by the CVD method. Then, a WN (tungsten nitride) film having a thickness of about 50 nm and a W film having a thickness of about 100 nm are deposited thereon by sputtering, and a silicon nitride film 15 having a thickness of about 150 nm is further formed thereon by CVD. After deposition by a method, these films are formed by patterning these films using the photoresist film 16 as a mask. The WN film functions as a barrier layer that prevents the W film and the polycrystalline silicon film from reacting during the high-temperature heat treatment to form a high-resistance silicide layer at the interface between them. As the barrier layer, a TiN (titanium nitride) film or the like can be used in addition to the WN film.

When a part of the gate electrode 14A (word line WL) is made of low-resistance metal (W), its sheet resistance can be reduced to about 2 to 2.5 Ω / □, so that the word line delay is reduced. Can be reduced. Also, the gate electrode 1
Since the word line delay can be reduced without backing 4 (word line WL) with an Al wiring or the like, the number of wiring layers formed above the memory cells can be reduced by one.

Next, after removing the photoresist film 16, the semiconductor substrate 1 is etched using an etching solution such as hydrofluoric acid.
Dry etching residues and photoresist residues remaining on the surface of the substrate are removed. When this wet etching is performed, the gate oxide film 13 in a region other than the region under the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C is formed.
At the same time that the gate oxide film 1 under the gate sidewall is removed.
3 is also isotropically etched and an undercut occurs, so that the breakdown voltage of the gate oxide film 13 is reduced as it is. Therefore, the film quality of the shaved gate oxide film 13 is improved by wet oxidizing the semiconductor substrate 1 at about 900 ° C.

Next, as shown in FIG.
A p ^- type semiconductor region 17 is formed in the n-type well 12 on both sides of the gate electrode 14C by ion implantation of a p-type impurity, for example, B (boron) into the gate electrode 14C. In addition, the p-type well 11 has n
An n ^- type semiconductor region 18 is formed in the p-type well 11 on both sides of the gate electrode 14B by ion-implanting a p-type impurity, for example, P (phosphorus), and an n ^- type semiconductor region 19 is formed in the p-type well 11 on both sides of the gate electrode 14A. To form As a result, the memory cell selecting MISFET Qs is formed in the memory array.

Next, as shown in FIG.
After a silicon nitride film 20 having a thickness of about 50 to 100 nm is deposited thereon by the CVD method, the silicon nitride film 20 of the memory array is covered with a photoresist film 21 as shown in FIG. Is anisotropically etched to form sidewall spacers 20a on the side walls of the gate electrodes 14B and 14C. In this etching, an etching gas that increases the etching rate of the silicon nitride film 20 with respect to the silicon oxide film is used in order to minimize the shaving amount of the silicon oxide film 7 buried in the gate oxide film 13 and the element isolation trench 5. Use to do.
The silicon nitride film 1 on the gate electrodes 14B and 14C
In order to minimize the shaving amount of No. 5, the amount of over-etching is kept to a necessary minimum.

Next, after the photoresist film 21 is removed, as shown in FIG. 15, the n-type well 1 in the peripheral circuit region is formed.
2 is ion-implanted with a p-type impurity, for example, B (boron) to form ap ⁺ -type semiconductor region 2 of a p-channel MISFET.
2 (source, drain) are formed, and an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 11 in the peripheral circuit region to form an n ⁺ -type semiconductor region 23 (source, drain) of the n-channel MISFET. Form. Thus, the p-channel MISFET Qp having the LDD (Lightly Doped Drain) structure and the n-channel M
ISFET Qn is formed.

Next, as shown in FIG.
After spin-coating a SOG (spin-on-glass) film 24 having a thickness of about 300 nm on the upper surface,
The heat treatment is performed for about a minute, and the SOG film 24 is sintered (sintered).

Next, as shown in FIG.
After a silicon oxide film 25 having a thickness of about 600 nm is deposited on the upper surface of the silicon oxide film 25, the silicon oxide film 25 is polished by a CMP method to flatten the surface. The silicon oxide film 25 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

As described above, in this embodiment, the gate electrode 14A (word line WL) and the gate electrodes 14B,
SOG film 24 with good flatness even immediately after film formation on top of 4C
Is applied, and a silicon oxide film 2 deposited on the
5 is flattened by a CMP method. Thereby, the gate electrode 1
4A (word line WL) improves the gap fill property of a minute gap between the gate electrodes 14A (word line WL).
L) and planarization of the insulating film on the gate electrodes 14B and 14C can be realized.

Next, as shown in FIG. 18, a silicon oxide film 26 having a thickness of about 100 nm is formed on the silicon oxide film 25.
Is deposited. The silicon oxide film 26 is deposited in order to repair fine scratches on the surface of the silicon oxide film 25 generated when the silicon oxide film 25 is polished by the CMP method. Silicon oxide film 2
6 is deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. On top of the silicon oxide film 25, a PSG (Phospho Silicate Glas
s) A film or the like may be deposited.

Next, as shown in FIG. 19, the silicon oxide films 26 and 25 on the n-type semiconductor region 19 (source and drain) of the MISFET Qs for memory cell selection are dry-etched using the photoresist film 27 as a mask. The SOG film 24 is removed. This etching is performed under such a condition that the etching rates of the silicon oxide films 26 and 25 and the SOG film 24 with respect to the silicon nitride film 20 are increased, and the silicon nitride film covering the n-type semiconductor region 19 and the upper part of the element isolation trench 5 is formed. 20 is not completely removed.

Subsequently, as shown in FIG. 20, the n-type semiconductor region 19 of the MISFET Qs for selecting a memory cell is dry-etched using the photoresist film 27 as a mask.
By removing the silicon nitride film 15 and the gate oxide film 13 above the (source, drain), a contact hole 28 is formed in one upper part of the n-type semiconductor region 19 (source, drain) and in the other upper part. Contact hole 2
9 is formed.

This etching is performed under such conditions that the etching rate of the silicon nitride film 20 with respect to the silicon oxide film (the gate oxide film 13 and the silicon oxide film 7 in the element isolation trench 5) is increased. The element isolation groove 5 is prevented from being cut deeply. This etching is performed under such conditions that the silicon nitride film 20 is anisotropically etched, and the gate electrode 14A (word line W
The silicon nitride film 20 is left on the side wall of L). As a result, the contact holes 28 and 29 having a fine diameter smaller than the resolution limit of photolithography are formed in the gate electrode 1.
4A (word line WL) is formed in a self-aligned manner.
In order to form the contact holes 28 and 29 in a self-aligned manner with respect to the gate electrode 14A (word line WL), the silicon nitride film 20 is anisotropically etched in advance to form a sidewall on the side wall of the gate electrode 14A (word line WL). A spacer may be formed.

Next, after removing the photoresist film 27, dry etching residues and photoresist residues on the substrate surface exposed at the bottoms of the contact holes 28 and 29 are etched using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. And so on. At that time, the contact hole 28,
The SOG film 24 exposed on the side wall of the S.sub.29 is also exposed to the etching solution. However, the SOG film 24 has a reduced etching rate with respect to a hydrofluoric acid-based etching solution by the above-described sintering at about 800.degree. The sidewalls of the contact holes 28 and 29 are not largely undercut by the etching process. As a result, it is possible to reliably prevent a short circuit between plugs embedded in the contact holes 28 and 29 in the next step.

Next, as shown in FIG. 21, plugs 30 are formed inside the contact holes 28 and 29. The plug 30 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 26 by CVD.
After the deposition by the method, the polycrystalline silicon film is polished by the CMP method and is formed by being left inside the contact holes 28 and 29.

Next, as shown in FIG. 22, a silicon oxide film 31 having a thickness of about 200 nm is formed on the silicon oxide film 26.
Is deposited, the semiconductor substrate 1 is heat-treated at about 800 ° C. The silicon oxide film 31 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. By this heat treatment,
An n-type impurity in the polycrystalline silicon film forming the plug 30 is supplied from the bottom of the contact holes 28 and 29 to the n-type semiconductor region 19 (source,
Drain) and the resistance of the n-type semiconductor region 19 is reduced.

Next, as shown in FIG. 23, the silicon oxide film 31 above the contact hole 28 is removed by dry etching using the photoresist film 32 as a mask to expose the surface of the plug 30. Next, after removing the photoresist film 32, as shown in FIG. 24, the silicon oxide films 31, 26, 25 and the SOG film 24 in the peripheral circuit region are dry-etched using the photoresist film 33 as a mask.
By removing the gate oxide film 13 and contact holes 34 and 35 above the n ⁺ -type semiconductor region 23 (source and drain) of the n-channel MISFET Qn, the p ⁺ -type semiconductor region 22 of the p-channel MISFET Qp Contact holes 36 and 37 are formed above (source, drain).

Next, after removing the photoresist film 33, as shown in FIG. 25, the bit lines BL and the first layer wirings 38 and 39 of the peripheral circuit are formed on the silicon oxide film 31. In order to form the bit line BL and the first layer wirings 38 and 39, first, a film thickness 5
A Ti film of about 0 nm is deposited by a sputtering method, and the semiconductor substrate 1 is heat-treated at about 800 ° C. Next, a TiN film having a thickness of about 50 nm is deposited on the Ti film by a sputtering method, and a W film having a thickness of about 150 nm and a silicon nitride film 40 having a thickness of about 200 nm are further deposited thereon by a CVD method. These films are patterned using the photoresist film 41 as a mask.

After a Ti film is deposited on the silicon oxide film 31, the semiconductor substrate 1 is heat-treated at about 800 ° C., so that the Ti film reacts with the Si substrate and the n-channel type M
A low-resistance TiSi ₂ (titanium silicide) layer 42 is formed on the surface of the n ⁺ type semiconductor region 23 (source, drain) of the ISFET Qn and the surface of the p ⁺ type semiconductor region 22 (source, drain) of the p-channel MISFET Qp. You. Although not shown, the memory cell selection M
The surface of the plug 30 buried in the contact hole 28 above the n-type semiconductor region 19 of the ISFET Qs
An Si ₂ layer 42 is formed.

Thus, the wiring (bit line B) connected to n ⁺ type semiconductor region 23 and p ⁺ type semiconductor region 22 is formed.
L, the contact resistance of the first layer wirings 38, 39) can be reduced. Further, by forming the bit line BL with a W film / TiN film / Ti film, the sheet resistance is reduced to 2Ω.
/ □ or less, so that the information reading speed and the writing speed can be improved, and the bit line BL and the first layer wirings 38 and 39 of the peripheral circuit can be formed simultaneously in one step. Therefore, the manufacturing process of the DRAM can be shortened. Further, when the first layer wirings (38, 39) of the peripheral circuit are formed of the same layer as the bit line BL, the peripheral wiring is more peripheral than the case where the first layer wiring is formed of the upper layer Al wiring of the memory cell. MISFE of circuit
T (n-channel MISFET Qn, p-channel MI
Since the aspect ratio of the contact holes (34 to 37) connecting the SFET Qp) and the first layer wiring is reduced,
The connection reliability of the first layer wiring is improved.

The bit line BL is used to reduce the parasitic capacitance formed between the bit line BL and the adjacent bit line BL as much as possible to improve the information reading speed and the writing speed.
The gap is formed so as to be longer than the width. The interval between the bit lines BL is, for example, about 0.24 μm, and the width thereof is, for example, about 0.22 μm.

Next, after removing the photoresist film 41, as shown in FIG. 26, side wall spacers 43 are formed on the side walls of the bit lines BL and the side walls of the first layer wirings 38 and 39.
To form The side wall spacer 43 is formed by depositing a silicon nitride film on the bit line BL and the first layer wirings 38 and 39 by the CVD method, and then anisotropically etching the silicon nitride film.

Next, as shown in FIG.
Then, an SOG film 44 having a thickness of about 300 nm is spin-coated on the first layer wirings 38 and 39. Next, the semiconductor substrate 1 is heat-treated at 800 ° C. for about 1 minute to sinter (bake) the SOG film 44.

Since the SOG film 44 has a higher reflow property than the BPSG film and is excellent in the gap fill property between fine wirings, the gap between the bit lines BL miniaturized to the resolution limit of the photolithography. Can be satisfactorily embedded. In addition, since the SOG film 44 can obtain high reflow properties without performing a high-temperature and long-time heat treatment required for the BPSG film, the source and drain of the memory cell selection MISFET Qs formed under the bit line BL are formed. And MISFETs for peripheral circuits (n-channel MISFE
TQn, the p-channel type MISFET Qp) can suppress the thermal diffusion of the impurities contained in the source and drain, and can achieve a shallow junction. Further, since the deterioration of the metal (W film) forming the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C can be suppressed, the performance of the MISFET forming the memory cell and the peripheral circuit of the DRAM can be improved. Can be. Further, a Ti film, a TiN film, and a W film constituting the bit line BL and the first layer wirings 38 and 39 are formed.
Wiring resistance can be reduced by suppressing film deterioration.

Next, as shown in FIG.
After a silicon oxide film 45 having a thickness of about 600 nm is deposited on the upper surface of the substrate, the silicon oxide film 45 is polished by a CMP method to flatten the surface. The silicon oxide film 45 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

As described above, in this embodiment, the SOG film 44 having good flatness is applied to the bit line BL and the first layer wirings 38 and 39 immediately after the film formation, and the oxidation The silicon film 45 is planarized by the CMP method. Thereby, the gap fill property of the minute gap between the bit lines BL is improved, and the flattening of the insulating film on the bit lines BL and the first layer wirings 38 and 39 can be realized. Further, since heat treatment at a high temperature for a long time is not performed, the MISFE forming the memory cell and the peripheral circuit is not required.
It is possible to achieve high performance by preventing the characteristic deterioration of T, and to reduce the resistance of the bit line BL and the first layer wirings 38 and 39.

Next, as shown in FIG. 29, a silicon oxide film 46 having a thickness of about 100 nm is formed on the silicon oxide film 45.
Is deposited. The silicon oxide film 46 is deposited to repair fine scratches on the surface of the silicon oxide film 45 generated when the silicon oxide film 45 is polished by the CMP method. Silicon oxide film 4
6 is deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 30, the silicon oxide films 46 and 45 over the contact holes 29 are removed by dry etching using the photoresist film 47 as a mask.
After removing the film 44 and the silicon oxide film 31, the plug 30
Is formed to reach the surface of the substrate. This etching is performed on the silicon oxide films 46, 45, 31 and SO
The etching is performed under such a condition that the etching rate of the silicon nitride film with respect to the G film 44 becomes small.
To prevent the silicon nitride film 40 and the sidewall spacers 43 on the upper portion from being etched deeply. As a result, the through hole 48 is formed in self alignment with the bit line BL.

Next, after removing the photoresist film 47, a dry etching residue or a photoresist residue on the surface of the plug 30 exposed at the bottom of the through hole 48 is etched using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. And so on. At this time, the SOG film 44 exposed on the side wall of the through hole 48 is also exposed to the etching solution.
Since the etching rate of the OG film 44 with respect to the hydrofluoric acid-based etchant is reduced by the sintering at about 800 ° C., the side wall of the through hole 48 is not largely undercut by the wet etching process. Accordingly, a short circuit between the plug buried in the through hole 48 and the bit line BL in the next step can be reliably prevented. Also, since the plug and the bit line BL can be sufficiently separated from each other,
An increase in the parasitic capacitance of the bit line BL can be suppressed.

Next, as shown in FIG. 31, a plug 49 is formed inside the through hole 48. The plug 49 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 46 by a CVD method, and then etching back the polycrystalline silicon film to form a through hole 48. It is formed by leaving it inside.

Next, as shown in FIG. 32, a silicon nitride film 51 having a thickness of about 100 nm is formed on the silicon oxide film 46.
Is deposited by the CVD method, and the silicon nitride film 51 in the peripheral circuit region is removed by dry etching using the photoresist film 52 as a mask. The silicon nitride film 51 remaining in the memory array is used as an etching stopper when etching a silicon oxide film between the lower electrodes in a step of forming a lower electrode of the information storage capacitor element described later.

Next, after removing the photoresist film 52, as shown in FIG. 33, for example, ozone (O ₃ ) and tetraethoxysilane (T
A silicon oxide film 53 having a thickness of about 1.3 μm is deposited by a plasma CVD method using EOS) as a source gas, and the silicon oxide film 53 and the silicon nitride film 51 are removed by dry etching using a photoresist film 54 as a mask. As a result, a deep groove 55 is formed above the through hole 48 in which the plug 49 is embedded, and a frame-shaped deep long groove 59 surrounding the memory array is formed around the memory array.

FIG. 34 is a plan view of a main portion of a photomask (reticle) 70 used for transferring the pattern of the groove 55 and the pattern of the long groove 59 to the photoresist film 54.

In the center of the photomask 70 (the area corresponding to the memory array), light-shielding patterns 55A corresponding to the grooves 55 are formed in a lattice pattern at a rate of one per memory cell. Outside the group of light-shielding patterns 55A (the area corresponding to the boundary between the memory array and the peripheral circuit area), a frame-shaped light-shielding pattern 59A corresponding to the long groove 59 is arranged so as to surround the group of light-shielding patterns 55A. Have been.

In another area of the photomask 70, an alignment mark AM used for alignment with the semiconductor substrate 1 is formed. In a region (not shown) of the photomask 70, a TEG pattern is formed.
These alignment marks AM and TEG patterns are
The light-shielding pattern 55A corresponding to the groove 55 and the light-shielding pattern 59A having a larger area than the light-shielding pattern 59A corresponding to the long groove 59 are configured. Therefore, when the silicon oxide film 53 is dry-etched using the photoresist film 54 as a mask, as shown in FIG. 35, the silicon oxide film 53 has large-area deep grooves 80 corresponding to these large-area patterns simultaneously. It is formed.

Next, after removing the photoresist film 54, as shown in FIGS. 36 and 37, an n-type impurity (for example, P (phosphorus)) is doped on the silicon oxide film 53 to a thickness of about 60 nm. A polycrystalline silicon film 56 is deposited by a CVD method. This polycrystalline silicon film 56 is used as a lower electrode material of the information storage capacitor.

Next, as shown in FIG. 38, after an SOG film 57 having a thickness (for example, about 300 to 400 nm) sufficient to bury the groove 55 and the long groove 59 is deposited on the polycrystalline silicon film 56, SOG film 5 by heat treatment at about 400 ° C.
Bake 7. At this time, as shown in FIG. 39, since the area of the groove 80 corresponding to the above-described alignment mark AM or TEG pattern is sufficiently larger than that of the groove 55 or the long groove 59, the SOG film 57 is completely contained therein. Is not embedded.

Next, as shown in FIG.
Is etched back to expose the polycrystalline silicon film 56 above the silicon oxide film 53, and then the polycrystalline silicon film 56 is etched back to form polycrystalline silicon on the inside (inner wall and bottom) of the groove 55 and the long groove 59. Crystalline silicon film 5
Leave 6. At this time, in the present embodiment, as shown in FIG.
Is formed, and the SOG film 57 and the polycrystalline silicon film 55 are etched back. As a result, as shown in FIG. 11, the SOG film 57 remains in the trench 80 covered with the photoresist film 81 without being substantially removed. On the other hand, when the above-described etchback is performed without forming the photoresist film 81 on the groove 80, as shown in FIG.
Since the central portion of the groove 80 having a small thickness of the SOG film 57 is deeply ground, even the polycrystalline silicon film 56 at the bottom of the groove 80 is also ground, exposing the surface of the silicon oxide film 46 therebelow. . Therefore, the polycrystalline silicon film 56 at the bottom of the groove 80 is peeled and scattered in a later wet etching step or the like, and becomes a foreign substance.

Next, the photoresist film 8 above the groove 80
After removing 1, as shown in FIG. 43, the silicon oxide film 53 in the peripheral circuit region is covered with a photoresist film 58, and the SOG film 57 and the groove 55 inside the groove 55 are etched using a hydrofluoric acid-based etchant. The lower electrode 60 of the information storage capacitor is formed by wet etching the silicon oxide film 53 in the gap. At this time, since the silicon nitride film 51 is formed at the bottom of the gap of the groove 55, even if the silicon oxide film 53 is entirely removed, the silicon oxide film 46 thereunder is not shaved by the etchant.

One end of the photoresist film 58 covering the silicon oxide film 53 in the peripheral circuit region is arranged at the boundary between the memory array and the peripheral circuit region, that is, above the long groove 59. Therefore, when the above-mentioned wet etching is performed, the SOG film 57 inside the long groove 59 is also removed, but the lower electrode material (polycrystalline silicon film 56) on the inner wall of the long groove 59 serves as an etching stopper.
No side wall is cut off. Further, since the surface of the silicon oxide film 53 in the peripheral circuit region is covered with the photoresist film 58, the surface is not scraped.
As a result, the step between the memory array and the peripheral circuit is eliminated, and the peripheral circuit region is also flattened.

Next, the photoresist film 58 covering the peripheral circuit region is removed, and then, in order to prevent oxidation of the polycrystalline silicon film (56) constituting the lower electrode 60, the semiconductor substrate 1 is placed in an ammonia atmosphere at 800 After nitriding the surface of the polycrystalline silicon film (56) by heat treatment at about
As shown in FIG. 7, a Ta ₂ O ₅ (tantalum oxide) film 61 having a thickness of about 20 nm is deposited on the lower electrode 60 by CVD.
Then the semiconductor substrate 1 is heat treated at about 800 ° C. Ta ₂
The defect of the O ₅ film 61 is repaired. This Ta ₂ O ₅ film 61
Is used as a material for a capacitive insulating film of an information storage capacitor.

Next, as shown in FIG. 45, the Ta ₂ O ₅ film 61 is formed on the Ta ₂ O ₅ film 61 by a CVD method and a sputtering method.
After depositing a TiN film 62 of about 0 nm, the TiN film 62 is dry-etched using the photoresist film 63 as a mask.
And by patterning the the Ta ₂ O ₅ film 61, and an upper electrode made of TiN film 62, the Ta ₂ O ₅ film 6
1 is formed, and an information storage capacitance element C composed of a lower electrode 60 made of a polycrystalline silicon film 56 is formed. Thereby, the MISFET for memory cell selection
A DRAM memory cell composed of Qs and an information storage capacitor C connected in series thereto is completed.

Thereafter, although not shown, about two layers of A are formed above the information storage capacitive element C with an interlayer insulating film interposed therebetween.
By forming the l (aluminum) wiring, the DRAM of the present embodiment is substantially completed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, the lower electrode material is not limited to a polycrystalline silicon film, but may be a metal film or the like. Further, the present invention can be applied to an LSI or the like in which a logic LSI and a DRAM are mounted.

[0079]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the method of manufacturing a DRAM according to the present invention, when the lower electrode of the information storage capacitor element is formed, the defect that the lower electrode material at the bottom of the large-area groove formed in the thick insulating film is peeled off. DRAM can be prevented
Can improve the production yield.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to an embodiment of the present invention is formed.

FIG. 2 is an equivalent circuit diagram of a DRAM according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 22 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 32 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 34 is a plan view of a main part of a photomask (reticle) used in an embodiment of the present invention.

FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 36 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 37 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 38 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 39 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 40 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 41 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 42 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a DRAM studied by the present inventors.

FIG. 43 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 44 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 45 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 1A semiconductor chip 2 silicon oxide film 3 silicon nitride film 4 photoresist film 5 element isolation groove 5a groove 6 silicon oxide film 7 silicon oxide film 8 silicon nitride film 9 photoresist film 10 n-type semiconductor region 11 p-type well 12 n-type well 13 gate oxide film 14A to 14C gate electrode 15 silicon nitride film 16 photoresist film 17 p ^- type semiconductor region 18 n ^- type semiconductor region 19 n-type semiconductor region 20 silicon nitride film 20a sidewall spacer 21 photoresist film 22 p ⁺ type semiconductor region 23 n ⁺ type semiconductor region 24 SOG film 24 a, 24 b SOG film 25 silicon oxide film 26 silicon oxide film 27 photoresist film 28 contact hole 29 contact hole 30 plug 31 silicon oxide film 32 photoresist Strike film 33 photoresist film 34-37 contact hole 38, 39 first layer wiring 40 silicon nitride film 41 photoresist film 42 TiSi ₂ layer 43 sidewall spacer 44 SOG film 45 silicon oxide film 46 silicon oxide film 47 photoresist film 48 Through hole 49 Plug 51 Silicon nitride film 52 Photo resist film 53 Silicon oxide film 54 Photo resist film 55 Groove 55A Light shielding pattern 56 Polycrystalline silicon film 57 SOG film 58 Photo resist film 59 Long groove 59A Light shielding pattern 60 Lower electrode 61 Ta ₂ O ₅ (Tantalum oxide) film 62 TiN film (upper electrode) 63 Photoresist film 64 Silicon oxide film 65 Photoresist film 66 Through hole 67 Plug 68, 69 Second layer wiring 70 Photomask (reticle) 71 silicon oxide film 72 SOG film 73 silicon oxide film 74, 75 through hole 76 plug 77 to 79 third layer wiring 80 groove AM alignment mark BL bit line C information storage capacitor MARY memory array Qn n-channel MISFET Qp p-channel MISFET Qs MISFET for memory cell selection SA Sense amplifier WD Word driver

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Akira Imai 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. 20-1 chome Semiconductor Division, Hitachi, Ltd.

Claims (5)

[Claims] 1. A DRAM comprising a memory cell selection MISFET and an information storage capacitance element connected in series with the MISFET, wherein the information storage capacitance element is disposed above the memory cell selection MISFET. And (a) a memory cell selecting MISFET in a memory array on a main surface of a semiconductor substrate.
Forming a MISFET of a peripheral circuit in a peripheral circuit region, and (b) the MISFET for selecting a memory cell.
And depositing a first insulating film having a thickness corresponding to the height of an information storage capacitor formed in a later step on the MISFET of the peripheral circuit, and (c) using the photoresist film as a mask. Forming a groove by opening the first insulating film of the memory array by performing the etching, and forming a long groove surrounding the memory array by opening the first insulating film at the boundary between the memory array and the peripheral circuit region; Forming a second groove having an area larger than that of the groove and the long groove by opening the insulating film in another region of the semiconductor substrate; and (d) including the inside of the groove and the long groove. On top of the first insulating film,
Depositing a first conductive film constituting a lower electrode of the information storage capacitor, and then depositing a second insulating film filling the groove and the long groove on the first conductive film; 2) etching back the insulating film and the first conductive film above the first insulating film to leave the first conductive film only inside the groove and the long groove; A cylinder having an opening above by etching the first insulating film and the second insulating film inside the groove in the gap between the groove and the groove adjacent to the groove using the photoresist film as a mask as a mask (G) forming a third insulating film and a second
After depositing a conductive film, the second conductive film and the second insulating film are patterned to form a lower electrode made of the first conductive film, a capacitor insulating film made of the third insulating film, (E) forming an information storage capacitive element composed of an upper electrode made of a conductive film.
A step of etching back the second insulating film and the first conductive film on the first insulating film in a step, covering an upper part of the second groove with a photoresist film. Production method. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said second groove is an alignment mark or a TEG pattern. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film is a silicon oxide film, and said second insulating film is an SOG film. Device manufacturing method. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first conductive film is a polycrystalline silicon film. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the etching in the step (f) is wet etching.