JPH11243332A - Cmos gate circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS gate circuit which reduces output distortions due to capacitive load, also has small power consumption while suppressing an internal through current and is also manufactured inexpensively without changing a conventional manufacturing process. SOLUTION: A 2nd P-channel type MOS transistor 7 and a 2nd N-channel type MOS transistor 8 are added to a gate where the drains of a 1st P-channel type MOS transistor 2 and a 1st N-channel MOS type transistor 3 are connected to each other and both the transistors 7 and 8 are turned on for a prescribed time only at the time of the rise and fall of output signal. Also, a delay gate and a through current inhibit gate are added to the transistors 2 and 3 and the through current is prevented by shifting an off state during delay time 'of the delay gate when both the transistors 2 and 3 alternate on and off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed logic circuit, and more particularly to a CMOS gate circuit which can prevent a through current, consumes low power, and can be realized without changing a manufacturing process.

There is a strong demand for high-speed communication devices and information processing devices in order to increase their communication capacity and improve information processing capability.
Higher speed is also required for the CMOS gate circuit used.

[0003]

FIG. 13 shows a conventional CMOS gate circuit. In FIG. 13, 1 indicates an inverter whose input-to-output polarity is inverted, 2 indicates a P-channel MOS transistor, and 3 indicates an N-channel MOS transistor. Further, one inverter similar to 1 is further constituted by the combination of the P-channel MOS transistor 2 and the N-channel MOS transistor 3. Therefore, FIG.
Reference numeral 3 denotes a non-inverting gate whose input and output polarities match. Reference numeral 14 denotes a stray capacitance when the latter stage is viewed from the data output terminal in FIG.

FIG. 14 is a truth table of the circuit of FIG.
When the data input is 0, the data output is also 0, and when the data input is 1, the data output is 1 accordingly.
FIG. 16 shows a conventional three-state CMOS gate circuit having three states of 0 and 1 and an undefined output (high impedance state) as gate outputs. In FIG. 16, reference numeral 1 denotes an inverter, 2 denotes a P-channel MOS transistor, and 3 denotes an N-channel MOS transistor.
3, the P-channel MOS transistor 2 and the N
One inverter is constituted by the channel type MOS transistor 3. Reference numeral 5 denotes an output inversion logical product circuit, and reference numeral 6 denotes an output inversion logical sum circuit.

In FIG. 16, the data input and the control signal are inverted for each output after the logical product and logical sum operation, and supplied to an inverter composed of the P-channel MOS transistor 2 and the N-channel MOS transistor 3. Is done.

The operation of FIG. 16 is as follows. First, when the control signal is 1, the second input of the AND circuit 5 becomes 0, so that the AND circuit 5 outputs 1. At this time, 1 is supplied to the second input of the OR circuit 6, and the OR circuit 6
Outputs 0.

Therefore, when the control signal is 1, both the P-channel MOS transistor 2 and the N-channel MOS transistor 3 are turned off, and the level of the data output becomes indefinite (high impedance state).

On the other hand, when the control signal is 0, the output of the inverter 1 is fixed at 1, so that the AND circuit 5 inverts the data input, and outputs 1 when the data input is 0, and also outputs 1 when the data input is 0. Outputs 0 when is 1. Also, at this time, since 0 is fixedly supplied to the second input of the OR circuit 6, the circuit 6 also acts to invert the data input and outputs 1 when the data input is 0, and also outputs 1 when the data input is 0. Outputs 0 when is 1.

Therefore, when the control signal is 0, the circuit of FIG. 16 operates as a non-inverting gate. FIG. 17 is a truth table showing the above operation of the configuration of FIG.

[0010]

FIG. 15 is a diagram for explaining the operation of the configuration shown in FIG. First, when the data input changes from 0 to 1, the output of the inverter 1 drops from 1 to 0, the P-channel MOS transistor 2 turns on, and the floating capacitor 14 is charged with the power supply voltage supplied to the source. Changes the data output to 1.

At this time, the on-resistance between the source and the drain of the P-channel MOS transistor 2 is R, and the floating capacitance 14 is
, The data output rises with a charging time constant τ, that is, τ = RC.

On the other hand, when the data input falls from 1 to 0, the output of the inverter 1 rises from 0 to 1, so that the N-channel MOS transistor 3 replaces the P-channel MOS transistor 2 and the floating capacitance is turned on. Discharge 14 charges. If the on-resistance between the source and the drain of the N-channel MOS transistor 3 at this time is R, the data output falls with a time constant τ in the same manner as when the input changes from 0 to 1.

Therefore, in the circuit of FIG.
As a result, waveform distortion occurs at the rise and fall of the data output, causing an output response delay with respect to the data input. Next, FIG. 18 shows the operation when the control signal is 0 in FIG. In FIG. 16, since the control signal is 0, the inverter 1 outputs 1. Therefore, data input is 0
From 1 to 1, the output of the AND circuit 5 (abbreviated as NAND) and the output of the OR circuit 6 (abbreviated as NOR) both change from 1 to 0.

As a result, when the data input changes from 0 to 1, the P-channel MOS transistor 2 is turned on to charge the floating capacitance. Assuming that the on-resistance of the P-channel MOS transistor 2 at this time is R and the capacitance of the stray capacitance 14 is C, the data output becomes a time constant τ
, Which causes an output response delay with respect to the data input as in FIG.

On the other hand, when the data input changes from 1 to 0, both the AND circuit 5 and the OR circuit 6 change from 0 to 1, so that the N-channel MOS transistor 3 is turned on at this time. The floating capacitor 14 is discharged. Assuming that the on-resistance of the N-channel MOS transistor 3 at this time is R, the data output falls with a time constant τ, as in the case where the input changes from 0 to 1. Causes a delay.

As described above, the conventional CMO shown in FIGS.
The first problem of the S gate is a load dependency problem that causes an output response delay due to waveform distortion due to a capacitive load. The output response delay is significantly increased when the gate is used for a buffer output stage of an integrated circuit because of the large stray capacitance distributed to the wiring outside the integrated circuit.

In order to reduce the output response delay caused by the above-mentioned stray capacitance, it is necessary to lower the operating impedance of the gate and to reduce the time constant τ. Therefore, the N-channel type MOS transistor and the P-channel type MOS
There is a method in which the gate width of the transistor is increased or the gate length is reduced to increase the driving capability.

However, the former method increases the chip area of the transistor and hinders high integration, while the latter method causes an increase in leakage current and a decrease in electrostatic breakdown voltage due to miniaturization. Further, in any case, a decrease in the operating impedance of the gate causes an increase in the DC current in the impedance trimming circuit connected to the subsequent stage, thereby increasing power consumption.

Next, as a second problem, the conventional CMOS gate circuit shown in FIGS.
The channel type MOS transistor 2 and the N-channel type MOS transistor 3 are simultaneously instantaneously turned on,
There is a problem called a through current through which an impact current flows.

FIG. 19 is a diagram for explaining a pattern of generation of a through current. FIG. 19 shows the gate input voltages of the P-channel MOS transistor 2 and the N-channel MOS transistor 3, the threshold voltages of the two MOS transistors,
The relationship between the output voltage of the S gate circuit and the through current is shown. Vs is the power supply voltage of the CMOS gate circuit, Vth-P is the threshold voltage point of the P-channel MOS transistor 2,
th-N is a threshold voltage point of the N-channel MOS transistor 3, and t is time.

Both the P-channel MOS transistor 2 and the N-channel MOS transistor 3 shown in FIGS. 13 and 16 receive the output of the inverter 1 in the preceding stage.
The threshold voltage point of the transistor is Vth-P and Vth as shown in FIG.
Different at th-N.

When the output of the inverter 1 is 1, the N-channel MOS transistor 3 is turned off, and
In this case, the P-channel type MOS transistor 2 is turned on, and an ON / OFF action is exclusively performed between the two MOS transistors.

However, in the process of changing the data input, the exclusive function may be temporarily lost as follows.
For example, when the data input in FIG. 13 changes from 0 to 1, the gate input voltage (ie, the output level of the inverter 1) decreases from 1 to 0 in FIG. When the voltage falls below the threshold voltage point Vth-P between the gate and the drain, the transistor 3 is first turned on (period indicated by b in FIG. 19), and then the gate input voltage further decreases and the N-channel MOS transistor 3 When the gate-drain threshold voltage Vth-N or less, the transistor 2 is turned off (period indicated by c in FIG. 19).

That is, the P-channel MOS transistor 2, which has been off with the change of the gate input voltage, first turns on, and the N-channel MOS transistor 3, which has been on, then turns off. Conversely, when the data input of FIG. 13 changes from 1 to 0, the N-channel type M which is turned off in the reverse order in the order corresponding to the periods indicated by c, d, and a in FIG.
OS transistor 3 first turns on, and the P
The exclusive action of both MOS transistors proceeds in the order in which the channel MOS transistors 2 are turned off.

FIG. 20 shows the period from a to d shown in FIG.
3 shows the operating states of the P-channel MOS transistor 2 and the N-channel MOS transistor 3 corresponding to the above. In periods b and d, both the P-channel MOS transistor 2 and the N-channel MOS transistor 3 It turns on.

As described above, when the two MOS transistors are turned on and off alternately in FIG. 13, a period in which the two MOS transistors are turned on is overlapped with the change in the gate input voltage. As a result, in the periods b and d until the output change of the inverter 1 reaches the end point and the exclusive operation of the two MOS transistors is determined, a short-circuit current accompanying the turning on of the two MOS transistors flows. Becomes This is an abnormal current called a through current generated in a data input change process.

The output change time of the inverter 1 is CMOS
Since the through current is small corresponding to the speed of the gate circuit and the through current is instantaneous, the logical operation of the CMOS gate circuit is maintained, but the instantaneous large current flows ineffectively and the waveform distortion of the first problem occurs. As a result, the output change process increases as the output process lengthens, and causes serious troubles such as abnormal heat generation and a parasitic thyristor phenomenon (a phenomenon called latch-up).

Further, the impulsive load fluctuation gives an electric disturbance to a peripheral circuit, and becomes a major factor which hinders high speed and stabilization of the constituent devices. SUMMARY OF THE INVENTION In view of the first problem, an object of the present invention is to provide a low power consumption CMOS gate capable of reducing the influence of stray capacitance without changing a normal manufacturing process.

Further, the present invention has been made in view of the above-mentioned second problem, and has as its object to provide a CMOS gate which can easily prevent a through current without changing a normal manufacturing process.

[0030]

According to the present invention, there is provided a CMOS circuit shown in FIG.
A new second P-channel MOS transistor and a new second N-channel MOS transistor are added to the gate circuit by using a normal circuit element, and the P-channel MOS transistor 2 is turned on to start data output. The changing period is the added second P-channel MOS.
The transistor is also turned on to charge the floating capacitor 14, and the added second N is used during the period when the N-channel MOS transistor 3 is turned on and the data output falls.
The channel type MOS transistor is also turned on and the stray capacitance 1
4 is configured to discharge the electric charge of 4 and ordinary gates are operated in parallel only when the output changes, thereby achieving a high-speed CMOS gate circuit.

According to the principle of the present invention, for example, FIG.
Of the second normal P-channel type M
If the dimensions of the OS transistor and the P-channel MOS transistor 2 and the dimensions of the second normal N-channel MOS transistor and the N-channel MOS transistor 3 are the same, the on-resistance R is reduced to half. , The time constant of the output response delay due to the capacitive load
Can be reduced to

Moreover, the added second P-channel type M
Since the OS transistor and the second N-channel MOS transistor are configured to be turned on only when the data output rises and falls, the sending end and the receiving end between the sending and receiving gates are usually used for high speed operation. Can significantly reduce the steady load current to be consumed in the impedance trimming circuit provided by simply adding a second P-channel MOS transistor and a second N-channel MOS transistor, Each of the P-channel type MOs
Unlike the case where the S transistor 2 and the N-channel MOS transistor 3 are connected in parallel, the response of a normal CMOS gate circuit can be sped up while suppressing a steady increase in power consumption.

Next, the present invention solves the second problem, that is, the through current, by using a delay gate using a normal circuit element in the CMOS gate circuit of FIG. A gate is added to block a through current as follows.

That is, as described above, the through current is generated when both the P-channel MOS transistor 2 and the N-channel MOS transistor 3 are excessively turned on during the process of changing the output of the inverter 1. Therefore, in the present invention, a delay signal corresponding to the output determination time of the inverter 1 is generated by the delay gate,
When the OS transistor turns on or off alternately, the two MOS transistors are turned off during the delay period, and after the delay period when the data input is determined, either of the two MOS transistors is exclusively turned on. In effect, the suppression gate is configured to block through current.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment of the present invention for increasing the speed, in which the present invention is applied to a non-inverting gate.

In FIG. 1, reference numeral 1 denotes an inverter. 2 is a P-channel type MOS transistor, 3 is an N-channel type M transistor
With the OS transistor, the P-channel MOS transistor 2 and the N-channel MOS transistor 3 constitute an inverter. Therefore, the configuration of FIG. 1 is a non-inverting gate.

4 is a delay inverter, 5 is an AND circuit for inverting output, 6 is an OR circuit for inverting output, 7 is a second P-channel MOS transistor to be newly added, and 8 is a second to be newly added. N-channel MOS transistor, 14
Is the stray capacitance when the latter stage is viewed from the output terminal of FIG.

FIG. 1 shows the configuration of FIG. 13 in which the delay inverter 4, the output inversion AND circuit 5, the output inversion OR circuit 6, the second P-channel MOS transistor 7 and the second N The speed is increased by adding a channel type MOS transistor 8.

FIG. 2 is a diagram for explaining the operation of the configuration of FIG.
The operation is as follows. Since a data input and a data input obtained by delaying and inverting the data input by the inverter 4 are supplied to the AND circuit 5, the output of the AND circuit 5 changes from the rise of the data input to the output of the delay inverter 4. It becomes 0 for a certain period until the fall of.

Since the output of the AND circuit 5 is supplied to the gate of the second P-channel type MOS transistor 7, the transistor 7 operates only during the certain period during which the AND circuit 5 outputs 0. Turn on.

On the other hand, during this period, 0 is supplied to the gate of the P-channel MOS transistor 2 and the P-channel MOS transistor 2 is also turned on. Therefore, while the AND circuit 5 is ON, the stray capacitance 1
4 is the P-channel MOS transistor 2 and the second P-type MOS transistor 2.
It is charged by both channel type MOS transistors 7. If the P-channel MOS transistor 2 and the second P-channel MOS transistor 7 have the same dimensions, the on-resistance is R × １ ／ and the rising time constant is reduced to τ ××.

Similarly, since a data input and a data input obtained by delaying and inverting the data input by the delay inverter 4 are supplied to the OR circuit 6, the OR circuit 6 operates at the falling edge of the data input. From the delay inverter 4
Becomes 1 for a certain period until the output rises.

Since the output of the OR circuit 6 is supplied to the gate of the second N-channel MOS transistor 8, the transistor 8 is turned on for a certain period during which the OR circuit 6 outputs 1. become.

During this period, the N-channel type M
1 is supplied to the gate of the OS transistor 3, and
The N-channel MOS transistor 3 is also turned on. Accordingly, while the OR circuit 6 is on, the floating capacitor 14 is discharged by both the N-channel MOS transistor 3 and the second N-channel MOS transistor 8. If the N-channel MOS transistor 3 and the second N-channel MOS transistor 8 have the same dimensions, the on-resistance viewed from the floating capacitance side is R × １ ／, and the falling time constant at this time is R × １ ／. Decreases to τ × １ ／. FIG. 2 shows this pattern by a solid line (circuit of the present invention) and a broken line (conventional circuit) of data output.

Here, the second P-channel MOS transistor 7 and the second N-channel MOS transistor 8
As described above, the average power consumed by the impedance trimming circuit is very small as described above because the power is turned on only at the rise and fall of the data as described above. The speed of the gate circuit is increased.

That is, in a CMOS gate circuit in which the drains of a P-channel MOS transistor and an N-channel MOS transistor are connected to each other, a second P-channel MOS transistor and a second N-channel MOS transistor are newly added.
A transistor is added, and control is performed such that the second N-channel MOS transistor is turned on only when the data output falls, and the P-channel MOS transistor is turned on only when the data output changes.

The ON resistance of the MOS transistor is MO
Since the dimension of the second P-channel MOS transistor 7 and the second N-channel MOS transistor 8 is increased in an allowable range, the response of the configuration of FIG. Speed up.

FIG. 1 shows an additional P-channel type MO.
1 for both S and N channel MOS transistors
Although the number is assumed to be plural, the number may naturally be plural and each number may be different.

FIG. 3 shows a second embodiment of the high speed operation of the present invention, in which the speed of a three-state CMOS gate circuit is increased. In FIG. 3, 1 is an inverter, 2 is a P-channel MOS transistor, 3 is an N-channel MOS transistor, 4 is a delay inverter, 5 is an AND circuit of output inversion, 6 is an OR circuit of output inversion, and 7
3 is a second P-channel MOS transistor, 8 is a second N-channel MOS transistor, 9 is a logical AND circuit of three-input output inversion, 10 is a logical OR circuit of three-input output inversion, and 14 is a circuit of FIG. This is the stray capacitance when the subsequent stage is viewed from the data output terminal in the configuration.

The configuration of FIG. 3 differs from the configuration of FIG. 16 in that the logical product of the delay inverter 4, the second P-channel MOS transistor 7, the second N-channel MOS transistor 8, and the inverted output of the three inputs. The circuit 9 and the OR circuit 10 for inverting the output of the three inputs are added to increase the speed.

FIG. 4 is a diagram for explaining the operation of the configuration shown in FIG. 3 and shows the case where the control signal is 0. The operation is as follows. Since the control signal is 0, the inverter 1 always outputs 1. Therefore, the logical product circuit 5 and the logical sum circuit 6 to which the data input and the inverter 1 are input are provided.
Is an inverted version of the data input.

On the other hand, the delay inverter 4 outputs the data input after delaying and inverting the data input by the delay amount of the delay inverter 4. Therefore, the output of the AND circuit 9 (abbreviated as 3NAND in FIG. 4) of the three-input output inversion supplied with the data input, the output of the inverter 1 and the output of the delay inverter 4 is the data input. It becomes 0 for a certain period from the rising to the falling of the output of the delay inverter 4. Since the output of the AND circuit 9 for inverting the output of the three inputs is supplied to the gate of the second P-channel MOS transistor 7, the output of the second P-channel MOS transistor 7 is inverted. Of the AND circuit 9 is turned on for the certain period of time of 0. At this time, the P-channel type M
Since 0 is also supplied to the gate of the OS transistor 2, the P-channel MOS transistor 2 and the second P-channel MOS transistor 7 output 0 from the three-input inverted AND circuit 9. For a certain period of time. As a result, the impedance seen from the floating capacitor 14 side decreases, and the response of the rising edge of the data output of the configuration of FIG. 3 is faster than that of FIG.

Similarly, the output of the three-input inverted OR circuit 10 (abbreviated as 3NOR in FIG. 4) supplied with the data input, the output of the inverter 1 and the output of the delay inverter 4 is , For a fixed period from the falling edge of the data input to the rising edge of the output of the delay inverter 4.
become. Since the output of the OR circuit 10 of the three-input output inversion is supplied to the gate of the second N-channel MOS transistor 8, the second N-channel MOS transistor 8 performs the three-input output inversion. Of the OR circuit 10 is turned on only for a certain period of time. At this time, since 1 is also supplied to the gate of the N-channel MOS transistor 3, the N-channel MOS transistor 3
And the second N-channel type MOS transistor 8 are simultaneously turned on for a certain period of time when the output of the OR circuit 10 for inverting the output of the three inputs is 1. As a result, the impedance seen from the floating capacitor 14 side is reduced, and the response of the falling edge of the data output of the configuration of FIG. 3 is faster than that of FIG.

FIG. 5 shows a third embodiment of the present invention, in which the speed of a three-state CMOS gate circuit is increased as in FIG. In FIG. 5, 1 is an inverter, 2 is a P-channel MOS transistor, 3 is an N-channel MOS transistor, 5 is an output inversion AND circuit, 6 is an output inversion OR circuit, and 7 is a second P-channel MOS transistor. The transistor 8 is a second N-channel type M
OS transistor, 11 is a delay non-inverter, 12
Is a logical sum circuit, 13 is a logical product circuit, and 14 is a stray capacitance when the latter stage is viewed in the configuration of FIG.

The configuration of FIG. 5 is different from the configuration of FIG.
An inverter 11, the second P-channel MOS transistor 7, the second N-channel MOS transistor 8,
The logical product circuit 13 and the logical sum circuit 12 are added to increase the speed.

FIG. 6 is a diagram for explaining the operation of the configuration of FIG.
The case where the control signal is 0 is shown and the operation is as follows. Since the control signal is 0, the inverter 1
Always outputs 1. Therefore, the output of the AND circuit 5 is obtained by inverting the data input. Also, since the control signal is supplied to the OR circuit 6 as it is, the output of the OR circuit 6 is also the inverted data input.

Accordingly, the OR circuit 12, which is supplied with the output of the delay non-inverter 11 and the output of the AND circuit 5, operates from the rise of the data input to the rise of the output of the delay non-inverter 11. 0 only for a certain period
Is output. Since the output of the OR circuit 12 is supplied to the gate of the second P-channel MOS transistor 7, the second P-channel MOS transistor 7 is turned on only during this fixed period. At this time, the P-channel type MO
Since the S transistor 2 is also on, the P-channel type M
The OS transistor 2 and the second P-channel MOS transistor 7 are simultaneously turned on for a certain period from the rise of the data input to the rise of the output of the delay non-inverter 11. For this reason, the impedance seen from the floating capacitor 14 side decreases, and the time constant at the time of rising of the data output decreases.

Similarly, the AND circuit 13 which is supplied with the output of the delay non-inverter 11 and the output of the OR circuit 6 of the output inversion outputs the output of the delay non-inverter 11 from the falling edge of the data input. 1 is output only for a certain period until the output falls. Since the output of the AND circuit 13 is supplied to the gate of the second N-channel MOS transistor 8, the second N-channel MOS transistor 8 is turned on only during this period. At this time, since the N-channel MOS transistor 3 is also on, the N-channel MOS transistor 3 and the second N-channel MOS transistor 3 are turned on.
The OS transistor 8 is simultaneously turned on for a certain period from the fall of the data input to the fall of the output of the delay non-inverter 11. Therefore, the stray capacitance 14
The impedance seen from the side decreases, and the time constant at the time of falling of the data output decreases.

As described above, the response of the configuration of FIG.
Speedup for the configuration of The configuration of FIG. 5 is obtained by modifying the configuration of FIG. Therefore, it can be understood that there is not a single means for increasing the speed of the three-state CMOS gate circuit.

That is, similarly to FIG. 3, the configuration of FIG. 5 has a configuration in which the drains of the P-channel MOS transistor and the N-channel MOS transistor are connected to each other.
In the state CMOS gate circuit, a second P-channel MOS transistor and a second N-channel MOS transistor are newly added, and the second N-channel MOS transistor is turned on only when the data output falls, Only when the data output rises, the P-channel type M
The configuration is such that the OS transistor is turned on, thereby increasing the speed of the CMOS gate circuit while suppressing an increase in power consumption.

FIG. 7 shows a first embodiment of the through current blocking according to the present invention. 2 is a P-channel type MOS transistor, 3 is an N-channel type MOS transistor, 11 is a delay non-inverter, 5 is an output inversion logical product circuit, and 6 is an output inversion logical sum circuit. Numeral 14 indicates a stray capacitance when the latter stage is viewed from the data output terminal.

FIG. 8 is a diagram for explaining the operation of the configuration of FIG. 7, and the operation is as follows. When the data input rises to 1, the data input and the delay non-inverter 1
Since the logical sum with the data input delayed by 1 is 1 at this point, the output of the inverted OR circuit 6 (abbreviated as NOR output) becomes 0. Thereby, the N-channel MOS transistor 3 is turned off. On the other hand, the logical product of the output of the delay non-inverter 11 and the data input indicates the output of the output inversion logical product circuit 5 at the time corresponding to the delay time of the delay non-inverter 11 (abbreviated as NAND output). ) Becomes 0. Thereby, the P channel type M
The OS transistor 2 is turned on, and the output of the gate circuit becomes 1 corresponding to the data input.

Next, when the data input becomes 0, the output of the AND circuit 5 (the output of the NAND circuit) immediately becomes 1, and
The channel type MOS transistor 2 is turned off. On the other hand,
When the data input becomes 0, the output of the output OR circuit 6 (the output of the NOR circuit) becomes 1 at the time corresponding to the delay time of the delay non-inverter 11. As a result, the N-channel MOS transistor 3 is turned on, and the output of the gate circuit becomes 0 corresponding to the data input.

The above operation is in the following order. FIG.
When the data input rises in order in correspondence with periods B and C shown in FIG.
Is turned off (period B), and then the delay non-inverter 1
The P-channel MOS transistor 2 is turned on in response to the delay of 1 (period C).

At the time of falling of the data input, the P-channel MOS is first turned on in order corresponding to the periods D and A shown in FIG.
The transistor 2 is turned off (period D), and the N-channel MOS transistor 3 is turned on in response to the delay (period A).

That is, during the change period of the data input based on the delay time of the delay non-inverter 11, both the P-channel MOS transistor 2 and the N-channel MOS transistor 3 are turned off so as to pass through. Blocking current.

FIG. 9 shows a second embodiment of the through current blocking according to the present invention, in which the through current blocking of the three-state CMOS gate circuit of FIG. 16 is performed. 1 is an inverter, 2 is a P-channel MOS transistor, 3
Denotes an N-channel type MOS transistor, 11 denotes a delay non-inverter, 5 denotes an output inversion AND circuit, 6 denotes an output inversion OR circuit, and 14 denotes a stray capacitance when a subsequent stage is viewed from the data output terminal.

FIG. 10 is a diagram for explaining the operation of the configuration of FIG. 9 and illustrates the case where the control signal is 0. The operation is as follows, as in the case of FIG. Since the control signal is 0, the inverter 1 always outputs 1, and the output of the AND circuit 5 is obtained by inverting the data input. The control signal is also supplied to the OR circuit 6, and since the control signal is 0, the output of the OR circuit 6 is also the inverted data input.

When the data input rises to 1, the logical sum of the data input and the data input delayed by the delay non-inverter 11 is 1, so that the output of the output OR circuit 6 (the output of 3NOR) is obtained. Is 0). Thereby, the N-channel MOS transistor 3 is turned off. On the other hand, the logical product of the output of the delay non-inverter 11 and the data input indicates the output of the AND circuit 5 whose output is inverted at the time corresponding to the delay time of the delay non-inverter 11 (abbreviated as the output of 3NAND). ) Becomes 0. As a result, the P-channel MOS transistor 2 is turned on, and the output of the gate circuit becomes 1 corresponding to the data input.

Next, when the data input becomes 0, the output of the AND circuit 5 (the output of 3NAND) immediately becomes 1, and the P-channel MOS transistor 2 is turned off. On the other hand, when the data input becomes 0, the delay non-inverter 11
At the time corresponding to the delay time of (1), the output of the output OR circuit 6 (the output of 3NOR) becomes 1. As a result, the N-channel MOS transistor 3 is turned on, and the output of the gate circuit becomes 0 corresponding to the data input.

The above operation is in the following order. FIG.
0, the N-channel MOS transistor 3 is turned off (period B) at the time of rising of the data input in order in response to the periods B and C shown in FIG. The channel type MOS transistor 2 is turned on (period C).

When the data input falls, the P-channel MOS transistor 2 is turned off (period D) in order corresponding to periods D and A in FIG. 10, and then the N-channel MOS transistor 2 is turned off in response to the delay. The type MOS transistor 3 is turned on (period A).

That is, during the change period of the data input based on the delay time of the delay non-inverter 11, both the P-channel type MOS transistor 2 and the N-channel type MOS transistor 3 are turned off so as to pass through. Blocking current.

Next, FIG. 11 shows a parallel embodiment of the present invention for increasing the speed and preventing the through current. In FIG. 11, 1 is an inverter, 2 is a P-channel MOS transistor, and 3 is N
Channel type MOS transistor, 4 is a delay inverter,
5 is an output inversion AND circuit, 6 is an output inversion OR circuit, 7 is a second P-channel MOS transistor, 8 is a second N-channel MOS transistor, and 9 is a three-input AND output inversion. Circuit, 11 is a delay non-inverter, 1
Numeral 0 denotes a logical OR circuit for inverting the output of three inputs, and numeral 14 denotes a stray capacitance when the subsequent stage is viewed from the data output terminal in the configuration of FIG.

The configuration shown in FIG. 11 is based on the second embodiment of the high-speed operation of the present invention shown in FIG. 3, and the delay non-inverter 11 is further added to simultaneously increase the operation speed and prevent the through current. Things.

FIG. 12 is a diagram for explaining the operation of the configuration shown in FIG. 11, and shows the case where the control signal is 0. First, the operation for speeding up the present invention will be mainly described. First, when the data output rises, the inverter 1 outputs 1 because the control signal is 0 when the data input rises to 1. The logical product of the data input and the output of the inverter 1 is input. The outputs of the circuit 5 and the OR circuit 6 are obtained by inverting the data input.

On the other hand, the delay inverter 4 delays the data input by the delay non-inverter 11, and further delays and inverts the data input by the delay amount of the delay inverter 4 and outputs the delayed data.
Accordingly, the output of the AND circuit 9 (in FIG. 12, abbreviated as 3NAND9 output) of the three-input output inversion supplied with the data input, the output of the inverter 1 and the output of the delay inverter 4 is the delay signal. It becomes 0 for a certain period from the rise of the non-inverter 11 to the fall of the output of the delay inverter 4. Since the output of the AND circuit 9 for inverting the output of the three inputs is supplied to the gate of the second P-channel MOS transistor 7, the output of the second P-channel MOS transistor 7 is
The transistor 7 is turned on for the fixed period when the output of the AND circuit 9 for inverting the three inputs is zero. At this time, since 0 is also supplied to the gate of the P-channel MOS transistor 2, the P-channel MOS transistor 2
And the second P-channel type MOS transistor 7 are simultaneously turned on for a predetermined period (period E shown in FIG. 12) of the output 0 of the AND circuit 9 of the output inversion of the three inputs.

As a result, the impedance seen from the side of the stray capacitance 14 decreases, and the rising response of the data output is reduced as shown in FIG.
And the speeding up of the present invention is achieved.
On the other hand, in the case of the falling of the data output, similarly, when the data input falls to 0, the output of the delay non-inverter 11 and the output of the delay inverter 4 are supplied with the inverted OR circuit 10 of the three inputs. Output (3 NOR in FIG. 12)
10 output) is the delay non-inverter 1
It becomes 1 for a certain period from the fall of one output to the rise of the output of the delay inverter 4. The output of the OR circuit 10 for inverting the output of the three inputs is the second N-channel type MOS.
Since the second N-channel MOS transistor 8 is supplied to the gate of the transistor 8, the output of the OR circuit 10 of the three-input output inversion is ON for the certain period of time. At this time, since 1 is also supplied to the gate of the N-channel MOS transistor 3, the N-channel MOS transistor 3 and the second N-channel MOS transistor 3
The transistor 8 is a logical OR circuit 1 for inverting the output of the three inputs.
The output of 0 is turned on at the same time as the constant period of 1 (period F shown in FIG. 12). Therefore, the impedance seen from the floating capacitor 14 side is reduced, and the response of the falling edge of the data output is speeded up as compared with FIG. 16, and the speeding up of the present invention is achieved.

Referring to FIG. 12, the function of preventing the through current of the present invention in the inverter gate composed of P-channel MOS transistor 2 and N-channel MOS transistor 3 in FIG. 11 will be mainly described.

When the data input rises to 1, the logical sum of the data input and the data input delayed by the delay non-inverter 11 is 1, so the output of the inverted OR circuit 6 (abbreviated as 3NOR output). Is 0. Thereby, the N-channel MOS transistor 3 is turned off. On the other hand, the logical product of the output of the delay non-inverter 11 and the data input indicates the output of the AND circuit 5 whose output is inverted at the time corresponding to the delay time of the delay non-inverter 11 (abbreviated as 3NAND output). Becomes 0. As a result, the P-channel MOS transistor 2 is turned on, and the output of the gate circuit becomes 1 corresponding to the data input.

Next, when the data input becomes 0, the output (3 NAND output) of the AND circuit 5 becomes 1 immediately,
The channel type MOS transistor 2 is turned off. On the other hand,
When the data input becomes 0, the output (3NOR output) of the output inversion OR circuit 6 becomes 1 at the time corresponding to the delay time of the delay non-inverter 11. As a result, the N-channel MOS transistor 3 is turned on, and the output of the gate circuit becomes 0 corresponding to the data input.

The above operation is in the following order. FIG.
In response to periods B and C shown in FIG. 2, the N-channel MOS transistor 3 is first turned off at the time of rising of data input (period B), and then the P-channel MOS transistor 3 is responded to the delay of the delay non-inverter 11. The MOS transistor 2 is turned on (period C).

At the time of falling of the data input, the P-channel type MOS transistor is first turned on in order corresponding to the periods D and A shown in FIG.
The transistor 2 is turned off (period D), and the N-channel MOS transistor 3 is turned on in response to the delay (period A).

That is, during the change period of the data input based on the delay time of the delay non-inverter 11, both the P-channel type MOS transistor 2 and the N-channel type MOS transistor 3 are turned off so as to pass through. Blocking current.

As described above, in FIG. 11, the second embodiment of the speed-up of the present invention shown in FIG. 3 and the second embodiment of the through current blocking of the present invention shown in FIG. 9 are implemented in parallel. However, as shown in the above example, the speed-up and the through current blocking embodiments of the present invention can be implemented independently or in parallel, and each effect can be achieved independently or in conjunction with the implementation. It is clear that they can be performed in parallel.

[0086]

As described above in detail, according to the present invention, it is possible to reduce the dependency on the capacitive load while suppressing the increase in power consumption without changing the manufacturing process of a normal CMOS gate circuit, and to reduce the through current. Therefore, it is possible to provide a CMOS gate circuit in which the above-mentioned problems are prevented, so that a remarkable effect is attained for speeding up and stabilizing the constituent devices.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of a high-speed operation according to the present invention.

FIG. 2 is a diagram illustrating the operation of the configuration of FIG.

FIG. 3 is a second embodiment of the speed-up of the present invention.

FIG. 4 is a diagram illustrating the operation of the configuration of FIG. 3;

FIG. 5 is a third embodiment of the speed-up of the present invention.

6 is a diagram for explaining the operation of the configuration of FIG. 5;

FIG. 7 is a first embodiment of the through current blocking of the present invention.

FIG. 8 is a diagram illustrating the operation of the configuration of FIG. 7;

FIG. 9 shows a second embodiment of the through current blocking according to the present invention.

FIG. 10 is a diagram for explaining the operation of the configuration of FIG. 9; .

FIG. 11 is a parallel embodiment of speeding-up and blocking of a through current according to the present invention.

FIG. 12 is a diagram for explaining the operation of the configuration of FIG. 11;

FIG. 13 shows a conventional CMOS gate circuit.

FIG. 14 is a truth table of the configuration of FIG. 13;

FIG. 15 is a diagram illustrating the operation of the configuration of FIG.

FIG. 16 shows a conventional three-state CMOS gate circuit.

FIG. 17 is a truth table of the configuration of FIG. 16;

18 is a diagram illustrating the operation of the configuration in FIG.

FIG. 19 is a diagram illustrating a gate input voltage and a threshold voltage.

FIG. 20 is an operation state table of the circuit in FIG. 19;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Inverter 2 P-channel type MOS transistor 3 N-channel type MOS transistor 4 Delay inverter 5 AND circuit of output inversion 6 OR circuit of output inversion 7 Second P-channel type MOS transistor 8 Second N-channel type MOS transistor 9 AND circuit for inverting output of 3 inputs 10 OR circuit for inverting output of 3 inputs 11 Delayed non-inverter 12 OR circuit 13 AND circuit 14 Floating capacitance

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masayuki Horie 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture In-house Fujitsu Digital Technology Co., Ltd. (72) Susumu Suwa, 2-chome Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa No.3-9 Fujitsu Digital Technology Stock Company In-house

Claims (5)

[Claims] 1. A CMOS gate circuit having a configuration in which drains of a first P-channel MOS transistor and a first N-channel MOS transistor are connected to each other, wherein a second P-channel MOS transistor and a second N-channel MOS transistor are connected. A second P-channel MOS transistor and a second N-channel MOS transistor.
The drains of the transistors are connected to each other, and the connection point is connected to the connection point between the drains of the first P-channel MOS transistor and the first N-channel MOS transistor. The CMOS
The second N-channel MOS transistor is turned on for a predetermined time from the start of the rise of the data output of the gate circuit,
A CMOS gate circuit comprising a configuration in which the gate circuit is turned on for a predetermined time from the start of falling of the data output of the gate circuit. A first inverter for receiving the data input and inverting and outputting the data, and a drain of the first P-channel MOS transistor and a drain of the first N-channel MOS transistor connected to each other; A second inverter receiving the output of the inverter of claim 1, a delay inverter for delaying and inverting the data input;
An output inverting AND circuit for receiving the data input and the output of the delay inverter, an output inverting OR circuit for receiving the data input and the output of the delay inverter, A second P-channel MOS transistor having a drain connected to a connection point of a drain of the N-channel MOS transistor and receiving an output of the AND circuit of the output inversion at a gate; A second N-channel MOS transistor having a drain connected to a connection point of the drain of the first N-channel MOS transistor and having a gate receiving the output of the output inversion OR circuit; circuit. 3. A first inverter for receiving and inverting and outputting a control signal, a logical product circuit of a first output inversion receiving a data input and an output of the first inverter, and a data input and a control signal. A first output inversion OR circuit, and the drains of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other. To the first P
A second inverter receiving the channel type MOS transistor and receiving the output of the first output inversion OR circuit by the first N-channel type MOS transistor; An inverter, an AND circuit for receiving a data input, an output of the delay inverter, and an output of the first inverter, and a second output inversion receiving a data input, a control signal, and an output of the delay inverter And a drain connected to a connection point between the drains of the first P-channel MOS transistor and the first N-channel MOS transistor, and gate the output of the second output inverted AND circuit. A second P-channel MOS transistor, a first P-channel MOS transistor and a first N-channel MOS Is a drain connected to the connection point of the drains of transistors, CMOS gate circuit, characterized in that it comprises a second N-channel type MOS transistor for receiving an output of the OR circuit of the second output inversion gate. 4. A first inverter for receiving and inverting and outputting a control signal, an AND circuit for inverting output receiving a data input and an output of the first inverter, and an output inverting receiving a data input and a control signal. And the drains of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other, and the output of the AND circuit of the first output inversion is connected to the first P-channel MOS transistor. Channel type MO
A non-inverter for delaying data input in a CMOS gate circuit comprising: a second inverter receiving an S transistor and receiving the output of the first output inverted OR circuit by the first N-channel MOS transistor An OR circuit receiving an output of the delay non-inverter and an output of the AND circuit of the output inversion, an AND circuit receiving the output of the delay non-inverter and the output of the output inversion OR circuit, A second P-channel MOS transistor having a drain connected to a connection point between the drains of the one P-channel MOS transistor and the first N-channel MOS transistor and receiving an output of the OR circuit at a gate; A drain is connected to a connection point between the drains of one P-channel MOS transistor and the first N-channel MOS transistor. Are continued, CMOS gate circuit, characterized in that it comprises a second N-channel type MOS transistor for receiving an output of the logical product circuit to the gate. 5. A delay gate for delaying and outputting a data input, an AND circuit of an output inversion receiving the data input and the output of the delay gate, and a logical sum of an output inversion receiving the data input and the output of the delay gate Circuit and P-channel MOS
CMOS including transistor and inverter formed by connecting drains of N-channel MOS transistors
A gate circuit, wherein the output of the AND circuit of the output inversion is a P-channel MOS
The output of the OR circuit of the output inversion is received at the gate of the N-channel MOS transistor, and the period corresponding to the delay time of the delay gate is the same as that of the P-channel MOS transistor. A CMOS gate circuit wherein both of the N-channel MOS transistors are deactivated.