JPH1124796A - Power-on reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To permit the reset of an internal circuit and to conquer the instable operation of the internal circuit by performing necessary and sufficient clock signal inputs even at the time of a product test by generating internal clocks without inputting any clock signal from the outside. SOLUTION: A counter 14 counts clock signals from an oscillator 13 over a period from the power-on of a system to the fixture of all the nodes of internal circuits such as logic circuits 101 and 102 at potentials corresponding to the clock signals. An output Out of the counter 14 is connected to an R input so as to reset an SR-FF 12 after prescribed counts. Corresponding to the value of a select signal, a selector 15 selects any one of two inputs and sends it to the output Out. Namely, an internal clock signal INCK of a Q output from the oscillator 13 and an external clock signal EXCK for the operation control of the system applied from the other system are supplied to the selector 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power-on reset circuit, and more particularly, to a power-on reset circuit used in a high-speed circuit.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a reset circuit including a flip-flop, which is formed in a general logic circuit. Each of the logic circuits 101 and 102 includes an inverter, a logic gate circuit, and the like, and is constituted by a set of circuits. The reset circuit includes flip-flops 27-2 for holding data for transmitting a signal synchronized with a clock signal.
9, the reset signal R becomes effective, thereby preventing unnecessary data transmission.

In FIG. 5, flip-flops 27 to 2
9 uses a single clock signal CLK for clock input. The flip-flops 27 to 29 are master-slave type flip-flops. A reset signal R for resetting the flip-flops 27 to 29 is
Set to fall active. That is, when the reset signal R of the ground potential (hereinafter abbreviated as “L”) is input, the outputs of the flip-flops 27 to 29 are set to “L”.

FIG. 6 is an example showing operation waveforms of the circuit of FIG. The circuit of FIG. 5 operates like a shift register,
For example, data 1 (hatched data) of the input data IN is output to the node 4 at the rise of the clock signal CLK at time t1. Further, the input data 1 is output to the node 5 at the rise of the clock signal CLK at time t2. Similarly, data 1 is output to output data OUT because clock signal CL at time t3
This is from the rise of K.

The data provided from the data input IN is output to the data output OUT in this manner. However, if the reset operation by the reset signal R is not performed, the initial operation as shown by the timing of the broken line tA in FIG. In the state, the value of the internal node (for example, the node 5 and the data output OUT as illustrated) becomes undefined. If the data is undefined, it is not possible to guarantee what kind of behavior the circuit will exhibit. Therefore, a reset operation is performed at the start of the operation.

FIG. 7 is an example showing operation waveforms of the circuit of FIG. 5 accompanied by a reset operation. When the power is turned on, it is in a normal reset state (by a power-on reset circuit or the like: the description is omitted here). Therefore, as shown by a reset signal R in FIG. 29 is reset. Therefore, since the output of any flip-flop becomes “L”, the value of the internal node (here, node 5 and the like) does not become undefined in the initial operation state as shown by the timing of the broken line tA, and the value of the output data OUT becomes There is no indefinite.

The reset operation is performed as described above. In a logic circuit operating at high speed, the output delay of the flip-flop is further affected by the reset circuit included in the flip-flop. This is because, compared to a flip-flop without reset, a logic for reset is added with a reset, so that a signal propagation delay is longer.

Therefore, a logic circuit operating at high speed employs the circuit shown in FIG. That is, the flip-flops 7 to 9 having no reset function are used, and a two-input AND gate 21 of, for example, a data input and a reset signal R (falling active) is added to the first stage of the signal transmission system. Thus, the configuration is such that the reset signal R as the data of the flip-flop is shifted and transmitted to the subsequent stage by the clock signal CLK.

FIG. 9 is an example showing operation waveforms of the circuit of FIG. The reset is performed by reset signal R (ground potential:
"L") is input to the AND gate 21. During the reset period, the input of the flip-flop 7 becomes “L”, and the output of the flip-flop 7 becomes “L” at the rising of the clock signal CLK, that is, the node 4 becomes “L”. Similarly, at the next rising of the clock signal CLK, the flip-flop 8
, That is, the node 5 becomes “L”. Hereinafter, similarly, reset is performed by writing "L" data to each flip-flop.

The operation of the circuit is such that the clock signal CLK is input to all flip-flops, in FIG. 9, until the time when "L" data is written, that is, the time indicated by the broken line ta in the flip-flops 7 to 9, and the logic circuits 101, 102, etc. This will reset the internal circuit.

In the circuit system shown in FIG. 8, the circuit can be reset without using a flip-flop with reset. However, a required number of clock signal inputs are required until all the circuits are reset.

Until the required number of clock inputs is received,
In some circuits, the data becomes indefinite and an unstable operation is forced. For example, in the logic circuit 101 shown in FIG. 8, the operation state of the logic circuit 101 cannot be guaranteed because the data at the node 5 is indeterminate until the time indicated by the broken line tb in FIG.

In a normal operation, a reset operation can be performed by inputting a required number of clock signals. However, during a product test (for example, a Burn-In test (operation measurement test at a higher temperature than normal)) In (2), there is a limit (number of inputs) of the clock signal input, and a clock input sufficient to reset the internal circuit may not be performed.
Therefore, the internal circuit becomes unstable, and an unexpected operation occurs. When the power is turned on, the clock may not be supplied from the system in some cases, and the internal circuit becomes unstable as described above.

[0014]

As described above, a configuration in which a flip-flop having no reset function is provided between logic circuits due to the necessity of high-speed operation and a reset signal is shifted and transmitted using an external clock signal is employed. However, the fear of unstable operation of the internal circuit due to the limitation (the number of inputs) of the clock signal input during the product test cannot be avoided.

An object of the present invention is to provide a power-on reset circuit that inputs a necessary and sufficient clock signal even during a product test and overcomes unstable operation of an internal circuit in view of the above circumstances.

[0016]

A power-on reset circuit according to the present invention includes a detection circuit for detecting power-on of a system, and a clock signal for transmitting a reset signal to an internal circuit of the system in accordance with an output of the detection circuit. And a clock generation circuit that generates
A counter for counting clock signals from the clock generation circuit for a predetermined time until the potentials of all nodes of the internal circuit are determined in accordance with the reset signal; and selecting a clock signal from the clock generation circuit when the counter counts. A selector that propagates the reset signal to an internal circuit of the system, and switches to a clock signal for controlling the operation of the system which is provided from a system different from the clock generation circuit after counting by the counter. It is characterized by.

[0017]

FIG. 1 is a circuit diagram showing a configuration of a power-on reset circuit according to a first embodiment of the present invention. The logic circuits 101 and 102 inside the system
Since it is composed of a set of circuits including an inverter, a logic gate circuit and the like (not shown), they are represented as shown in the figure for convenience. Data holding flip-flops 7 to 9 for transmitting a signal in synchronization with a clock signal are provided. In the first stage of this signal transmission system, for example, a two-input AND gate 21 for a data input and a reset signal R (falling active) is provided. Is provided. Thus, at the time of power-on reset, the reset signal R is made valid, and the data is shifted to the subsequent stage by the clock signal CLK as the data of the flip-flop.

According to the present invention, an oscillator (clock generation circuit) for internally generating a clock signal spontaneously for a certain period after power-on, and a clock signal for generating the clock signal only for a period necessary and sufficient for an internal reset. A counter is provided, the reset is completed during the counting period of the counter, and undefined data is not propagated during the operation period. Hereinafter, the circuit configuration will be described.

The power-on detection circuit 11 is a circuit which detects the power-on of the system and outputs a power supply potential (hereinafter abbreviated as "H") for a certain period of time after the power supply reaches the power supply voltage (FIG. 1). 2 node 16).

The output of the power-on detection circuit 11 is S
R-FF (set / reset flip-flop) 12
S (set) input. When "H" is input to the S input, "H" is output to the Q output. Even if the S input changes thereafter, the output is not affected. The Q output (node 17) is later inverted via an inverter IV to become a reset signal R. The Q output of the SR-FF 12 changes when the reset input (R in the block of the SR-FF 12) is “H”.
Is input only, in which case the Q output becomes "L".

The oscillator 13 is a circuit for generating a clock while the enable signal (E in the figure) is at "H". That is, SR applied to enable signal E input
While the Q output of the FF 12 is “H”, a clock signal for transmitting a reset signal to a logic circuit inside the system is generated at the Q output of the oscillator 13.

The Q output of the oscillator 13 is input to a counter 14. The counter 14 counts the input In,
Counting is performed up to a set value, and when counting is performed up to the set value, “H” is output to the output Out. That is, the counter 14 counts the clock signal from the oscillator 13 for a predetermined time from when the power of the system is turned on until the potentials of all the nodes of the internal circuits such as the logic circuits 101 and 102 are set to the potentials according to the reset signal. . The output Out of the counter 14 is SR-FF after a predetermined count is counted.
12 is connected to the R input so that it is reset.

The selector 15 selects one of the two inputs (1 and 0 in the figure) according to the value of the select signal (S in the figure) and sends it to the output Out. If the select signal is "L", input 0 is output, and if "H", input 1 is output.

That is, the selector 15 is configured to supply the internal clock signal INCK, which is the Q output from the oscillator 13, and the external clock signal EXCK for controlling the operation of the system provided from another system. Has become. The signal at the node 17 which is the Q output of the SR-FF 12 is supplied to the S input of the selector 15. Thus, one of the two clock signals is selectively output from the output Out of the selector 15. That is, when the counter 14 counts, the clock signal IN from the oscillator 13 is output.
CK is selected, a reset signal is propagated to the internal logic circuit of the system, and after counting by the counter 14, the clock is switched to an external clock signal EXCK for controlling the operation of the system, and the input data is transmitted to the internal circuit of the system. .

Next, the circuit operation of the configuration shown in FIG. 1 will be described with reference to the waveform diagram shown in FIG. In addition, for simplicity of description, the description is divided into three timings. (I) Power-on period When the power is turned on, the power-on detection circuit 11 detects the power-on, and the node 16 becomes “H”. Next, SR-FF
12 is set, and the node 17 becomes "H". Next, oscillator 13 is enabled and the oscillator output appears at node 18. The selector 15 sets the node 17 to “H”.
Therefore, the node 18 is selected, and the oscillator 1 is connected to the output Out.
An output of 3 appears.

(Ii) Reset Period A clock signal from the oscillator 13 is sent to the output Out of the selector 15, and this clock signal is input as many times as necessary for resetting the internal circuits (the logic circuits 101, 102, etc.). Then, the necessary and sufficient number of resets is 8
Times). When the necessary number of clock signals from the oscillator 13 is counted by the counter 14, the counter 14 outputs "H". That is, the node 19 changes from “L” to “H”. Here, when the node 19 changes to “H”, the SR-FF 12 is reset, and the node 17 changes from “H” to “L”. As a result, the reset signal changes from “L” to “H”.

(Iii) Operation Period When the node 17 changes from “H” to “L”, the selector 15
Selects the node 20 of the external clock signal, and selects the selector 1
The external clock signal EXCK appears at the output Out 5. Thereafter, similarly to the normal operation, the external clock signal EXCK
Circuit operation by the clock signal CLK based on the

That is, during a period in which the circuit must be reset, there is no need to input an external clock signal, and a clock is generated by an internal clock generation circuit to reset the internal circuit.

FIG. 3 is a circuit diagram showing a specific example of the oscillator 13, counter 14, and selector 15 in the circuit of FIG. The oscillator 13 is configured by a ring oscillator in which inverters IV are connected in a ring. Counter 14
Is a shift register configuration using flip-flops FF1 to FF3. The output of a NAND gate 141 having three inputs of Q outputs of FF1, FF2, and FF3 is a reset signal / R (the / at the top indicates inversion, and in the figure, (Low active with a bar attached to it). With this configuration, the counter is automatically reset when the number of times necessary for the reset is sufficient, here, eight times. The output of the NAND gate 141 is supplied to the RS-
Connected to the reset input of FF12. Selector 15
Is a NAND gate 15 in which one of two inputs is an external clock signal EXCK and the other is an inverted signal of the S input (Q output of the RS-FF 12) (a signal passed through the inverter 150).
One of the 1 and 2 inputs is the internal clock I from the oscillator 13.
NCK, the other includes an NAND gate 152 having S input (Q output of RS-FF 12) and a NAND gate 153 having two inputs of outputs of NAND gates 151 and 152, and an output of NAND gate 153 is an output of selector 15. Out.

FIG. 4 shows another embodiment of the present invention, in which the power-on reset circuit of FIG. 1 is applied to a DRAM. The oscillator 13 is configured to share the substrate bias generation circuit of the DRAM, and the counter 14 also shares the counter circuit inside the DRAM. Thus, the DRAM has many components of the power-on reset circuit of the present invention. Others are prepared in an interface circuit, and the power-on reset circuit of the present invention can be realized with a minimum of additional circuits.

In the case of a configuration in which a reset signal is shifted and transmitted using an external clock signal at the time of testing a DRAM product, there is a concern that unstable operation of an internal circuit may be caused by a limitation (the number of inputs) of a clock signal input. By applying the present invention to the prior art, during the period in which the circuit must be reset, the internal circuit is reliably reset by the generation of the internal clock without depending on the external clock signal.

[0032]

As described above, according to the present invention,
Since the internal clock is generated without inputting a clock signal from the outside, the internal circuit can be reset. Therefore, the internal circuit can be reset without being affected by the limitation of the number of clock inputs during a product test, and the state of the internal circuit is not unstable, and malfunction of the circuit can be prevented. Also, even when the clock is not supplied by the system, the internal circuit can be reset.

As a result, it is possible to provide a power-on reset circuit that inputs a necessary and sufficient clock signal by generating an internal clock when the power is turned on and overcomes the unstable operation of the internal circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a power-on reset circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing a circuit operation of the configuration of FIG.

FIG. 3 is a circuit diagram showing a specific example of a part of the circuit of FIG. 1;

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

FIG. 5 is a circuit diagram including a flip-flop with reset, which is configured in a conventional general logic circuit.

FIG. 6 is a waveform chart showing the operation of the circuit of FIG. 5;

FIG. 7 is a waveform chart showing the circuit operation of FIG. 5 with a reset operation.

FIG. 8 is a conventional circuit diagram for performing a reset operation on the premise of high-speed operation.

FIG. 9 is a circuit diagram showing the circuit operation of FIG. 8;

[Explanation of symbols]

4 to 5, 16 to 19 nodes 7 to 9 flip-flops 101 and 102 logic circuit 11 power-on detection circuit 12 SR-FF (set / reset flip-flop) 13 oscillator 14 counter 15 selector

Claims (3)

[Claims] 1. A detection circuit for detecting power-on of a system, a clock generation circuit for generating a clock signal for transmitting a reset signal to an internal circuit of the system in accordance with an output of the detection circuit, and a power-on of the system A counter that counts a clock signal from the clock generation circuit for a predetermined time until the potentials of all the nodes of the internal circuit are determined according to the reset signal; and a clock from the clock generation circuit when the counter counts. A selector for selecting a signal, transmitting the reset signal to an internal circuit of the system, and switching to a clock signal for controlling the operation of the system which is provided from a different system from the clock generation circuit after counting by the counter. A power-on reset circuit, comprising: 2. The power-on reset circuit according to claim 1, wherein said clock generation circuit is configured using a clock generation circuit in a substrate bias generation circuit in a DRAM. 3. The power-on reset circuit according to claim 1, wherein the counter uses a counter circuit in a DRAM.