JPH11238313A - Optical disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely binarize an address signal even when upper/lower balance of the address signal is different greately by precisely detecting a threshold value slicing the upper side signal and the lower side signal of the address signal, imparting an offset to the address signal according to its difference and automatically adjusting the balance between the upper side and lower side. SOLUTION: Comparators 3, 4 binarize the address signals based on the threshold values (+), (-) of symmetric voltages to output them as upper side and lower side addresses. An OR gate 6 adds these outputs to make them binarized addresses, and monostable-multivibrators 5, 7 output upper side and lower side address detection signals. When the upper side and lower side of the address signal are unbalanced, the threshold values (+) are detected on specified two sections in a header field, and the balance of the signal before binarization is changed suitably according to the difference. Thus, by offsetting both differential address signals, and taking the difference signal of both signals, the upper/lower balance is improved, and the upper side and lower side signals are sliced precisely.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk apparatus, and more particularly, to an optical disk apparatus in which address information is recorded intermittently even if a reproduction signal is deteriorated due to a lens shift. The reproducing means has a feature.

[0002]

2. Description of the Related Art In recent years, with the advent of DVDs (Digital Video Disks), attention has been paid to large-capacity optical disk devices. ing.

Hereinafter, an address reproducing circuit in a DVD-RAM reproducing circuit will be described. FIG. 7 is a block diagram of the address reproducing circuit. 7, 101, 10
Reference numeral 2 denotes a comparator, which binarizes the address signal with respect to each threshold value. An OR gate 104 adds the outputs of the comparators 101 and 102. Reference numerals 103 and 105 denote retriggerable mono-multis, which have a function of outputting a pulse for an appropriate time in response to an output of the comparator 101 or 102, and output a pulse again from that point when a trigger input is received during pulse output. Has a function.

[0004] 106, 109 are current sources, 107, 108
Denotes an analog switch, and 106 to 109 constitute a charge pump circuit. Reference numeral 110 denotes an analog switch that opens and closes according to an address gate signal. The analog switch 110 charges and discharges the capacitor 111 when the address gate signal is “H”. Reference numeral 112 denotes an inverter, which applies a voltage obtained by inverting the threshold voltage of the comparator 102 to the comparator 101 as a threshold voltage.

[0005] The operation of the address information reproducing circuit of the DVD-RAM configured as described above will be briefly described.

According to the DVD-RAM standard, a disk is divided into a plurality of zones, and sectors are provided for each round of the disk by the number (n) unique to each zone. A sector is composed of a header field that forms an address when a disc is created, and a recording field that records data by the user.The header field is recorded across grooves and lands to reduce crosstalk from adjacent tracks. ing. For the track, zone CLV recording is performed while switching the groove and land every one rotation.

As shown in FIG. 8, in the groove, (m-
In the switching section from the 1) th sector to the (m) sector, the address of the (m) sector behind the header portion is valid. In the land, the address of the (m + n) th sector in front of the header portion is valid at the portion where the (m + n-1) th sector is switched to the (m + n) th sector.

The reproduction of the header field uses a tracking error signal. The tracking error signal of the groove in FIG. 9 is a tracking error signal when the laser spot moves in the groove in FIG. 8, and the tracking error signal of the land indicates that when the laser spot moves in the land. . As described above, the feature of the groove and the land is that the waveform of the header portion is inverted upside down.

Next, reproduction of the header field will be briefly described with reference to FIGS. When the address signal shown in FIG. 10 is input to the comparators 101 and 102, the comparator 101 sets the threshold (−) as a threshold voltage, and the comparator 102 sets the threshold (+) as a threshold voltage. Perform binarization.

Here, the threshold value (-) is a voltage obtained by inverting the threshold value (+) by the inverter 112 with reference to the reference voltage. Therefore, the threshold value (-) and the threshold value (+) are The voltage is symmetric with respect to the reference voltage.

In FIG. 10, an upper address which is higher than the reference voltage of the address signal is an upper address, and a lower address which is lower than the reference voltage is a lower address.
The value added by the R gate 104 is a binary address signal.

The lower address is a mono multi 103
The mono multi 103 outputs a lower address detection signal. The upper address is input to the mono multi 105 as a trigger signal, and the mono multi 105 outputs an upper address detection signal.

The lower address detection signal and the upper address detection signal are added by an external circuit and used as a gate signal of the analog switch 110 as an address gate signal for identifying a header field. The binary address signal is supplied to the current sources 106 and 109, the analog switch 10
7 and 108, the input signal of the charge pump. When the address gate signal is "H" and the analog switch 110 is on, the binary address signal "H" is output.
The charging current flows into the capacitor 111 during the period, and the discharging current flows from the capacitor 111 during the “L” period of the binary address signal.

According to the above configuration, since the capacitor 111 is charged and discharged only during the header field, the threshold value is set so that the pulse duty of the binary address signal gated by the address gate signal is set to 50%. −), Feedback is applied to the threshold value (+), so that the address detection accuracy is improved and accurate binarization is possible.

[0015]

However, in the prior art, the condition is such that the peak values above and below the reference voltage of the address signal are substantially equal, and the threshold voltage when binarizing by the comparator is used. Also has a circuit configuration for generating a voltage symmetric with respect to the reference voltage.

For this reason, when the peak values above and below the reference voltage of the address signal become unbalanced due to the variation of the optical pickup and the lens shift, the binarization cannot be performed accurately. Occurs.
The optical variation of the optical pickup affects the spot position and spot shape on the detector that receives the reflected light from the disk. Even when the light spot moves in the center of the groove or land shown in FIG. 8, the address signal shown in FIG. The upper and lower sides of are not symmetric. Further, in the lens shift state, the spot position on the detector is shifted, so that the upper and lower sides of the address signal are not symmetrical also in this case.

FIG. 11 shows an example of such a state.
Since the upper amplitude of the address signal is larger than the lower amplitude, the threshold value is feedback-controlled so that it is at the center of the upper amplitude. In this case, the lower current cannot be detected and the discharge current flows out of the capacitor 111.

Further, in an actual drive, an error may occur during reproduction and an optical pickup may flow, and the reproduction position may be largely shifted. Since the DVD-RAM disk has a constant linear velocity recording (ZCLV) for each zone, for example, when flowing from the innermost circumference to the outermost circumference, the address signal frequency increases, and when flowing from the outermost circumference to the innermost circumference. Becomes smaller, so if the feedback gain for slicing the address is constant,
The difference in the charging / discharging time of the capacitor 13 extremely deteriorates the slice accuracy.

[0019]

In order to solve the above-mentioned problems, the present invention provides a balance adjusting means for adjusting the vertical balance of an address signal with respect to a reference potential, and the number of pulses of the first and second binarized signals. Pulse counting means for counting, digital comparison means for outputting a detection pulse for a predetermined time when it is detected that the number of pulses matches at least one predetermined value, and a pulse output means for outputting a detection pulse during the detection pulse. Means for individually detecting the first and second thresholds, and means for applying feedback to the balance adjusting means so that the absolute values of the first and second threshold voltages are equal. It is characterized by doing.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, there is provided an address detecting means for extracting an address signal from a reproduction signal of an optical disk on which address information is recorded intermittently, A first comparing means for converting the address signal into a first binary signal with a threshold value of 1, and a second comparing means for converting the address signal into a second binary signal with a second threshold value
And the first and second binarized signals so that the average lengths of the pulse widths of the first and second binarized signals are equal.
In the optical disc apparatus having the first feedback means and the second feedback means for changing the first and second threshold values by feeding back the comparison means, the DC offset value of the address signal is changed. Balance adjusting means for adjusting the balance between the positive and negative amplitudes of the address signal with respect to the input bias voltage of the first and second comparing means; and pulses of the first and second binarized signals. A pulse counting means for counting the number, a digital comparing means for outputting a detection pulse of a predetermined time when it is detected that the number of pulses matches at least one predetermined value, and the detection pulse being output. A first sample / hold means for sampling / holding the first threshold while the detection pulse is being output. A second sample / hold means for sampling / holding said second threshold, said first
And a differential output means for multiplying and outputting the result by taking a difference between the second sample / hold means and the second sample / hold means, and an output of the differential output means is given to the balance adjusting means as the DC offset value, And a third feedback unit that performs feedback so that an absolute value of the first threshold value is equal to an absolute value of the second threshold value.

As a result, the first threshold value and the second threshold value are accurately detected and feedback is performed so that the absolute values of the first threshold value and the second threshold value are equal. As a result, the address detection accuracy can be improved.

According to a second aspect of the present invention, there is provided means for detecting the pulse output time of the first and second binarized signals, and the pulse output time when reproducing the optical disc at 1 × speed. Means for comparing the pulse output time with the predetermined time, and setting the gain of the first and second feedback means if the pulse output time is within the predetermined time, At the predetermined time, a predetermined initial gain is set so as to accurately binarize the maximum mark length signal and the minimum mark length signal, and when the pulse output time is longer than the predetermined time, the first gain is set. And means for lowering the gain of the second feedback means.

As a result, the feedback gain is changed according to the address signal reproduction frequency, so that the slice gain at the time of binarization can be made appropriate, and thereby the binarization error can be reduced.

(Embodiment 1) An embodiment of the present invention will be described below. FIG. 1 is a block diagram of an optical disk device according to an embodiment. Reference numeral 1 denotes a balance adjustment circuit that changes a combined balance of a differential address signal (+) and a differential address signal (−), and 2 denotes a balance adjustment circuit. This is a differential amplifier for synthesizing differential signals. Reference numerals 3 and 4 denote comparators, which binarize the address signal with respect to each threshold value. Reference numeral 6 denotes an OR gate for adding the outputs of the comparators 3 and 4. Reference numerals 5 and 7 denote retriggerable mono-multis, a function of receiving pulses from the comparators 3 and 4 and outputting a pulse for an appropriate time, and a function of outputting a pulse again from the time when a trigger input is received during pulse output. have.

Reference numerals 8 and 11 denote current sources, reference numerals 9 and 10 denote analog switches, and 8 to 11 constitute a charge pump circuit. Reference numeral 12 denotes an analog switch which is opened and closed by an address gate signal, and is used to charge and discharge the capacitor 13 when the address gate signal is at "H".

Reference numeral 14 denotes an inverter which applies a voltage obtained by inverting the threshold voltage (+) of the comparator 4 to the comparator 3 as a threshold voltage (-). A counter 15 counts a channel clock which is a clock synchronized with the binary address signal when the address gate signal is "H", and is initialized at rising edges and falling edges of the address gate signal.

Decoders 16 and 17 decode the result counted by the counter 15, and when they match, output a pulse of a predetermined time.
Used as 19 gate-on signals. Reference numerals 20 and 21 denote capacitors for holding the voltage values when the analog switches 18 and 19 are turned on. Reference numeral 22 denotes a differential amplifier which calculates the voltage difference held by the capacitors 20 and 21 and multiplies the output by A, and outputs the result. The output is connected to the adjustment terminal of the balance adjustment circuit 1 so that the capacitor 2
Automatic balance adjustment is performed according to the voltage difference held at 0 and 21.

The operation of the optical disk device configured as described above will be briefly described. When the address signal is input to the comparators 3 and 4, the comparator 3 sets the threshold (−) as a threshold voltage,
Performs binarization using a threshold (+) as a threshold voltage.

Here, the threshold value (-) is a voltage obtained by inverting the threshold value (+) by the inverter 14 with reference to the reference voltage. Therefore, the threshold value (-) and the threshold value (+) are The voltage is symmetric with respect to the reference voltage. An upper address obtained by binarizing the reference voltage of the address signal is an upper address, a lower address obtained by binarization is a lower address, and a sum obtained by the OR gate 6 is a binarized address signal. The lower address is input to the mono multi 5 as a trigger signal, and
Outputs a lower address detection signal, and the upper address is input to the mono multi 7 as a trigger signal.
Outputs an upper address detection signal.

The lower address detection signal and the upper address detection signal are added by an external circuit and used as a gate signal of the analog switch 12 as an address gate signal for identifying a header field. The binarized address signal becomes an input signal of a charge pump constituted by the current sources 8 and 11 and the analog switches 9 and 10. When the address switch signal is “H” and the analog switch 12 is on, the capacitor 1 is turned on during the “H” period of the binary address signal.
3, the charging current flows, and the binary address signal “L”
During the period, a discharge current flows from the capacitor 13. Therefore, when the lower address and the upper address are normally detected, the capacitor 13 is used only during the header field.
The pulse duty of the binary address signal gated by the address gate signal is 5
Feedback is applied to the threshold value (-) and the threshold value (+) so as to be 0%.

However, as described with reference to FIG. 11, when the upper side and the lower side of the address signal are unbalanced, the threshold value is first feedback-controlled so as to be at the upper center. It becomes impossible to capture the lower waveform at the portion that enters the slice, and the address cannot be reproduced.

Therefore, in this embodiment, means is provided for detecting a threshold value (+) in the two sections specified in the header field and appropriately changing the balance of the signal before binarization based on the difference. ing.

The counter 15 shown in FIG. 1 is a counter using an address gate signal as an enable control signal, and counts a channel clock only during a period when the address gate signal is "H". The channel clock is a clock (period: T) synchronized with the binarized address signal.
Created by the L circuit.

Here, the contents of the header will be briefly described with reference to FIG. 2. VFO1 is 36 bytes (576T), VF
In O2, a 4T signal is recorded for 8 bytes (128T), and the drive can be used to synchronize the PLL. AM is an address mark, and the drive uses it as a synchronization signal of the address signal. PIDs 1 to 4 are physical addresses, and IEDs 1 to 4 are error detection codes of the PIDs 1 to 4, respectively. PA1 and PA2 are codes added so as to keep the 8-16 modulation format.

In this embodiment, the decoded value of the decoder 16 for decoding the count value of the counter 15 is 73
6. Set the decode value of the decoder 17 to 1760.
This value is the position where VFO2 is detected in FIG.

FIG. 3 shows the change of the slice voltage for binarizing VFO1 and VFO2.
In the case of (1), the charge / discharge of the capacitor 13 starts after the address gate signal rises to "H", so that the time required for the slice voltage to rise is required. I haven't.

The time required for the rise depends on the amplitude, the vertical balance, and the frequency of the address signal. In particular, the amplitude and the vertical balance differ depending on the drive.
When the slice voltage at FO1 is used as the threshold, the error is large.

Further, PID1-4, IED1-4, PA
In the period of 1, PA2, data of 4T or more is randomly included, and charging and discharging of the capacitor 13 becomes irregular, so that the value differs for each sector.

On the other hand, in the case of VFO2, the front H
Since the slice voltage has already risen in the header1 period, and the VFO2 is composed of only the 4T signal, charging and discharging of the capacitor 13 can be performed stably.

As described above, the decoder 16 has a
er2 VFO2 period is detected and the analog switch 18
Is turned on, and the voltage of the capacitor 13 at this time is sampled / held by the capacitor 21. The decoder 17 has a Hea
The analog switch 1 is detected by detecting the VFO2 period of der4.
9 is turned on, and the voltage of the capacitor 13 at this time is sampled / held by the capacitor 20.

Then, the differential amplifier 22 calculates the difference between the two voltages, outputs a voltage multiplied by an appropriate gain A, and inputs the voltage to the adjustment terminal of the balance adjustment circuit. The offset balance between the differential address signal (+) and the differential address signal (-) is changed in proportion to the voltage to adjust the composite balance.

In FIG. 4, (A) shows the waveform of the conventional circuit, and the address signal cannot be sliced below the reference voltage (VREF). On the other hand, in the present embodiment shown in (B), the differential address signal (+) is
Since the difference signal is obtained after offsetting α and the differential address signal (−) by α, the vertical balance with respect to the reference voltage (VREF) can be improved, and accurate slicing can be performed.

(Embodiment 2) Another embodiment will be described below. FIG. 5 is a block diagram of a second embodiment of the present invention. Reference numeral 23 denotes an edge detection circuit for detecting a falling edge of an address gate signal. This is a latch circuit that latches a count value. Reference numeral 25 denotes a CPU which takes in and determines the count value held by the latch circuit 24. 26 is a resistor, 27 is an NPN transistor, and 28 is a capacitor.

The operation of the optical disk device of the present embodiment configured as described above will be briefly described. At first, a relatively near outer periphery is being reproduced, and the switching signal connected from the CPU 25 to the resistor 26 is set to “L”.

When the optical pickup flows inward due to disturbance or the like, when the edge detection circuit 23 and the latch circuit 24 detect the falling edge of the address gate signal, the CPU 25 reads the latched count value. . The CPU 25 compares the count value at the predetermined time with the previously latched count value, and in this case,
Since the latched count value is larger, it is determined that the current feedback gain is larger. To explain the reason, first, the relationship between the capacitor capacity, the charging / discharging current, the charging / discharging time, and the capacitor voltage will be described below.

V = i * t / C (1) As can be seen from the equation (1), the charging / discharging time t increases due to the increase in the time of the address gate signal. Becomes larger, and the slice curve rattles. This state is shown in FIG. Therefore, the CPU 25 sets the switching signal to “H”, turns on the NPN transistor 27 and turns on the capacitor 1.
3 is connected in parallel with a capacitor 28 to increase the capacitor capacity. Thereby, the denominator of the equation (1) is increased, and the degree of change of the capacitor voltage is reduced. The collector-emitter voltage of the NPN transistor 27 is 0.2 to
There is about 0.3 V, but it can be ignored in actual operation. This state is the state shown in FIG. 6D, and the slice curve is settled, so that a binarization error at the time of address detection can be reduced.

[0047]

As described above, according to the present invention, a threshold value for slicing an upper signal and a lower signal of an address signal is accurately detected, and an offset is given to the address signal in accordance with the difference. The balance between the upper side and the lower side can be automatically adjusted. As a result, binarization can be accurately performed even when the vertical balance of the address signal is largely different due to the variation of the optical pickup or the like. Further, the time of the address signal portion can be detected, and the gain for slicing can be changed according to this time. As a result, the slice curve is settled, so that the binarization error can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an optical disk device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of an address section of the device.

FIG. 3 is a slice waveform diagram of an address portion of the device.

FIG. 4 is a timing chart for explaining the operation of the apparatus.

FIG. 5 is a block diagram of an optical disc device according to a second embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the apparatus.

FIG. 7 is a block diagram of a conventional optical disk device.

FIG. 8 is a diagram showing a phase change disk having a recording capacity of 2.6 Gbytes in the same device.

FIG. 9 is a timing chart showing tracking error signals in lands and grooves in the same device.

FIG. 10 is a timing chart for explaining the operation of the apparatus.

FIG. 11 is a timing chart for explaining a problem of the apparatus.

[Explanation of symbols]

 Reference Signs List 1 balance adjustment circuit 2 differential amplifier 3, 4 comparator 5, 7 retriggerable mono-multi 6 OR gate 8, 11 current source 9, 10, 12, 18, 19 analog switch 13, 20, 21, 28 capacitor 14 inverter DESCRIPTION OF SYMBOLS 15 Counter 16, 17 Decoder 22 Differential amplifier 23 Edge detection circuit 24 Latch circuit 25 CPU 26 Resistance 27 NPN transistor

Claims (2)

[Claims] 1. An address detecting means for extracting an address signal from a reproduction signal of an optical disk on which address information is intermittently recorded, and converting the address signal into a first binary signal at a first threshold value. A first comparing means for converting; a second comparing means for converting the address signal into a second binary signal with a second threshold; a pulse of the first and second binary signals The first feedback means and the second feedback means for changing the first and second threshold values by applying feedback to the first and second comparison means so that the average length of the width becomes equal. In the optical disc device having a balance adjustment, a DC offset value of the address signal is changed to adjust a balance between a positive amplitude and a negative amplitude of the address signal with respect to an input bias voltage of the first and second comparing means. Means Pulse counting means for counting the number of pulses of the first and second binarized signals; detecting that the number of pulses coincides with at least one or more predetermined values determined in advance; Digital comparison means for outputting the first threshold value; first sample / hold means for sampling / holding the first threshold value while the detection pulse is being output; Second sample / hold means for sampling / holding the second threshold value; and differential output means for obtaining a difference between the first and second sample / hold means and then multiplying the result by a predetermined value. Giving the output of the differential output means to the balance adjusting means as the DC offset value, and setting the absolute values of the first threshold value and the second threshold value to equal. Optical disk apparatus characterized by comprising a third feedback means for applying feedback to Kusuru so. 2. A means for detecting pulse output times of first and second binarized signals, wherein the pulse output time when reproducing the optical disc at 1 × speed is set as a predetermined time, and Means for comparing a predetermined time; and if the pulse output time is within the predetermined time, the gain of the first and second feedback means is changed to a maximum mark length signal when the pulse output time is the predetermined time. Means for setting a predetermined initial gain so as to accurately binarize the minimum mark length signal, and reducing the gains of the first and second feedback means when the pulse output time is longer than the predetermined time. The optical disk device according to claim 1, comprising: