JPH11237641A - Liquid crystal display device, its production and detecting method of defect - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor substrate having short bars which make detection of short circuit fault easy and which are not damaged by electrostatic charges by arranging plural first wirings parallel to one another, plural second wirings formed parallel to the first wirings, first and second short bars connected to the first and second wirings, and main short bars formed outside the first and second short bars. SOLUTION: First and second auxiliary short bars 410, 420 are formed between a gate short bar 200 and gate pads 110, 120 and parallel to the gate short bar 200. Third to fifth subshort bars 210, 220, 230 are formed between a data short bar 400 and data pads 510, 520 and parallel to the data short bar 400. In this structure. the first and second auxiliary short bars 410, 420 are connected to G1, G3, and G2, G4, respectively. The third to fifth auxiliary short bars 210, 220, 230 are connected to data lines D1 and D4, D2, D3, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, a method of manufacturing the same, and a defect inspection method, and more particularly, to a liquid crystal display device having two or more short bars, a method of manufacturing the same, and a pixel defect inspection method using the short bar structure. About.

[0002]

2. Description of the Related Art In a liquid crystal display device, a short bar serves to discharge static electricity generated during a manufacturing process of the liquid crystal display device, and is used to inspect an array of thin film transistors after the process is completed. Sometimes.

Hereinafter, a conventional liquid crystal display device will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic view showing a conventional thin film transistor substrate for a liquid crystal display device having a short bar, FIG. 2 is an enlarged view of a portion A in FIG. 1, and FIG. It is sectional drawing by the III 'line.

[0005] As shown in FIGS. 1 to 3, gate lines G 1, G 2, G 3,... A gate pad 10 is formed at an end of each of the gate lines G1, G2, G3,. Outside the gate pad 10, the gate short bar 20 is connected to the gate line G.
1, G2, G3, ... are united. In addition, inspection pads 2 are formed at both ends of the gate short bar 20.

The gate lines 5 (FIG. 3) including the gate lines G1, G2, G3,..., The gate pad 10, and the gate short bar 20 are covered with a gate insulating film 15. Data lines D1, D2, D3, D4,... Are formed in the vertical direction, and the data lines D1, D2, D3,.
Data pads 30 are formed at the ends of D4,. Outside the data pad 30, the data short bar 40 connects the data lines D 1, D 2, D 3, D 4,... To one, and the test pads 3 are formed at both ends of the data short bar 40. Here gate short bar 2
0 and the data short bar 40 may be connected to each other through an opening formed in the gate insulating film 15.

The data lines including the data lines D1, D2, D3, D4,..., The data pads 30, and the data short bars 40 are covered with an insulating film 25. Data pad 3
The insulating films 15 and 25 near 0 and the gate pad 10 have been removed.

In the screen display area of the liquid crystal display device, data lines D1, D2, D3, D4,... And gate lines G1, G2,.
A pixel region PX surrounded by G3,... Is formed, and a thin film transistor TFT is formed in each pixel region PX, and receives a scanning signal from the gate lines G1, G2, G3,. Data lines D1, D2, D3, D
4. It plays the role of switching the image signal from.

In the liquid crystal display device having such a structure, static electricity generated in the substrate during the manufacturing process is discharged or dispersed through the gate short bar 20 and the data short bar 40.

[0010] On the other hand, after the completion of such a manufacturing process of the liquid crystal display device, an array inspection for detecting a defect in the substrate is performed. Thereafter, the gate short bar 20 and the data short bar 40 are cut and removed with reference to the cutting line L.

Hereinafter, the principle of the conventional array inspection will be described with reference to FIGS. 1 and 4. FIG.

FIG. 4 is a diagram showing the polarity of an array test signal applied to each pixel.

As shown in FIG. 1, the short bar 20,
A voltage for array inspection is applied to 40 inspection pads 2 and 3. At this time, the gate lines G1, G2, G3, ... and the data lines D1, D2, D3, D4, ... are connected to one short bar 20, 40, respectively. At the same time, the data voltages having the same magnitude and the same polarity are applied to the respective R, G, and B pixels as shown in FIG. As a result, in the currently used normally white system, the data lines D1, D2,
The pixel area PX appears dark due to the voltage applied to D3 and D4.

On the other hand, the pixel region PX in which the gate lines G1, G2, G3,... Or the data lines D1, D2, D3, D4,. , It is possible to detect a defect in the pixel area PX.

[0015]

However, as shown in FIG. 1, when two or more gate lines or two or more data lines D2 and D3 are short-circuited to each other, this cannot be detected. This is because two data lines D2, D3
Is applied with the same polarity and magnitude.

If the short bar 40 is divided into two or more to compensate for such disadvantages, the detection power increases.
During the process, static electricity may damage the substrate.

An object of the present invention is to realize a thin film transistor substrate having a short bar which can easily detect a short circuit failure and is not vulnerable to static electricity.

Another object of the present invention is to provide an inspection method for easily detecting a short circuit between adjacent data lines or gate lines and a pixel defect.

Still another object of the present invention is to provide an inspection method capable of easily detecting a defect in a highly precise substrate.

[0020]

In order to achieve the above object, a first invention of the present application provides a plurality of first wirings parallel to each other,
A plurality of second wirings formed in parallel with the first wiring, a first short bar connected to the first wiring, a second short bar connected to the second wiring, a first and a second short bar; Provided is a liquid crystal display substrate including a main short bar formed outside a short bar.

For example, there is a liquid crystal display substrate in which a plurality of gate lines are formed in parallel with each other, and two test short bars for connecting the gate lines alternately are formed. Outside the short bar, a main short bar connecting all the gate lines into one is formed. The gate line and the test short bar may be connected by a conductive connection pattern. A number of data lines are formed perpendicular to the gate lines, and it is possible that three test short bars are alternately connected to three consecutive data lines. The bars can also be connected by a conductive connection pattern. Preferably, a data line is connected to the main short bar outside the short bar and connected to the gate line.

The second invention of the present application is the first invention of the present application,
The first and second lines provide a liquid crystal display substrate that is a gate line to which a scanning signal is applied.

The third invention of the present application is the first invention of the present application,
The first and second wirings provide a liquid crystal display substrate that is a data line to which an image signal is applied.

According to a fourth aspect of the present invention, in the first aspect of the present invention,
The main short bar provides a liquid crystal display substrate connected to the first and second wirings.

According to a fifth aspect of the present invention, in the first aspect of the present invention,
The first and second lines provide a liquid crystal display substrate that is alternately arranged.

According to a sixth aspect of the present invention, there is provided a gate insulating film having a transparent insulating substrate, a plurality of gate lines formed on the substrate in parallel with each other, and a first opening covering the gate line and exposing the gate line. A plurality of data lines formed on the gate insulating film along a direction intersecting the gate line; and a first auxiliary short bar formed at one end of the gate insulating film in a direction along the data line. , At one end of the gate insulating film,
A second auxiliary short bar formed in parallel with the first auxiliary short bar; and a second opening formed on the data line and the first and second auxiliary short bars, the second opening being formed on the first opening. A protective film having third and fourth openings respectively above the first and second auxiliary short bars, and a gate line formed on the protective film and passing through the first and second openings and the third opening. A first connection pattern respectively connected to the first and second auxiliary short bars; and a first connection pattern formed on the protective film and through the first and second openings and the fourth opening.
A liquid crystal display substrate includes a gate line not connected to the connection pattern and a second connection pattern connected to the second auxiliary short bar.

The seventh invention of the present application is the sixth invention of the present application,
In the direction along the first and second auxiliary short bars on the substrate,
And third, fourth, and fifth auxiliary short bars formed in parallel with each other, and third, fourth, and fifth connection patterns formed on the protective film. The five connection pattern provides a liquid crystal display substrate that electrically connects the data lines to the third, fourth, and fifth auxiliary short bars, respectively.

The eighth invention of the present application is the seventh invention of the present application,
The protection film has a fifth opening exposing the data line, and the gate insulating film and the protection film have sixth, seventh, and eighth openings exposing the third, fourth, and fifth auxiliary short bars, respectively. The third, fourth, and fifth connection patterns are connected to different data lines through the fifth opening, and are connected to the third, fourth, and fifth openings through the sixth, seventh, and eighth openings, respectively. A liquid crystal display substrate connected to the fifth auxiliary short bar is provided.

The ninth invention of the present application is the sixth invention of the present application,
Provided is a liquid crystal display substrate further comprising a gate short bar formed on the substrate and connected to a gate line.

A tenth aspect of the present invention provides the liquid crystal display substrate according to the sixth aspect of the present invention, further comprising a data short bar formed on the gate insulating film and connected to the data line.

According to an eleventh aspect of the present invention, in the sixth aspect of the present invention, there is provided a gate insulating film formed on a substrate, including a gate short bar connected to a gate line,
The data short bar further includes a data short bar connected to the data line, and the data short bar provides a liquid crystal display substrate electrically connected to the gate short bar.

According to a twelfth aspect of the present invention, in the sixth aspect of the present invention, the gate line is formed on the substrate in a direction along the first and second auxiliary short bars, the gate line being located outside the first and second auxiliary short bars. And a liquid crystal display substrate further including a gate short bar separated from the liquid crystal display substrate.

According to a thirteenth aspect of the present invention, in the sixth aspect of the present invention, the third, fourth, and fifth auxiliary short bars are located outside the third, fourth, and fifth auxiliary short bars and on the gate insulating film. Provided is a liquid crystal display substrate further including a data short bar formed in a direction and separated from a data line.

According to a fourteenth aspect of the present invention, in the sixth aspect of the present invention, the gate line is formed on the substrate in a direction along the first and second auxiliary short bars, the gate line being located outside the first and second auxiliary short bars. Are formed outside the gate short bar and the third, fourth, and fifth auxiliary short bars, and are formed on the gate insulating film in a direction along the third, fourth, and fifth auxiliary short bars. And a data short bar separated from the data line, wherein the data short bar provides a liquid crystal display substrate electrically connected to the gate short bar.

According to a fifteenth aspect of the present invention, a transparent insulating substrate, a plurality of gate lines formed on the substrate in parallel with each other,
A first substrate formed on a substrate in a direction along the gate line;
A first auxiliary short bar covering the auxiliary short bar, a second auxiliary short bar formed in parallel with the first auxiliary short bar on the substrate, the gate line, and the first and second auxiliary short bars; A gate insulating film having first and second openings for exposing the bars, a plurality of data lines formed in parallel with each other on the gate insulating film in a direction intersecting with the gate lines; A protective film formed on the first and second auxiliary short bars, the third and fourth openings on the first and second openings, respectively, and the fifth opening on the data line; A first connection pattern formed on the protection film, the first connection pattern being connected to the data line and the first auxiliary short bar through the first and third openings and the fifth opening. Through the fourth opening and the fifth opening, The second, which is connected to the not connected to the connection pattern data line and the second auxiliary short bars
A liquid crystal display substrate including a connection pattern.

A sixteenth aspect of the present invention provides the liquid crystal display substrate according to the fifteenth aspect of the present invention, further comprising a gate short bar formed on the substrate and connected to the gate line.

A seventeenth aspect of the present invention provides the liquid crystal display substrate according to the fifteenth aspect of the present invention, further comprising a data short bar formed on the gate insulating film and connected to the data line.

According to an eighteenth aspect of the present invention, in the fifteenth aspect of the present invention, a gate short bar formed on the substrate and connected to the gate line, and a data short bar formed on the gate insulating film and connected to the data line. And a bar, wherein the data short bar is electrically connected to the gate short bar.

According to a nineteenth aspect of the present invention, in the fifteenth aspect of the present invention, the semiconductor device is located outside the first and second auxiliary short bars, is formed on the gate insulating film in a direction along the gate line, and is separated from the data line. A liquid crystal display substrate further including a data short bar.

A twentieth aspect of the present invention provides the liquid crystal display substrate according to the fifteenth aspect of the present invention, further comprising a gate short bar formed on the substrate along the data line and separated from the gate line.

According to a twenty-first aspect of the present invention, in accordance with the fifteenth aspect of the present invention, the semiconductor device is located outside the first and second auxiliary short bars, is formed on the gate insulating film in a direction along the gate line, and is separated from the data line. The data short bar further includes a gate short bar formed on the substrate in a direction along the data line and separated from the gate line, wherein the gate short bar is electrically connected to the data short bar. A display substrate is provided.

The twenty-second invention of the present application includes a step of laminating a metal layer on a transparent insulating substrate; a step of patterning the metal layer to form a gate line; a step of forming a gate insulating film on the gate line; Forming first and second auxiliary short bars for testing a gate line and a data line on the insulating film, laminating a protective film, etching the protective film and the gate insulating film to form a gate line; Forming a first opening and second and third openings respectively exposing the first and second auxiliary short bars; depositing a transparent conductive layer; patterning the transparent conductive layer; A first connection pattern connected to the gate line and the first short bar through the first and second openings, and a second connection pattern connected to the gate line and the second short bar through the first and third openings.
A method of manufacturing a liquid crystal display substrate includes a step of forming a connection pattern and a pixel electrode.

In such a method of manufacturing a liquid crystal display device, the conductive connection pattern is formed at the stage of forming the transparent pixel electrode. After forming the transparent conductive connection pattern,
It is also possible to remove some of the gate lines and data lines inside the main short bar.

The twenty-third invention of the present application provides the method of manufacturing a liquid crystal display substrate according to the twenty-second invention of the present application, further comprising a step of patterning a metal layer and forming a short bar for preventing static electricity connected to the gate line.

According to a twenty-fourth aspect of the present invention, there is provided a method of manufacturing a liquid crystal display substrate according to the twenty-third aspect of the present invention, further comprising the step of removing the connection between the antistatic short bar and the gate line after forming the connection pattern.

In such a method of manufacturing a liquid crystal display substrate, two or more gate auxiliary short bars or two or more data auxiliary short bars are formed and separated from the gate short bar and the data short bar after the process is completed. , Not only is it not vulnerable to static electricity,
It is easy to detect a short-circuit failure in the substrate.

According to a twenty-fifth aspect of the present invention, there are provided a step of forming first, second and third auxiliary short bars for testing gate lines and data lines on a substrate, a step of forming a gate insulating film, and a step of forming a gate insulating film. Laminating a metal layer on the film, patterning the metal layer to form a data line, laminating a protective film, etching the protective film and the gate insulating film to form a data line and the first line. A first opening exposing the second and third auxiliary short bars and second, third and fourth openings.
Forming an opening, depositing a transparent conductive layer, and patterning the transparent conductive layer to form a data line and the first to third auxiliary short bars through the first and second to fourth openings. Forming a connection pattern and a pixel electrode to be connected to each other.

According to a twenty-sixth aspect of the present invention, there is provided a method of manufacturing a liquid crystal display substrate according to the twenty-fifth aspect of the present invention, further comprising the step of patterning a metal layer and forming a short bar for preventing static electricity connected to the data line.

According to a twenty-seventh aspect of the present invention, there is provided a method of manufacturing a liquid crystal display substrate according to the twenty-sixth aspect of the present invention, further comprising removing a connection between the antistatic short bar and the data line after forming the connection pattern.

According to a twenty-eighth aspect of the present invention, a plurality of gate lines and data lines, a main antistatic short bar connected to the gate lines and data lines, and a gate alternately connected to the gate lines are provided on the substrate. Forming first and second auxiliary short bars for testing, and third and fourth auxiliary short bars for data testing alternately connected to the data lines, and separating the main short bar from the gate and the data lines. Applying a voltage to the first and second auxiliary short bars and the third and fourth auxiliary short bars,
Detecting a defect included in the data line and / or the gate line.

According to a twenty-ninth aspect of the present invention, there is provided a method of manufacturing a liquid crystal display substrate according to the twenty-eighth aspect of the present invention, wherein different voltages are respectively applied to the first auxiliary short bar and the second auxiliary short bar.

According to a thirtieth aspect of the present invention, there is provided a method of manufacturing a liquid crystal display substrate according to the twenty-eighth aspect of the present invention, wherein different voltages are applied to the third auxiliary short bar and the fourth auxiliary short bar.

A thirty-first invention provides a method of manufacturing a liquid crystal display substrate according to the twenty-eighth invention, further comprising a step of removing the first, second, third, and fourth auxiliary short bars after the failure detection step. I do.

The thirty-second invention of the present application is directed to a plurality of R, G, and B pixels, first and second gate lines which are divided into even-numbered and odd-numbered pixels, and connected to R, G, and B pixels, respectively. A liquid crystal display substrate having a plurality of data lines divided and connected, wherein a first pulse is applied to a first gate line, and a second pulse is applied to the second gate line at a timing different from the first pulse. And applying a first
In the step of applying the pulse, the first and second signals having the same polarity are applied to the first and second data lines adjacent to each other among the three data lines sequentially arranged, and A third signal having a polarity different from that of the first and second signals is applied to the remaining third data lines except for the first and second data lines. 3 Apply the first and second signals to the data lines,
An inspection method of a liquid crystal display device, in which a third signal is applied to a data line, is provided.

For example, a pulse signal is applied to two adjacent gate lines using two test auxiliary lines and three test auxiliary lines, and two of the three adjacent data lines are used. Are applied with signals of the same polarity.
A signal having a polarity opposite to the polarity of the signal applied to the two data lines is applied to the remaining one data line. Next, a signal having the same polarity is applied to two data lines selected in a combination different from the above, and a signal having a polarity opposite to this signal is applied to the other data line.

In order to improve the reliability of the test, another test mode in which the polarity of the signal and the polarity reversal time are changed in such a manner that a signal applied to each data line is transferred to an adjacent data line is applied. It is also possible.

In the method for inspecting a liquid crystal display device according to the present invention, a short circuit between adjacent pixels or adjacent lines can be detected, and the detection power and reliability of display defects are improved.

A thirty-third aspect of the present invention provides a method for inspecting a liquid crystal display device according to the thirty-second aspect of the present invention, wherein the first pulse and the second pulse are applied periodically and with a time difference of half a cycle. I do.

According to a thirty-fourth aspect of the present invention, in the thirty-second aspect of the present invention, a step of applying a third pulse to the first gate line;
Applying a fourth pulse to the gate line at a different timing from the third pulse, wherein applying the third pulse includes applying the first and second signals to the second and third data lines. A third signal is applied to one data line,
In the step of applying a pulse, a method for testing a liquid crystal display device is provided in which first and second signals are applied to first and third data lines and a third signal is applied to a second data line.

According to a thirty-fifth aspect of the present invention, in the thirty-fourth aspect of the present invention, there is provided a method for inspecting a liquid crystal display device, wherein the third pulse and the fourth pulse are applied periodically and with a time difference of half a cycle. I do.

The thirty-sixth invention of the present application is directed to a plurality of R, G, and B pixels, first and second gate lines that are divided into even-numbered and odd-numbered pixels and connected to the R, G, and B pixels, respectively. A liquid crystal display substrate having a plurality of data lines divided and connected, wherein a first pulse is applied to a first gate line, and a second pulse is applied to a second gate line at a timing different from the first pulse. Applying a first pulse, wherein in the step of applying the first pulse, the first and second data lines adjacent to each other among the three data lines arranged consecutively have a first polarity. 1st inversion with one inversion cycle
A signal is applied to the third data line except for the first and second data lines among the three data lines, and the third data line is inverted at a first inversion cycle, and the second signal line has a polarity opposite to the first signal. A method for testing a liquid crystal display device, comprising applying a signal and applying a second pulse, applying a second signal to first and second data lines and applying a first signal to a third data line.

According to a thirty-seventh aspect of the present invention, in the thirty-sixth aspect of the present invention, a step of applying a third pulse to the first gate line,
Applying a fourth pulse to the gate line at a different timing from the third pulse, wherein applying the third pulse includes applying a first signal to the first and third data lines, Applying a second signal to the line;
A method of testing a liquid crystal display device, comprising applying a first signal to a second data line and applying a second signal to first and third data lines in the step of applying a pulse.

According to a thirty-eighth aspect of the present invention, in the thirty-seventh aspect of the present invention, there is provided a method of inspecting a liquid crystal display device, wherein the first pulse and the second pulse or the third pulse and the fourth pulse are applied with a time difference of a half cycle from each other. .

A thirty-ninth aspect of the present invention provides the liquid crystal display device inspection method according to the thirty-seventh aspect of the present invention, wherein the timings at which the first to fourth pulses are applied are timings at which the first and second signals are inverted.

According to a fortieth aspect of the present invention, in the thirty-seventh aspect of the present invention, there is provided a method of inspecting a liquid crystal display device, wherein the first inversion period is equal to the width of the first to fourth pulses.

A forty-first invention provides a method for inspecting a liquid crystal display device according to the thirty-seventh invention, wherein the first inversion cycle is twice the width of the first to fourth pulses.

A forty-second invention provides a method for inspecting a liquid crystal display device according to the thirty-seventh invention, wherein the first to fourth pulses are applied after the timing when the first and second signals are inverted.

According to a forty-third aspect of the present invention, in the thirty-seventh aspect of the present invention, the first to fourth pulses are applied after the timing when the first and second signals are inverted, and the first inversion cycle is the width of the first to fourth pulses. An inspection method for a larger liquid crystal display device is provided.

[0069]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, a liquid crystal display substrate and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to FIG.

FIG. 5 is a schematic view showing a wiring in a thin film transistor substrate for a liquid crystal display device having a short bar according to an embodiment of the present invention, in which an antistatic wiring and a wiring for inspecting a substrate failure are not removed. 3 shows the wiring of the liquid crystal display device in a state.

The gate lines G1, G2, G3, G4
Are formed of a material such as aluminum, and gate pads 110, 120, 130, 140,... Are formed at the ends of the gate lines G1, G2, G3, G4, respectively. Also, data lines D1, D2 with gate lines G1, G2, G3, G4... And an insulating film (not shown) interposed therebetween.
2, D3, D4... Are formed in a vertical direction with a material such as chromium or molybdenum, and data lines D1, D2, D3,.
Data pads 510, 520, 5
Are formed.

Gate pads 110, 120, 130, 1
40 and data pads 510, 520, 530, 540
Are displayed in the screen display area A inside the data lines D1, D2.
2, D3, D4... And gate lines G1, G2, G3, G4.
Are formed so as to intersect with the pixel region PX. Each pixel area PX has a thin film transistor TF
T is formed. The TFT has gate lines G1, G2,
Receive scanning signals from G3, G4,.
2, D3, D4,...

The static electricity generated during such a wiring forming process causes the thin film transistors TFT or the wirings G1, G2... D1, D2... In the pixel region PX to be defective. Bar 200 and 400 patterns are formed as follows.

Gate pads 110, 120, 130, 1
The vertical gate short bars 200 formed of the same metal as the gate lines outside the gate pads 1.
Are connected to gate extensions 101, 102, 103, 104,... Extending in the lateral direction from 10, 120, 130, 140,. Data pads 510, 520, 530,
Data short bars 400 are formed in the horizontal direction outside of 540... Of the same metal as the data lines, and data extension portions 501, 502, and 520 extending from the data pads 510, 520, 530, 540. 503, 504 ...
Is linked to The gate short bar 200 and the data short bar 400 are connected to each other through a contact hole opened in an insulating film therebetween.

The short bars 200, 4
00, the static electricity generated in the substrate is dispersed and discharged, and after all the wiring steps of the substrate are completed, the substrate is cut along the cutting line L1 to remove the gate and data short bars 200 and 400. .

Thereafter, an array inspection in the pixel display area of the substrate is performed.

At this time, the gate and data short bar 2
Auxiliary short bar 4 formed inside 00, 400
Inspection is performed using 10, 420; These auxiliary short bars 410, 420; 2
The structures of 10, 220 and 230 are as follows.

First and second auxiliary short bars 410, 4
20 is a gate short bar 200 and a gate pad 11
Are formed in parallel with the gate short bar 200 with the same metal as the data line between the data short bar 400 and the data pad 51.
0 to 520, 530, 540,...
Auxiliary short bars 210, 220 and 230 are formed in the same metal as the gate lines in parallel with the data short bar 400. At this time, the first and second auxiliary short bars 41
0, 420 are odd-numbered gate lines G1, G3,.
And the even-numbered gate lines G2, G4,.
Third to fifth auxiliary short bars 210, 220, 230
Are (3n-2) th data lines D1, D4,.
(3n-1) th data lines D2... And 3nth data lines D3.

Therefore, different signals are respectively supplied to the first auxiliary short bar 410 connected to the odd-numbered gate lines G1, G3,... And the second auxiliary short bar 420 connected to the even-numbered gate lines G2, G4,. , And the data lines D1, D2, D3, D4... Are divided into three groups using the third, fourth, and fifth auxiliary short bars 210, 220, and 230, and the R, G, and B signals are respectively divided into three groups. To inspect for defects in the substrate.

Hereinafter, the gate short bar 200 and the first and second auxiliary short bars 41 will be described with reference to FIGS.
0, 420, data short bar 400 and third, fourth,
The specific structure of the fifth auxiliary short bars 210, 220, 230 will be described in more detail.

FIGS. 6 and 7 are enlarged views of a portion B surrounded by a chain line in FIG. 5, that is, a gate short bar portion according to the first and second embodiments. FIG. 8 is a cross-sectional view taken along the line VIII-VIII 'of FIG. 7, and particularly shows a connection structure between the gate short bar and the auxiliary short bar.

Gate Pad 1 Formed on Substrate 1
The gate extension 1 extends from 10, 120, 130... To the gate short bar 200 formed on the substrate 1 in the vertical direction.
01, 102, 103 ... are extended. A gate insulating film 150 is formed on the gate extension. On the gate insulating film 150, first and second auxiliary short bars 410, 420 are formed in parallel with the gate short bar 200 and between the gate pads 110, 120, 130,. I have. A protective film 250 is formed on the auxiliary short bar.

.. Are connected to the first auxiliary short bar 410 or the second auxiliary short bar 420, and a connection pattern 310 made of the same material as that of the pixel electrode (not shown) is provided above the portion where the gate extension 101, 102, 103. , 3
20 are formed (FIG. 8). This connection pattern 31
Reference numerals 0 and 320 denote openings a opened in the protective film 250 above the first auxiliary short bar 410 and openings b opened in the gate insulating film 150 and the protective film 250 above the gate extension 101.
And the first auxiliary short bar 410 and the gate extension 101 respectively. In addition, the connection patterns 310 and 320 are respectively formed through an opening c opened in the protective film 250 above the second auxiliary short bar 420 and an opening d opened in the gate insulating film 150 and the protective film 250 above the gate extension 102. The second auxiliary short bar 420 is in contact with the gate extension 102. That is, the respective gate extensions 101 and 102 are electrically connected to the first and second auxiliary short bars 410 and 420, respectively.

As described above, by cutting the substrate 1 along the cutting line L1 before performing the array inspection, the gate short bar 200 is replaced with the auxiliary short bar 410,4.
After the inspection is completed, the cutting line L located outside the gate pads 110, 120 and 130 is electrically separated from the gate pad 110.
By cutting the substrate 1 along 2, the auxiliary short bars 410 and 420 are removed to finish the manufacture of the substrate.

The second embodiment shown in FIG. 7 has a structure in which it is not necessary to cut the substrate to separately remove the gate short bar 200 before the array inspection.

In the case of the second embodiment, the first and second auxiliary short bars 410, 420 and the gate extensions 101, 10
The connection form with 2, 103... Is the same as in the first embodiment.
However, partial gate extensions 101 and 102 between the gate short bar 200 and the first auxiliary short bar 410,
103, the gate insulating film 150 and the protective film 250 are removed, so that the respective gate extensions 101, 1
Are separated from the gate short bar 200. At this time, the gate extensions 101, 102,
103 and the gate short bar 200 are separated at the end of the substrate manufacturing process. This will be described later.

As described above, in the second embodiment, the gate short bar 200 and the auxiliary short bars 410, 420
Are separated from each other, so that there is no need to cut the substrate 1 before the array inspection.

Instead, when the inspection is completed, the substrate 1 is cut along the cutting line L2 in the same manner as in the above-described embodiment, so that the short bar 200 and the auxiliary short bar 4 are cut.
10, 420 are removed simultaneously.

FIG. 9 is an enlarged view of a portion C surrounded by a chain line in FIG. 5, that is, a data short bar portion. FIG. 10 is a cross-sectional view taken along the line XX 'of FIG. 9, and shows the connection between the data short bar and the third, fourth, and fifth auxiliary short bars.

As shown in FIGS. 9 and 10, the third, fourth and fifth auxiliary short bars 2 are made of the same metal as the gate wiring.
10, 220, 230 are formed on the substrate 1 in the horizontal direction in the figure. Gate insulating film 150 on the auxiliary short bar
Are laminated. The data line D is formed on the gate insulating film 150.
1, D2, D3, D4 ..., data pads 510, 52
0, 530, 540,..., Data extension units 501, 502,
503, 504... And a data wiring 55 such as a data short bar 400 connected to the data extension part. A protective film 250 is formed thereon.

As shown in FIG. 10, the openings f, h, j
Are formed on the protective film 250 above the data extension portions 501, 502, 503,. Openings g, i,
k is the third, fourth and fifth auxiliary short bars 210 and 22
The gate insulating film 150 and the protective film 2 above 0, 230...
50 are formed. The connection patterns 301, 302, and 303 formed on the passivation layer 250 are connected to third, fourth, and fifth auxiliary short bars 210, 220, and 230 through openings f, h, and j; g, i, and k, respectively. And data extension units 501, 502, 503,...

Similarly to the case of the gate short bar 200, the data extension portions 501, 502, 503,... And the opening 1 in which a part of the protective film 250 is opened are formed inside the data short bar 400. Extension 501,
.., 502, 503, 504,...
However, in this case, a substrate cutting step for separating the data short bar 400 for array inspection is not required.

Thus, the three auxiliary short bars 21
. Are connected to the data lines D1, D2, D3,... Alternately to 0, 220, 230, respectively. Third, fourth,
Different signals may be applied to the fifth auxiliary short bars 210, 220, and 230, respectively.

When two or more data lines, for example, two data lines D3 and D4 are short-circuited as shown in FIG.
3) When a different voltage is applied to each of the data lines D3 and D4, a pixel connected to the two data lines D3 and D4 has a brightness different from that of the other pixels, so that a short circuit can be easily found.

Although this embodiment has three separate auxiliary short bars 210, 220 and 230, it is also possible to form two or three or more auxiliary short bars.

Hereinafter, a method of manufacturing a liquid crystal display device having a short bar structure according to an embodiment of the present invention will be described with reference to FIGS. 5, 11 to 16, and 17 to 22.

FIGS. 11 to 16 are sectional views taken along the line VIII-VIII 'of FIG. 7, and are shown in the order of steps. 17 to 22 are cross-sectional views taken along line XX 'of FIG. 9, and are shown in the order of steps.

As shown in FIGS. 11 and 17, a metal layer 50 for a gate wiring is formed on a transparent insulating substrate 1, and gate lines G1, G2, G3, G4,. 130 ..., gate short bar 20
0, a gate wiring 5 including gate extensions 101, 102, 103... And auxiliary short bars 210, 220, 230
0 is patterned. After that, the gate insulating film 150,
An amorphous silicon film (not shown) and an n ⁺ amorphous silicon film (not shown) are continuously stacked, and the upper two layers are photo-etched to form a pattern in the pixel PX.

Next, as shown in FIGS. 12 and 18,
A metal layer 55 for data wiring is formed to form a data line D
, D2, D3, D4... And source-drain electrodes (not shown), data pads 510, 520, 530.
Data short bar 400, data extension parts 501, 50
2, 503, 504 ... and auxiliary short bars 410, 4
The data wiring 55 including 20 is patterned. Next, the n ⁺ amorphous silicon film is etched using the data wiring 55 as a mask.

As shown in FIGS. 13 and 14, and FIGS. 19 and 20, a protective film 250 is laminated thereon and then etched together with the gate insulating film 150 to form the gate pad 11.
., 520, 530,.
E; l and each auxiliary short bar 41
0, 420; 210, 220, 230, gate and data extension units 101, 102 ...; 501, 502, 503 ...
Openings a, b, c, d, e, f, g, h,
Form i, j, k.

Then, as shown in FIGS. 15 and 21,
A pixel electrode (not shown) is formed in the pixel area PX by laminating and etching the ITO material. In this process, IT
O connection patterns 310, 320, 301, 302, 30
3 are also formed. The ITO connection patterns 310 and 320
Auxiliary short bar 41 through openings a, b, c, d
0, 420 and the gate extensions 101, 102,. Other connection patterns 301, 302, 30
3 are alternately connected to the remaining auxiliary short bars 210, 220, 230 and the three data extensions 501, 504, 502,... Through openings f, g, h, i, j, k.

Finally, as shown in FIG. 16, the gate short bar 200 and the gate extensions 101, 102, 103
... and the auxiliary short bar 410 and the gate short bar 2
Separate from 00. As shown in FIG. 22, the data short bar 400 and the data extension units 501 and 502,
503 are separated between the auxiliary short bar 210 and the data short bar 400.

[0104] Such a separation process is performed as follows. The gate extensions 101, 102, 103,... Located between the auxiliary short bar 410 and the gate short bar 200 and the data extension located between the auxiliary short bar 210 and the data short bar 400 during the etching of the passivation layer 250. The parts 501, 502, 503 ... are exposed. Next, the connection patterns 301, 302, 303; 31
, And the data extensions 501,
Are removed by etching. Of course, the connection patterns 301, 30
2, 303; 310 and 320, the gate short bar 200 and the data short bar 400 can be cut and separated along the cutting line L1 before performing the array inspection of the substrate.

As described above, adjacent gate lines are divided and connected to two different auxiliary short bars, and three adjacent continuous data lines are divided into three different auxiliary short bars. The display quality of the liquid crystal display substrate can be inspected by using the 2G3D structure that is connected to the LCD panel.

Hereinafter, the connection structure of the auxiliary short bar, the data line, and the gate line for performing the inspection will be further described with reference to FIG.

As shown in FIG. 23, a plurality of gate lines G
, And a plurality of pixels P arranged in the row direction and the column direction, in which the plurality of data lines D1, D2, D3, D4, D5, D6.
X is formed.

The odd-numbered gate lines G1, G3, G5,.
, And even-numbered gate lines G2, G4, G6,.
0, so that different signals can be applied to even-numbered and odd-numbered pixel rows, respectively.

.., (3n−2) -th data lines D1, D4,.
1) th data lines D2, D5,.
3, D6... Are respectively connected to three R, G, B pixel columns that are continuously arranged. Also,
Third to fifth auxiliary short bars 210, 220, 230
Therefore, different signals can be applied to three adjacent pixel columns through the auxiliary short bars 210, 220, and 230, respectively.

The respective auxiliary short bars 410, 42
0; 210, 220, 230 are formed with test pads 4, 5; 6, 7, 8 for applying test signals.

Hereinafter, FIGS. 23, 24, 25 and 27 will be described.
The display inspection method according to the first embodiment will be described with reference to FIG.

FIG. 24 is a waveform diagram of signals applied to the gate line and the data line through each auxiliary short bar. FIGS. 25 to 27 are diagrams showing the signal polarities of the R, G, and B pixels in each of the modes mode1, mode2, and mode3 to which different signals are applied.

That is, through the first to fifth auxiliary short bars 410, 420; 210, 220, 230, odd-numbered gate lines and G1, G3,.
G4 ..., (3n-2) th data lines D1, D4 ..., (3
n-1) th data lines D2, D5 ... and 3n-th data lines D3, D6 ..., respectively _{G odd, G even, D R} , D G,
Apply the _DB signal voltage.

Hereinafter, each signal voltage will be described in more detail.

First and second auxiliary short bars 410, 4
Signal voltages G _odd and G _even shown in FIG. 24 are applied to _odd- numbered gate lines and even-numbered gate lines through 20, respectively. Each of the signal voltages G _odd and G _even includes a pulse for turning on the thin film transistors of the odd-row and even-row pixels. When one cycle is defined as the period after one pulse is applied until the next pulse is applied, the signal voltage G _even applied to the _even- numbered gate lines is equal to the signal voltage G _odd applied to the odd-numbered gate lines. It has a time difference of about a half cycle.
Accordingly, the thin film transistors of the pixels in the odd-numbered pixel rows conduct with a half-cycle time difference from the odd-numbered pixel rows.

On the other hand, the polarity of the signal voltages D _R , D _G , and D _B applied to the R, G, and B pixel columns is inverted once per cycle, and the inversion timing is the odd-numbered or even-numbered gate line. This is the time when the pulse applied to rises. More specifically, the signal voltages applied to two of the R, G, and B pixel columns have the same inversion timing and opposite polarities. For example, in FIG. 24, the polarity of the signal voltage applied to two pixel columns is inverted when a pulse is applied to the even-numbered gate lines, and the polarities are opposite to each other. In addition, the polarity of the inspection signal applied to the remaining one pixel column is inverted when a pulse is applied to the odd-numbered gate line.

FIG. 24 shows signals of three modes satisfying such conditions.

First, in the first mode mode1,
Test signal D _G applied to the test signal D _R and G pixel column are applied to the R pixel row have opposite polarities, inverted when the pulse is applied to the even-numbered gate lines. B
Test signal D _B applied to the pixel column is inverted when the pulse is applied to the odd-numbered gate lines. Test signal D _R when starting the first period 1F, the polarity of the D _G and D _B, respectively (+) and (- -) and ().

Next, in the second mode mode2,
Inspection signals D _R , D _G , D _B applied to the R, G, B pixel columns
Are B, R, and G in the first mode mode1, respectively.
Test signal D _B applied to the pixel, D _R, it is the same as D _G.

In the third mode mode3,
Inspection signals D _R , D _G , D _B applied to the R, G, B pixel columns
Are G, B, and R in the first mode mode1, respectively.
It is the same as the test signal applied to the pixel.

Hereinafter, the polarity of each pixel when such a signal is applied to each pixel will be described.

First, when a pulse is applied to the odd-numbered gate line, the thin-film transistor of the pixel in the odd-numbered row in the drawing is turned on, and a test signal flowing along each data line is applied to the pixel through the thin-film transistor. . Next, when the above-mentioned thin film transistor is turned off and a pulse is applied to the even-numbered gate line in the figure, the inspection signal is applied to the pixels in the even-numbered row in the figure through a similar process.

Therefore, the polarity of each pixel during the first period 1F in the first to third modes is as shown in FIGS. 25 to 27, and the polarity is opposite to that during the second period 2F. become.

First, as shown in FIG. 25, in the first mode mode1, the pixels of the R and G pixel columns have (+) and (-) polarity signals alternately appearing along the column, respectively. All pixels in the column exhibit a (-) polarity. When viewed along the rows, the G and B pixels in the odd-numbered rows have the same polarity, and the R pixels have the opposite polarity. However, in the even-numbered rows, the B and R pixels have the same polarity and G The pixel has the opposite polarity.

Next, as shown in FIG. 26, in the second mode mode2, the pixels of the G and B pixel columns have (+) and (-) polarity signals alternately appearing along the columns, respectively. All pixels in the R pixel column exhibit a (-) polarity. When viewed along the rows, the B and R pixels in the odd-numbered rows have the same polarity, and the G pixels have the opposite polarity. However, in the even-numbered rows, the R and G pixels have the same polarity, and The pixel has the opposite polarity.

Further, as shown in FIG. 27, in the third mode mode 3, the pixels of the R and B pixel columns have (+) and (-) polarity signals alternately appearing along the columns, respectively. All pixels in the pixel column exhibit a (-) polarity. When viewed along the row, the R and G pixels in the odd-numbered row have the same polarity, and the B pixel has the opposite polarity. However, in the even-numbered row, the G and B pixels have the same polarity and R The pixel has the opposite polarity.

First, even if only one of the three modes is applied, a short circuit between two adjacent gate lines or data lines can be detected. When a short circuit occurs between adjacent pixels to which signals having different polarities are applied, the same voltage corresponding to an average value of voltages applied to the two pixels is applied to the two pixels. As a result, the display of the same gradation is performed in the adjacent pixel where the short circuit has occurred, so that the short circuit defect can be determined. Further, when a short circuit occurs between adjacent wirings, the same signal is applied to all pixels in the row or column to which the wiring is connected, so that it can be seen that a short circuit between wirings has occurred.

However, a short circuit between adjacent pixels to which the same inspection signal is applied cannot be detected, and it is difficult to accurately detect the position of the short circuit.

In order to solve such a problem, when inspection is performed by applying any two of the three modes, signals having different polarities at least once between pixels adjacent in the row or column direction. Is applied, a pixel defect such as a short circuit between adjacent pixels can be easily detected, and a position where the defect has occurred can be more easily detected.

Further, the defect detection according to the first embodiment is performed.
In the method of applying signals for inspection,
The signals applied to the short bars 210, 220, 230
No. D _R, D_G, D_BPolarity is maintained for one cycle
Inspection of screen uniformity with relatively little pixel fluctuation
It is effective for

Hereinafter, the display inspection method according to the second embodiment will be described with reference to FIGS. 28, 29 and 30.

FIG. 28 is a waveform diagram of the inspection signal applied to the gate and the data line. FIGS. 29 and 30 show R, G, and B according to respective signal modes applied to the data lines.
FIG. 3 is a diagram illustrating the polarity of a pixel.

The first and second auxiliary short bars 410, 4
20 and third to fifth auxiliary short bars 210, 220,
Through 230, the odd and even gate lines and (3
n-2), (3n-1) and 3n-th data line,
The signal voltages G _odd , G _even , D _R , D _G , and D _B shown in FIG. 28 are respectively applied.

As in the first embodiment described above, if one cycle is defined as the period after one pulse is applied and the next pulse is applied, the voltage G applied to the even-numbered gate line is defined as one cycle.
_even is the signal voltage G _odd applied to the odd-numbered gate line.
And a phase difference of about a half cycle. Therefore, the thin film transistors in the odd-numbered rows of pixels conduct with the thin-film transistors in the even-numbered rows with a phase difference of about a half cycle.

On the other hand, the polarity of each of the test signal voltages D _R , D _G , and D _B applied to the R, G, and B pixel columns is inverted many times in one cycle with the same cycle as the pulse width. The test signal is also inverted once at the time when the pulse is applied to the odd-numbered gate line and at the time when the pulse is applied to the even-numbered gate line, and the polarity of the test signal at the time when the pulse is applied to the odd-numbered gate line is The polarity is opposite to the polarity of the test signal at the time when the pulse is applied to the even-numbered gate lines.
The same signal is applied to two of the R, G, and B pixel columns, and a signal having a polarity opposite to the signal applied to the two pixel columns is applied to the remaining one pixel column.

FIG. 28 shows signals of two modes satisfying such conditions.

First, in the fourth mode mode 4, R
The pixel columns and B pixel column and applying the same test signal D _R, D _B having the same polarity and the same inversion cycle, the test signal to the remaining G pixel columns in opposite polarity have the same inversion period D _{Apply G.}

Next, in the fifth mode mode 5, R
The same inspection signal is applied to the pixel column and the G pixel column, and inspection signals of opposite polarity are applied to the remaining B pixel columns.

FIGS. 29 and 30 show the polarity of each pixel when the signals in the fourth and fifth modes are applied to the pixel.

In the fourth mode shown in FIG. 29, adjacent pixels have different polarities when viewed in the column direction. When viewed in the row direction, all adjacent pixels except the adjacent B and R pixels exhibit different polarities.

In the fifth mode shown in FIG. 30, pixels adjacent in the column direction have different polarities, and in the row direction, the remaining pixels except for the adjacent R and G pixels have different polarities. Manifest.

As in the first embodiment, the short-circuit defect can be detected in only one of the two modes of the second embodiment, but all the fourth and fifth modes are applied. In such a case, since the detection power is high, a pixel defect such as a short circuit between adjacent pixels exhibiting the same polarity can be found.

In the defect detection method according to the second embodiment of the present invention, the polarity of the inspection signal applied to R, G, and B is inverted at the same period as the gate pulse width, so that R,
In some cases, the G and B signals are replaced, and the signals are not sufficiently charged in the pixels, so that flicker appears. In addition, since separation phenomena for even-numbered and odd-numbered gate lines are remarkably exhibited, it may be inappropriate in a screen uniformity inspection mainly confirmed by eyes. Also, it is difficult to detect a high or off pixel defect.

An inspection waveform according to the third embodiment for improving this is shown in FIG.

In FIG. 31, signals G _odd , G _even and R, G,
The signals D _R , D _G , and D _B applied to the B pixel column are almost the same as those in the second embodiment. However, the signals applied to the R, G, and B pixel columns are inverted at a period corresponding to twice the gate pulse width.

Therefore, there is no difficulty in charging the R, G, B signals in the pixel, the synchronization between the gate pulse and the data signal is easy, and the flicker is reduced. Is done. That is, the detection power is improved such that the defect in the high and off states is more easily detected than in the second embodiment and is suitable for the uniformity inspection.

FIG. 32 is a test signal waveform diagram according to the fourth embodiment of the present invention. As in the above-described embodiment, a signal is applied to the odd-numbered and even-numbered gate lines so that the pulses are synchronized with a half cycle difference, and the data line corresponds to twice the gate pulse width. An inspection signal whose polarity is inverted with time as a cycle is applied.

However, the gate pulse is set to R,
The inspection signal has a large initial value in the R, G, and B pixels at the moment when the gate is opened, when the signals D _R , D _G , and D _B applied to the G and B pixel columns are applied after the inverting times t1 and t2. To be charged. Accordingly, the time required for charging is reduced, and sufficient charging can be performed while the same gate pulse is applied. Therefore, the inspection can be easily performed even in the case of a highly precise substrate.

[0149]

As described above, in the liquid crystal display device according to the present invention, two or more gate auxiliary short bars or two or more data auxiliary short bars are formed. After the process is completed, the liquid crystal display substrate is separated from the gate short bar and the data short bar, so that the substrate is not vulnerable to static electricity. Also, separate inspection signals can be applied to each of the two gate auxiliary short bars and the data auxiliary short bar,
The defect detection power in the substrate is improved. As a result, the manufacturing cost can be reduced by discarding the defective substrate in the inspection stage without proceeding to the next stage. In addition, the data line signal is applied in advance from the time when the pulse applied to the gate line is turned on so that the data line signal is sufficiently applied, so that a highly precise substrate can be easily manufactured. Can be inspected.

[Brief description of the drawings]

FIG. 1 is a view illustrating a thin film transistor substrate for a liquid crystal display having a short bar structure according to the related art.

FIG. 2 is an enlarged plan view of a portion A in FIG. 1;

FIG. 3 is a sectional view taken along the line III-III ′ of FIG. 2;

FIG. 4 is a diagram illustrating a state where an array inspection signal is applied to pixels in a matrix form.

FIG. 5 is a view illustrating a thin film transistor substrate for a liquid crystal display device having a short bar according to the present invention;

FIG. 6 is an enlarged plan view showing a portion B in FIG. 5;

FIG. 7 is another plan view showing a portion B in FIG. 5 in an enlarged manner.

FIG. 8 is a sectional view taken along line VIII-VIII 'of FIG.

FIG. 9 is an enlarged plan view showing a portion C in FIG. 5;

FIG. 10 is a sectional view taken along line XX ′ of FIG. 9;

FIG. 11 is a cross-sectional view illustrating a method of manufacturing the liquid crystal display device according to the present invention, centering on the gate short bar, in the order of the steps.

FIG. 12 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to the present invention, focusing on a gate short bar, in the order of the steps.

FIG. 13 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to the present invention, focusing on a gate short bar, in the order of the steps.

FIG. 14 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to the present invention, centering on a gate short bar, in the order of the steps.

FIG. 15 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to the present invention, focusing on a gate short bar, in the order of the steps.

FIG. 16 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to the present invention, focusing on a gate short bar, in the order of the steps.

FIG. 17 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to the present invention, focusing on a data short bar, in the order of the steps.

FIG. 18 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to the present invention, focusing on a data short bar, in the order of the steps.

FIG. 19 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to the present invention, focusing on a data short bar, in the order of steps.

FIG. 20 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to the present invention, focusing on a data short bar, in the order of steps.

FIG. 21 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to the present invention, focusing on a data short bar, in the order of steps.

FIG. 22 is a cross-sectional view illustrating a method of manufacturing the liquid crystal display device according to the present invention, focusing on the data short bar, in the order of the steps.

FIG. 23 is a schematic view showing a connection form of a gate line, a data line and respective auxiliary short bars.

FIG. 24 is a waveform diagram of an array test signal applied to a gate and a data line according to the first embodiment.

FIG. 25 is a diagram illustrating the polarity of a signal applied according to the first embodiment for each of R, G, and B pixels.

FIG. 26 is a diagram illustrating polarities of a signal applied according to the first embodiment for each of R, G, and B pixels.

FIG. 27 is a diagram illustrating polarities of signals applied according to the first embodiment for each of R, G, and B pixels.

FIG. 28 is a waveform diagram of an array test signal applied to a gate and a data line according to the second embodiment.

FIG. 29 is a diagram illustrating the polarity of a signal applied according to the second embodiment for each of R, G, and B pixels.

FIG. 30 is a diagram illustrating the polarity of a signal applied according to the second embodiment for each of R, G, and B pixels.

FIG. 31 is a waveform diagram illustrating an array test signal applied to a gate and a data line according to a third embodiment.

FIG. 32 is a waveform diagram illustrating an array test signal applied to a gate and a data line according to a fourth embodiment.

[Explanation of symbols]

410, 420, 210, 220, 230 Auxiliary short bar 4, 5, 6, 7, 8 Test pad G1, G2, G3, G4, G5, G6 Gate line D1, D2, D3, D4, D5, D6 Data line 110 , 120, 130 Gate pad 510, 520, 530 Data pad 501, 502, 503, 504 Data extension 101, 102, 103 Gate extension 301, 302, 303, 310, 320 Connection pattern

Claims (43)

[Claims] 1. A liquid crystal display substrate used for a liquid crystal display device, comprising: a plurality of first wirings parallel to each other; a plurality of second wirings formed parallel to the first wirings; A liquid crystal display substrate comprising: a first short bar connected to the first wiring; a second short bar connected to the second wiring; and a main short bar formed outside the first and second short bars. . 2. The liquid crystal display substrate according to claim 1, wherein said first and second wirings are gate lines to which a scanning signal is applied. 3. The liquid crystal display substrate according to claim 1, wherein said first and second wirings are data lines to which an image signal is applied. 4. The liquid crystal display substrate according to claim 1, wherein said main short bar is connected to said first and second wirings. 5. The liquid crystal display substrate according to claim 1, wherein said first and second wirings are alternately arranged. 6. A transparent insulating substrate, a plurality of gate lines formed on the substrate in parallel with each other, and a gate insulating film having a first opening covering the gate lines and exposing the gate lines. A plurality of data lines formed on the gate insulating film along a direction intersecting the gate line; and a first auxiliary formed at one end of the gate insulating film in a direction along the data line. A short bar, a second auxiliary short bar formed at one end of the gate insulating film in parallel with the first auxiliary short bar, and a short bar formed on the data line and the first and second auxiliary short bars. A protection film having a second opening on the first opening and having third and fourth openings on the first and second auxiliary short bars respectively; and a protection film formed on the protection film. And the first and The gate line and the first gate through the second opening and the third opening.
A first connection pattern connected to the auxiliary short bar, and a first connection pattern formed on the protective layer and connected to the first connection pattern through the first and second openings and the fourth opening. A second connection pattern connected to the gate line and the second auxiliary short bar that are not provided. 7. A third, a fourth, and a fifth auxiliary short bar formed on the substrate in a direction along the first and second auxiliary short bars and parallel to each other, and formed on the protective film. And third, fourth, and fifth connection patterns, wherein the third, fourth, and fifth connection patterns include the data lines and the third, fourth, and fifth auxiliary short bars, respectively. The liquid crystal display substrate according to claim 6, wherein the liquid crystal display substrate is electrically connected. 8. The protection film has a fifth opening for exposing a data line, and the gate insulating film and the protection film have the third, fourth, and fourth openings.
The sixth, seventh,
An eighth opening, wherein the third, fourth, and fifth connection patterns are connected to different data lines through the fifth opening, and through the sixth, seventh, and eighth openings. The liquid crystal display substrate of claim 7, wherein the liquid crystal display substrate is connected to the third, fourth, and fifth auxiliary short bars, respectively. 9. The liquid crystal display substrate according to claim 6, further comprising a gate short bar formed on the substrate and connected to the gate line. 10. The liquid crystal display substrate according to claim 6, further comprising a data short bar formed on the gate insulating film and connected to the data line. 11. A gate short bar formed on the substrate and connected to the gate line, and a data short bar formed on the gate insulating film and connected to the data line, The liquid crystal display substrate of claim 6, wherein the data short bar is electrically connected to the gate short bar. 12. The semiconductor device according to claim 1, further comprising a plurality of auxiliary short bars formed on said substrate, wherein said plurality of auxiliary short bars are located outside said first and second auxiliary short bars. 7. The liquid crystal display substrate according to claim 6, further comprising a gate short bar. 13. The data gate formed outside the third, fourth, and fifth auxiliary short bars and formed on the gate insulating film in a direction along the third, fourth, and fifth auxiliary short bars. 7. The liquid crystal display substrate according to claim 6, further comprising a data short bar separated from the line. 14. The semiconductor device according to claim 1, further comprising a plurality of first and second auxiliary short bars formed on the substrate, the first and second auxiliary short bars being disposed outside the first and second auxiliary short bars, and being separated from the gate lines. A gate short bar, formed outside the third, fourth, and fifth auxiliary short bars and formed on the gate insulating film in a direction along the third, fourth, and fifth auxiliary short bars; The liquid crystal display substrate of claim 6, further comprising: a data short bar separated from the line, wherein the data short bar is electrically connected to the gate short bar. 15. A transparent insulating substrate, a plurality of gate lines formed on the substrate in parallel with each other, a first auxiliary short bar formed on the substrate in a direction along the gate line, A second auxiliary short bar formed in parallel with the first auxiliary short bar on the substrate, the gate line, and the first and second auxiliary short bars; A gate insulating film having first and second openings each exposing a bar; a plurality of data lines formed in parallel with each other on the gate insulating film in a direction intersecting with the gate lines; , Formed on the first and second auxiliary short bars, having third and fourth openings on the first and second openings, respectively, and having a fifth opening on the data line. A protective film; A first connection pattern formed on the protection film and connected to the data line and the first auxiliary short bar through the first and third openings and the fifth opening; A second connection pattern formed and connected to the data line and the second auxiliary short bar not connected to the first connection pattern through the second and fourth openings and the fifth opening; Liquid crystal display substrate including. 16. The liquid crystal display substrate according to claim 15, further comprising a gate short bar formed on the substrate and connected to the gate line. 17. The liquid crystal display substrate of claim 15, further comprising a data short bar formed on the gate insulating film and connected to the data line. 18. A gate short bar formed on the substrate and connected to the gate line, and a data short bar formed on the gate insulating film and connected to the data line, The liquid crystal display substrate of claim 15, wherein the data short bar is electrically connected to the gate short bar. 19. A data short bar located outside the first and second auxiliary short bars and formed on the gate insulating film in a direction along the gate lines and separated from the data lines. The liquid crystal display substrate according to claim 15, comprising: 20. The liquid crystal display substrate according to claim 15, further comprising a gate short bar formed on the substrate in a direction along the data line and separated from the gate line. 21. A data short bar located outside the first and second auxiliary short bars, formed on the gate insulating film in a direction along the gate lines, and separated from the data lines. The semiconductor device of claim 1, further comprising a gate short bar formed on the substrate in a direction along the data line and separated from the gate line, wherein the gate short bar is electrically connected to the data short bar. 16. The liquid crystal display substrate according to item 15. 22. A step of stacking a metal layer on a transparent insulating substrate; patterning the metal layer to form a gate line; forming a gate insulating film on the gate line; Forming first and second auxiliary short bars and data lines for testing the gate line on the film, laminating a protective film, etching the protective film and the gate insulating film, Forming a first opening and a second and a third opening respectively exposing a gate line and the first and second auxiliary short bars; depositing a transparent conductive layer; A first connection pattern connected to the gate line and the first short bar through the first and second openings, and the gate line and the second connection pattern through the first and third openings. Forming a second connection pattern connected to the gate bar and a pixel electrode. 23. The method according to claim 22, further comprising patterning the metal layer to form an antistatic short bar connected to the gate line. 24. The method according to claim 23, further comprising, after forming the connection pattern, removing a connection between the antistatic short bar and the gate line. 25. A step of forming first, second and third auxiliary short bars for testing gate lines and data lines on a substrate, forming a gate insulating film, and forming a gate insulating film on the substrate. Laminating a metal layer; patterning the metal layer to form a data line; laminating a protective film; etching the protective film and the gate insulating film to form the data line and the first; Forming a first opening exposing the second and third auxiliary short bars and second, third and fourth openings; depositing a transparent conductive layer; and patterning the transparent conductive layer. The data line is connected to the first through third openings through the first and second through fourth openings.
Forming a connection pattern and a pixel electrode respectively connected to the auxiliary short bar. 26. The method of claim 25, further comprising patterning the metal layer to form an antistatic short bar connected to the data line. 27. The method according to claim 26, further comprising removing a connection between the antistatic short bar and the data line after forming the connection pattern. 28. A plurality of gate lines and data lines on a substrate, a main antistatic short bar connected to the gate lines and data lines, and a gate test alternately connected to the gate lines. Forming first and second auxiliary short bars and third and fourth auxiliary short bars for data testing alternately connected to the data lines, respectively, and moving the main short bar from the gate and the data lines. Isolating, applying a voltage to the first and second auxiliary short bars, and applying a voltage to the third and fourth auxiliary short bars, and detecting a defect included in the data line and / or the gate line. And a method for manufacturing a liquid crystal display substrate. 29. A different voltage is applied to each of the first auxiliary short bar and the second auxiliary short bar,
A method for manufacturing a liquid crystal display substrate according to claim 28. 30. Applying different voltages to the third auxiliary short bar and the fourth auxiliary short bar, respectively.
A method for manufacturing a liquid crystal display substrate according to claim 28. 31. The method according to claim 28, further comprising removing the first, second, third and fourth auxiliary short bars after the failure detecting step. 32. A plurality of R, G, and B pixels, first and second gate lines that are divided into even-numbered and odd-numbered pixels, respectively, and are divided into the R, G, and B pixels. A liquid crystal display substrate having a plurality of data lines connected thereto, wherein a first pulse is applied to the first gate line, and a second pulse is applied to the second gate line at a timing different from the first pulse. Applying the first pulse, wherein in the applying the first pulse, the first data lines adjacent to each other among the three data lines arranged in series are arranged.
And applying the first and second signals of the same polarity to the second data line, and applying the first and second signals to the third data line excluding the first and second data lines among the three data lines. Applying a third signal having a polarity different from that of the second signal, and applying the first and second signals to the second and third data lines in the step of applying the second pulse; A method for inspecting a liquid crystal display device, wherein the third signal is applied. 33. The method according to claim 32, wherein the first pulse and the second pulse are applied periodically and with a time difference of half a cycle. 34. The method further comprising: applying a third pulse to the first gate line; and applying a fourth pulse to the second gate line at a different timing from the third pulse. Applying the first and second signals to the second and third data lines, applying the third signal to the first data line, and applying the fourth pulse. 33. The method according to claim 32, wherein the first and second signals are applied to the first and third data lines, and the third signal is applied to the second data lines. 35. The method according to claim 34, wherein the third pulse and the fourth pulse are applied periodically and with a time difference of half a cycle. 36. A plurality of R, G, and B pixels, first and second gate lines that are divided into even-numbered and odd-numbered pixels, respectively, and divided into the R, G, and B pixels. A liquid crystal display substrate having a plurality of connected data lines, wherein a first pulse is applied to the first gate line, and a second pulse is applied to the second gate line at a different timing from the first pulse. Applying a first pulse, wherein in the applying the first pulse, the first data lines adjacent to each other among the three data lines arranged in series are arranged.
And applying a first signal having a first polarity and inverting at a first inversion cycle to the second data line, and a third signal of the three data lines excluding the first and second data lines. Applying a second signal that is inverted at the first inversion cycle to the data line and has a polarity opposite to that of the first signal; and applying the second pulse to the first and second data lines. A method for testing a liquid crystal display device, comprising applying a second signal and applying the first signal to the third data line. 37. The method according to claim 37, further comprising: applying a third pulse to the first gate line; and applying a fourth pulse to the second gate line at a timing different from the third pulse. Applying a pulse, applying the first signal to the first and third data lines, applying the second signal to the second data line, and applying the fourth pulse; 37. The method according to claim 36, wherein the first signal is applied to the second data line and the second signal is applied to the first and third data lines. 38. The method according to claim 37, wherein the first pulse and the second pulse or the third pulse and the fourth pulse are applied with a time difference of a half cycle from each other. 39. The method according to claim 37, wherein the timing at which the first to fourth pulses are applied is a timing at which the first and second signals are inverted. 40. The method according to claim 37, wherein the first inversion cycle is equal to a width of the first to fourth pulses. 41. The method according to claim 37, wherein the first inversion cycle is twice the width of the first to fourth pulses. 42. The method according to claim 37, wherein the first to fourth pulses are applied after the timing when the first and second signals are inverted. 43. The method according to claim 37, wherein the first to fourth pulses are applied after a timing at which the first and second signals are inverted, and the first inversion cycle is larger than a width of the first to fourth pulses. 3. The inspection method for a liquid crystal display device according to 1.