JPH11226217A - Controller for pachinko game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller for a pachinko game machine which enables lowering of a circuit cost by controlling a ball game machine with an internal interrupt circuit of a CPU to eliminate an external circuit for generating a reset interruption. SOLUTION: In this interrupt processing, a stack pointer is initialized by a processing at S3 and hence, in the execution of the interrupt processing, there is no need for returning a value of the stack pointer by executing a RETI (RETurn Interrupt) instruction. Moreover, as the processing at S9 and S10 permits multiple interruption of a timer 1, when a timer interrupt flag is turned ON, an interrupt demand of the timer 1 is outputted immediately. As a result, the interrupt processing can be executed in a short time after the generation of the timer 1 interruption. This enables the controlling of a pachinko game machine by using the timer interrupt built into a CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a ball game machine represented by a pachinko game machine,
The present invention relates to a control device for a ball game machine that generates interrupts at regular intervals and performs control by the interrupt processing.

[0002]

2. Description of the Related Art A pachinko gaming machine of this type includes an external circuit that generates a reset signal at regular intervals (for example, a cycle of 2 ms), in addition to a CPU that executes calculations.
A reset signal generated by an external circuit is input to a reset terminal of the CPU, and causes the CPU to generate a reset interrupt at regular intervals. The CPU controls the pachinko gaming machine by this periodically generated reset interrupt, so that even if any abnormality occurs due to noise or the like during the execution of the game, the game can be continued without interruption. You can.

[0003]

However, in such a method, an external circuit for generating a reset signal at regular intervals is required, and there is a problem that circuit cost is increased.

By the way, some CPUs include ROM and RAM.
Some are built-in, and some are made more resistant to noise. Many of these CPUs have a built-in timer interrupt circuit or the like, and by using such an internal interrupt circuit, the external circuit can be eliminated and the circuit cost can be reduced.

However, compared to a reset interrupt, an interrupt by an internal interrupt circuit requires a longer time from the occurrence of an interrupt to the execution of an interrupt process. There was a problem that interrupt processing could not be executed. That is, in the case of a reset interrupt, if the next reset interrupt occurs during the reset interrupt processing, the next reset interrupt processing is immediately executed regardless of the execution state of the CPU. However, in the interrupt by the internal interrupt circuit, even if an interrupt by the next internal interrupt circuit occurs during the processing of the interrupt by the internal interrupt circuit, the CPU terminates the instruction being executed, and , RETI (RET
Only after the stack pointer is returned by execution of the (urn Interrupt) instruction, the interrupt processing by the next internal interrupt circuit cannot be executed. Therefore, in the interrupt by the internal interrupt circuit, a longer time is required from the generation of the interrupt to the execution of the interrupt processing, as compared with the case of the reset interrupt.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has an external circuit for controlling a ball game machine by an interrupt circuit built in a CPU to generate a reset interrupt. It is an object of the present invention to provide a control device for a ball-and-ball game machine capable of reducing the cost of a ball game machine.

[0007]

In order to achieve this object, a control device for a ball game machine according to a first aspect of the present invention comprises an interrupt means for generating an interrupt at a predetermined interval, and an interrupt by the interrupt means. Interrupt processing executed by an interrupt. The interrupt processing controls a ball game machine that plays a game by hitting a hit ball into a game area, and the interrupt means includes an interrupt built in a CPU. An interrupt circuit, wherein the interrupt processing includes stack return means for returning a value of a stack pointer to a state before the occurrence of the interrupt processing, and an interrupt for permitting occurrence of multiple interrupts by the interrupt means. Interrupt execution means, control means for executing control of the ball game machine, and predetermined processing after execution of the stack return means, interrupt permission means and control means until the next interrupt processing is executed. Loop means for repeating.

According to the first aspect of the present invention, in the interrupt processing by the interrupt circuit built in the CPU, the value of the stack pointer is changed by the stack return means before the interrupt processing occurs. At the same time, the state is restored, and the generation of multiple interrupts by the interrupt circuit is permitted by the interrupt permitting means. Thereafter, control of the ball game machine is performed by the control means. When the control is completed, predetermined processing is repeated by the loop means until a multiple interrupt is generated by the permitted interrupt circuit. Therefore, when the next interrupt is generated by the interrupt circuit during the processing of the interrupt, the CPU terminates the instruction being executed and immediately executes the next interrupt without executing the RETI instruction having a long execution time. Is executed. Therefore, the time from the occurrence of an interrupt to the start of the interrupt processing can be reduced.

[0009]

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In this embodiment, a pachinko game machine will be described as an example of a ball game machine.

FIG. 1 is a front view of the gaming board of the pachinko gaming machine P. Around the game board 1, there are provided a plurality of winning ports 2 from which 5 to 15 game balls are paid out when a hit ball wins. In the center of the game board 1, a liquid crystal (L) that displays a pattern or the like as a plurality of types of identification information
CD) display 3 is provided. The display screen of the LCD display 3 is divided horizontally into three parts.
In each of the three divided display areas, the symbol is displayed in a variable manner.

A symbol operation gate 4 is provided below the LCD display 3. When a hit ball passes through the symbol operation gate 4, the variable display of the LCD display 3 is started. Below the symbol operation gate 4, a specific winning opening (large winning opening) 5 is provided. This specific winning opening 5 is LC
When the display result after the change of the D display 3 matches one of the predetermined combination of symbols, a predetermined time (for example,
The winning opening is opened until 30 seconds elapse or until 10 hit balls are won. The specific winning opening 5 is provided with a V zone 5a. If a hit ball passes through the V zone 5a while the specific winning opening 5 is open, a continuation right is established and the specific winning opening 5 is closed. Thereafter, the specific winning opening 5 is opened again for a predetermined time (or until a predetermined number of hit balls are won in the specific winning opening 5). The opening / closing operation of the specific winning opening 5 can be repeated up to 16 times (16 rounds), and the state in which the opening / closing operation can be performed is a state in which a predetermined game value is given (a special game state). is there.

FIG. 2 is a block diagram showing an electric configuration of the pachinko gaming machine P. The control unit C of the pachinko gaming machine P is configured such that a CPU 11 as an arithmetic unit, an EEPROM 16 as a nonvolatile and electrically rewritable memory, and an input / output port 17 are mutually connected by a bus line 18. I have.

The CPU 11 has an arithmetic circuit 1 inside.
2, a timer interrupt circuit 13, a ROM 1 storing programs and various data shown in the flowcharts of FIGS.
4, a RAM 15 functioning as various work areas including a storage memory 15a. The arithmetic circuit 12 is a circuit having an ALU, various registers, a program counter, and the like, and is a circuit that performs arithmetic, that is, executes a program according to a program stored in the ROM 14. When the set time has elapsed, the timer interrupt circuit 13 generates an interrupt (interrupt requests 13g1 to 13g5).
), And is a circuit for causing the CPU 11 to perform an interrupt process, and includes five circuits of a timer 1 to a timer 5.

FIG. 3 is a block diagram of the timer interrupt circuit 13. As shown in FIG. As shown in FIG. 3, the timer interrupt circuit 13 includes a free running counter 13a, five compare registers 13b1 to 13b5, an interrupt flag register 13c, an interrupt mask register 13d, and ten AND circuits 13e1. To 13e5, 13f1 to 13f5. The free running counter 13a is a 16-bit counter that counts up by one each time the clock signal 13h is input. When the count value becomes FFFFh by counting up, the free running counter 13a returns to 0000h by the next clock signal 13h. .

The compare registers 13b1 to 13b5 are:
This is a register having a comparator function to be compared with the value of the free running counter 13a. A total of five registers are provided, one for each of the timers 1 to 5. A count value corresponding to the timing at which an interrupt is generated is written in each of the compare registers 13b1 to 13b5.
When the count value of the free running counter 13a matches the count value written in 5, the corresponding interrupt flags 13c1 to 13c5 of the interrupt flag register 13c are turned on.

The interrupt flag register 13c is a flag that is turned on when the count value of the free running counter 13a matches the count value of the compare registers 13b1 to 13b5, and indicates the state of occurrence of an interrupt. Interrupt flag 13c1 of interrupt flag register 13c
13c5 is provided for each of the timers 1 to 5, and corresponds to each of the compare registers 13b1 to 13b5.

The interrupt mask register 13d stores each timer 1
5 to 5 to set the permission or prohibition of the interrupt for each of the timers 1 to 5. When the corresponding timer mask registers 13d1 to 13d5 of the interrupt mask register 13d are turned on, the interrupts of the timers 1 to 5 are enabled. Conversely, when the timer mask registers 13d1 to 13d5 are turned off, the timers 1 to 5 are disabled. Interrupts are disabled.

The ten AND circuits 13e1 to 13e5
13f1 to 13f5 and the preceding AND circuits 13e1 to 13f1
13e5 is a timer interrupt flag 1 for each of the timers 1 to 5.
3c1 to 13c5 and the timer mask registers 13d1 to 13d1
When 3d5 is input and both are turned on, an on signal is output to the subsequent AND circuits 13f1 to 13f5. The AND circuits 13f1 to 13f5 at the subsequent stage receive, in addition to the output signals of the AND circuits 13e1 to 13e5 at the preceding stage, a signal for permitting or prohibiting the interruption of the CPU 11 as a whole. Request 1
3g1 to 13g5 are generated.

That is, in the state in which the interrupt of the entire CPU 11 is permitted, the count value of the free running counter 13a and the compare register 1 for the timers 1 to 5 for which the interrupt is permitted by the interrupt mask register 13d.
When the count values of 3b1 to 13b5 match, the corresponding timer interrupt flag 13c of interrupt flag register 13c
1 to 13c5 are turned on, and the subsequent AND circuits 13f1 to 13f1 are turned on.
The corresponding interrupt requests 13g1 to 13g5 are output from 13f5.

Here, the interrupt jump table will be described with reference to FIG. The interrupt jump table is a table that stores an address to which a program jumps when there are interrupt requests 13g1 to 13g5. When the interrupt requests 13g1 to 13g5 are output, the CPU 11 refers to the address of the interrupt jump table corresponding to the interrupt requests 13g1 to 13g5, sets the value of the program counter to the address, and executes the interrupt processing. Is performed. Therefore, the corresponding interrupt processing program is stored in the jump address (jump destination address) of the interrupt jump table.

In the present embodiment, the control of the pachinko gaming machine P is performed by a timer 1 interrupt. The jump address is the same RESET address as the jump address of the reset interrupt, the illegal opcode trap interrupt, and the clock monitor abnormal interrupt. The reset interrupt is an interrupt executed when the power of the pachinko gaming machine P is turned on,
The illegal opcode trap interrupt is an interrupt executed when the CPU 11 fetches an undefined opcode. Further, the clock monitor abnormal interrupt is executed by the CPU 11.
This is an interrupt that is executed when an abnormality occurs in the clock monitor provided in. That is, these reset interrupts, illegal opcode trap interrupts, and clock monitor abnormal interrupts are often caused by noise abnormalities such as electrostatic noise and AC line noise. Timer 1 for controlling machine P
By making the same as the jump address of the interrupt, even if such noise occurs, the control of the pachinko gaming machine P can be continued without malfunctioning.

Returning to FIG. The storage memory 15a provided in the RAM 15 stores the timer 1 compare register 13
This is a memory for storing the count value written to b1. The timer 1 interrupt of this embodiment is executed every 2 ms. Therefore, for each interruption process executed by the timer 1 interruption (each execution of the process of the flowchart of FIG. 5), a count value corresponding to 2 ms is added to the value of the storage memory 15a, and the counted value after the addition is added. Is stored in the storage memory 15a, and is written to the timer 1 compare register 13b1. Therefore, even if the timer 1 interrupt is a timer interrupt circuit using the free running counter 13a, the timer 1 interrupt is not accumulated without accumulating the error time from the occurrence of the interrupt until the actual interrupt processing is started. Can be executed periodically.

In this embodiment, the compare register 1
Each of 3b1 to 13b5 is configured to be readable and writable. Therefore, the value of the timer 1 compare register 13b1 is directly read out without providing the storage memory 15a, a count value corresponding to 2 ms is added to the value, and the addition result is written to the timer 1 compare register 13b1 again. It is conceivable to configure. However, the contents of the compare registers 13b1 to 13b5 are initialized to FFFFh by a system reset or a user reset. Therefore, when such a configuration is used, if noise or the like that causes a reset interrupt occurs, the interrupt interval (period) of the timer 1 interrupt is disturbed, and normal control cannot be continued. It is. Therefore, in this embodiment, a storage memory 15a is provided in the RAM 15 in order to avoid such a problem due to noise or the like.
The timer 1 compare register 13 is stored in the storage memory 15a.
The count value of b1 is stored.

The input / output port 17 is connected to the CPU 11 and the EEPROM 16 via the bus line 18,
The display device D and other input / output devices 19 are connected.
The control unit C sends various operation commands to the display device D and other input / output devices 19 via the input / output port 17 to control these devices. That is, the variable display of the LCD display 3 and the opening / closing operation of the specific winning opening 5 are also controlled based on this operation command.

The display device D includes a CPU 21, a program ROM 22, a work RAM 23, and a video RAM 24.
, Character ROM 25, image controller 26
, An input / output port 27 and the LCD display 3. The CPU 21 of the display device D responds to the operation command output from the control unit C to the LCD display 3.
The program ROM 22 stores a program executed by the CPU 21. The work RAM 23 is a CPU
21 is a memory that stores work data used when the program is executed by the program 21.

The video RAM 24 is a memory in which data displayed on the LCD display 3 is stored.
The display content of the D display 3 is changed. That is, the change display of the symbol in each display area is performed by rewriting the contents of the video RAM 24. The character ROM 25 is a memory for storing character data such as symbols displayed on the LCD display 3. The image controller 26 includes a CPU 21, a video RAM 24,
By adjusting the timing of each input / output port 27,
In addition to reading and writing data, the video RAM 2
The display data stored in the LCD 4 is displayed on the LCD display 3 at a predetermined timing with reference to the character ROM 25.

Next, each process executed by the control unit C of the pachinko gaming machine P configured as described above will be described with reference to the flowcharts of FIGS. FIG.
9 is a flowchart of an interrupt process executed every 2 ms by a timer 1 interrupt. As shown in the interrupt jump table of FIG. 4, the jump address of the reset interrupt is the same as the jump address of the timer 1 interrupt.
ET address. Therefore, this interrupt process is also executed in the reset interrupt process when the power is turned on. Also, Illegal opcode trap interrupt,
This interrupt process is also executed when a clock monitor abnormal interrupt occurs.

In this interrupt processing, first, the interrupt of the entire CPU 11 is prohibited (S1), and then the interrupt request 13 of the timer 1 is issued.
In order to release g1, the timer 1 interrupt flag 13c1 is cleared (S2), and the value of the stack pointer is initialized (S3). Next, a pattern (for example, a keyword) written in a predetermined area of the RAM 15 is checked to check whether the pattern is correctly written, that is, whether there is an abnormality in the pattern (S4). If there is an abnormality in the pattern (S4: Yes), the process is executed by the reset interrupt process after the power is turned on. In such a case, the RAM is initialized (S5) and the free running counter is executed. The value of 13a is written to the storage memory 15a (S6). The predetermined pattern checked in the processing of S4 is written in the initialization processing of the RAM.

After the processing in S6, or when no abnormality is found in the pattern check in S4 (S4:
No), the process proceeds to S7. In the process of S7, a count value corresponding to 2 ms, which is an interrupt interval (cycle), is added to the count value stored in the storage memory 15a (S
7). Then, the value of the storage memory 15a after the addition is written to the timer 1 compare register 13b1 (S8), and the time when the next timer 1 interrupt occurs is set. Thereafter, the timer 1 mask register 13d1 is turned on (S9), and further, C
After the interruption of the entire PU 11 is permitted (S10), the main processing which is the control processing of the pachinko gaming machine P is executed (S10).
11).

After the execution of the main processing (S11), the remaining time processing is repeated until the next timer 1 interrupt occurs (S12). FIG. 6 is a flowchart of the remaining time process. In the remaining time process, a predetermined process is performed (S1).
3). The predetermined process (S13) includes, for example, a process of updating a symbol pattern displayed on the LCD display 3 and a process of updating a random number used in the main process (S11).

During execution of the remaining time processing (S12), the count value of the free running counter 13a matches the count value of the timer 1 compare register 13b1, the timer 1 interrupt flag 13c1 turns on, and the timer 1 interrupt occurs. When this occurs, the timer 1 mask register 13d1 has already been turned on by the processing of S9, and C
Since interruption of the entire PU 11 is permitted, the AND circuit 13f1 outputs an interruption request 13g1 of the timer 1. Then, after completion of the instruction being executed, the CPU 11 saves the value of the program counter in the stack pointer, and starts the interrupt processing of the flowchart in FIG.

As described above, in this interrupt processing, the stack pointer has been initialized by the processing of S3.
When executing this interrupt processing, RETI (R
There is no need to execute the (ETurn Interrupt) instruction to return the value of the stack pointer. Moreover, since the multiple interrupts of the timer 1 are permitted by the processes of S9 and S10, when the timer 1 interrupt flag 13c1 is turned on, the interrupt request 13g1 of the timer 1 is output immediately. Therefore, timer 1
This interrupt processing can be executed within a short time after the occurrence of the interrupt. Thus, the pachinko gaming machine P can be controlled even by using the timer interrupt built in the CPU 11.

In this embodiment, the interrupt processing described in claim 1 corresponds to the processing in the flowchart of FIG. 5, and the processing of S3 is performed as the stack return means, and the processing of S9 and S10 is performed as the interrupt permission means. The processing corresponds to the processing of S11 as the control means, and the processing of S12 corresponds to the loop means.

The present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Can easily be inferred.

For example, in the present embodiment, the interrupt processing of FIG.
In addition to the timer 1 interrupt processing, the reset interrupt processing is also used, so that the stack pointer is initialized instead of returning the stack pointer in the processing of S3. However, if this interrupt processing is not shared with the reset interrupt processing and is dedicated to the timer 1 interrupt processing, the stack pointer is not initialized in step S3, The configuration may be such that the value of the stack pointer is returned by executing an instruction or the like.

Naturally, even when the interrupt process is shared by the timer 1 interrupt and the reset interrupt, the process of operating the stack pointer corresponding to S3 is performed by the reset interrupt. If the processing is divided into the timer 1 interrupt processing and the timer 1 interrupt processing, the stack pointer operation processing executed in the timer 1 interrupt processing is performed by, for example, executing a pop instruction instead of stack pointer initialization. You may comprise so that it may return.

Hereinafter, modified examples of the present invention will be described. 2. The control device for a ball-and-ball game machine according to claim 1, wherein said stack return means initializes a stack pointer, and a jump destination address when an interrupt is generated by said interrupt circuit is:
A control device 2 for a ball game machine, wherein the jump destination address of a reset interrupt executed when the power is turned on is the same as the jump destination address. Therefore, even if an abnormality such as a reset interrupt occurs due to noise or the like, the reset interrupt jump destination address is the same as the jump destination address when the interrupt is generated by the interrupt circuit. The reset processing is executed by the occurrence of a reset interrupt. Therefore, control can be performed without causing the ball game machine to malfunction.

In the control device 2 of the ball-and-ball game machine, the jump destination address when an interrupt is generated by the interrupt circuit is the same as the jump destination address of a trap interrupt generated when an undefined opcode is fetched. A control device 3 for a ball game machine. Therefore, even if an abnormality such as a trap interrupt occurs due to noise or the like,
Since the jump destination address of the trap interrupt is set to be the same as the jump destination address at the time of occurrence of the interrupt by the interrupt circuit, the interrupt processing is executed when an abnormal trap interrupt occurs. Therefore, control can be performed without causing the ball game machine to malfunction.

In the control device for a ball game machine or the control device for a ball game machine according to claim 1, the interrupt circuit comprises a timer interrupt circuit, which is updated every predetermined clock. A free-running counter, and a compare register that is compared with the value of the free-running counter, and generates an interrupt when the value of the free-running counter matches the value of the compare register. Set value storage means for storing a value set in the compare register; and addition means for adding a time corresponding to an interrupt interval to the contents of the set value storage means when an interrupt is generated by the timer interrupt circuit. Writing means for writing the addition result by the addition means to the compare register and the set value storage means. Controller spheres gaming machine 4. Therefore, even in the case of a timer interrupt using a free running counter, an interrupt can be generated at a desired interval without accumulating the error time from the occurrence of the interrupt to the start of the interrupt processing.

[0040]

According to the control device for a ball game machine of the present invention, the time from the occurrence of an interrupt to the start of the interrupt process is determined by the interrupt process using the interrupt circuit built in the CPU. Can be shortened. Therefore, there is an effect that an external circuit for generating a reset interrupt can be eliminated, and the circuit cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a front view of a game board of a pachinko gaming machine according to one embodiment of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of the pachinko gaming machine.

FIG. 3 is a block diagram showing a configuration of a timer interrupt circuit.

FIG. 4 is a diagram schematically illustrating an interrupt jump table.

FIG. 5 is a flowchart showing an interrupt process.

FIG. 6 is a flowchart showing a remaining time process.

[Explanation of symbols]

 11 CPU 13 Timer interruption circuit (interruption means, interruption circuit) 14 ROM 15 RAM 15a Storage memory C Control unit D Display device P Pachinko game machine (ball game machine)

Claims (1)

[Claims] An interrupt means for generating an interrupt at a predetermined interval, and an interrupt processing executed by an interrupt by the interrupt means, wherein the hitting ball is hit into a game area by the interrupt processing. In the control device for a ball game machine that controls a ball game machine that performs a game, the interrupt means is configured by an interrupt circuit built in a CPU, and the interrupt processing is performed by setting a value of a stack pointer to Stack return means for returning to a state before the occurrence of interrupt processing; interrupt permission means for permitting the generation of multiple interrupts by the interrupt means; control means for executing control of the ball game machine; A control device for a ball game machine, comprising: loop means for repeating a predetermined process until execution of the next interrupt process after execution of the stack return means, the interrupt permitting means, and the control means. .