JPH11205689A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device with which storage time can be set longer than the cycle of read-out scanning while executing cyclic red-out scanning. SOLUTION: A solid-state image pickup device 10 is provided with plural photodetecting parts PD for generating pixel outputs corresponding to the amount of photodetection, a pixel output holding part QA for holding the pixel output of each photodetecting part and outputting the held pixel output without destroying it, pixel output transfer parts QT and QP for transferring the pixel output from the photoedtecting part to the pixel output holding part and updating the pixel output held in the pixel output holding part, and image scanning circuits 2, 3, 7 and 8, QX and QH for scanning the pixel output from the pixel output holding part and generating a frame unit, field unit or image signal composed of one part of that unit. The above pixel output transfer part transfers the pixel output from the photodetecting part to the pixel output holding part once per plural times of scanning by the image scanning circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly, to a solid-state imaging device which achieves an accumulation time longer than a period of a read scan while performing a periodic read scan.

[0002]

2. Description of the Related Art Conventionally, there has been known a solid-state imaging device that scans a light receiving portion arranged in a matrix in a vertical direction and a horizontal direction and periodically reads out an image signal. In this type of solid-state imaging device, the pixel output of the light receiving unit is reset each time one read scan is performed. Therefore, the time during which the light receiving section accumulates the signal charge (hereinafter, referred to as “accumulation time”) is limited to the period of the readout scan or less.

For example, when an image signal of the NTSC system is generated by interlaced scanning, the accumulation time of the light receiving section is limited to a scanning period of a frame image (1/30 second) or less.
When an NTSC image signal is generated by two-line mixed scanning, the accumulation time of the light receiving unit is limited to a scan period (1/60 second) or less of a field image. FIG. 8 is a diagram illustrating a motion detection image processing device 100 using the solid-state imaging device as described above.

In FIG. 8, an image processing apparatus 1 for motion detection
Reference numeral 00 denotes a solid-state imaging device 101, an AD conversion circuit 102 that converts an image signal (analog signal) from the solid-state imaging device 101 into a digital signal, and image memories 103 and 104 that store the digital signal from the AD conversion circuit 102.
And an image processing circuit 105 which compares digital image signals stored in the image memories 103 and 104 with each other to detect a motion.

In the motion detection image processing apparatus 100 having such a configuration, first, an image signal read from the solid-state imaging device 101 is stored in the image memory 103 via the AD conversion circuit 102. Next, the image signal read subsequent to the image signal is stored in the image memory 104 via the AD conversion circuit 102.

The image processing circuit 105 reads out the image signals stored in the image memories 103 and 104 for each pixel and compares them with each other. At this time, pixels that differ by a predetermined threshold or more are detected, and a signal indicating detection of a moving object (hereinafter, referred to as a “moving object signal”) is generated.

[0007] By such a comparison process of the image signal in the time axis direction, it is possible to detect the motion of the subject.

[0008]

By the way, as described above, in the conventional solid-state imaging device, the accumulation time of the light receiving section cannot be set longer than the period of readout scanning.

Therefore, when photographing a low-luminance subject, there is a problem that a photographing method (a kind of sensitized photographing) in which the accumulation time of the light receiving section is set longer than the readout scanning cycle cannot be performed. . By the way, it has been conventionally known that an image signal of a solid-state imaging device undergoes periodic fluctuation under flickering illumination light such as a fluorescent lamp (hereinafter, such a phenomenon is referred to as a “flicker phenomenon”). ).

FIG. 9 is a diagram for explaining an example of this type of flicker phenomenon. In the Kanto region of Japan, the frequency of commercial power is 50 Hz. The amount of current passing through the fluorescent lamp directly lit by the commercial power supply increases and decreases at a rate of 100 times per second. Therefore, the illumination light blinks at a period of 1/100 second. In FIG. 9, under such a lighting environment,
The figure shows a case where the solid-state imaging device executes readout scanning every 1/30 second.

Under such conditions, the phase relationship between the "blink cycle of illumination light" and the "accumulation time" fluctuates in a 1/10 second cycle corresponding to the least common multiple of both cycles. Therefore, the amount of received light per storage time fluctuates in a 1/10 second cycle, and a luminance level fluctuation occurs in the image signal. Here, the cycle of the luminance level fluctuation is about 1/10 second, so that in an application such as image display, an afterimage effect of the eye works, and the flicker phenomenon is not so noticeable.

However, in applications where a moving object is detected as in the conventional image processing apparatus 100 for motion detection (FIG. 8), the luminance level fluctuation due to the flicker phenomenon described above is reduced.
There has been a problem that the moving object is erroneously detected. In the conventional motion detection image processing apparatus 100 (FIG. 8), a moving object is detected based on an image change between frames or between fields. For a subject moving at a low speed, therefore, there is a problem that an image change (for example, a band-like area caused by movement of an edge portion in the image) is small, and it becomes difficult to detect a moving object.

Therefore, according to the first and second aspects of the present invention,
In order to solve the above-described problem, it is an object to provide a solid-state imaging device that sets a storage time longer than a period of the readout scan while performing a periodic readout scan. It is another object of the present invention to provide a solid-state imaging device capable of further reducing a flicker phenomenon caused by flickering illumination light.

According to a fifth aspect of the present invention, there is provided a solid-state image pickup device which accurately executes signal processing in a time axis direction for an image signal obtained by setting an accumulation time longer than a period of a read scan. Aim. It is an object of the present invention to provide a solid-state imaging device capable of surely detecting a moving object even with a low-speed subject.

An object of the present invention is to provide a solid-state imaging device in which a pixel output holding unit (described later) is realized with a simple configuration.

[0016]

According to a first aspect of the present invention, there are provided a plurality of light receiving units arranged in a matrix and generating pixel outputs according to a light receiving amount, and provided for each light receiving unit. A pixel output holding unit that holds the pixel output and outputs the held pixel output in a non-destructive manner, transfers the pixel output from the light receiving unit to the pixel output holding unit, and outputs the pixel output held by the pixel output holding unit. A pixel output transfer unit for updating, and an image scanning circuit that scans a pixel output output from the pixel output holding unit and generates an image signal of a frame unit or a field unit or a part thereof, and the pixel output transfer unit includes: The pixel output is transferred from the light receiving unit to the pixel output holding unit once for each of a plurality of scans by the image scanning circuit.

In the solid-state imaging device having such a configuration, the pixel output is not read out from the light receiving section during a period of a plurality of readout scans. Therefore, the light receiving unit continuously performs the photoelectric conversion during the period of the multiple read scans.
As a result, the accumulation time of the light receiving unit is set longer than the period of the read scan. On the other hand, the pixel output holding unit keeps holding the previously held pixel output without updating the pixel output during the period of the plurality of read scans. During this period, the image scanning circuit periodically reads the pixel output from the pixel output holding unit. As a result, the same image signal is read from the solid-state imaging device a plurality of times.

According to the first aspect of the present invention, it is possible to set the accumulation time longer than the period of the read scan while performing the periodic read scan without interruption. According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, the image scanning circuit includes: a vertical readout line provided for each vertical column of the light receiving unit; A vertical scanning unit for sequentially selecting pixel outputs in units of horizontal lines and connecting to vertical reading lines; and a horizontal scanning unit for horizontally scanning pixel outputs in units of horizontal lines sequentially output from a group of vertical reading lines. It is characterized by becoming.

(Claim 3) The invention according to claim 3 is the solid-state imaging device according to claim 1 or 2,
The pixel output transfer unit transfers the pixel output from the light receiving unit to the pixel output holding unit at a cycle corresponding to a common multiple of the “scanning cycle of the image scanning circuit” and the “blinking cycle of the illumination light”. I do.

In the solid-state imaging device having such a configuration, the accumulation time of the light receiving section is set to a multiple of the "blink cycle of illumination light". Therefore, the amount of light received per storage time in the light receiving unit is substantially constant (a multiple of the amount of light received per blink cycle) regardless of the phase relationship between the accumulation time and the blink cycle. Therefore, even under the environment of flickering illumination light, the luminance level of the image signal is substantially constant, and the flicker phenomenon can be reliably reduced.

According to a fourth aspect of the present invention, in the solid-state imaging device according to the first or second aspect,
An electronic shutter circuit for initializing the pixel output of the light receiving unit at a timing preceding the time when the pixel output transfer unit transfers the pixel output from the light receiving unit by a multiple period of the “blink cycle of illumination light”; It is characterized by.

In the solid-state imaging device having such a configuration, the accumulation time of the light receiving section is set to a multiple of the "blink cycle of illumination light". Therefore, the amount of light received per storage time in the light receiving unit is substantially constant (a multiple of the amount of light received per blink cycle) regardless of the phase relationship between the accumulation time and the blink cycle. Therefore, even in a flickering lighting environment,
The luminance level of the image signal is substantially constant, and the flicker phenomenon can be reliably reduced.

According to a fifth aspect of the present invention, in the solid-state image pickup device according to any one of the first to fourth aspects, the pixel output transfer section has a pixel output transfer section that precedes and follows a pixel output transfer point. A signal processing circuit that captures pixel outputs from the pixel output holding unit and performs signal processing in a predetermined time axis direction on these successive pixel outputs;
And a processing result scanning circuit for scanning and outputting a processing result by the signal processing circuit.

In the present invention, the same image signal is repeatedly read over a plurality of read scans. In this case, valid information in the time axis direction is not included between these same image signals. Therefore, an expected result cannot be obtained in the signal processing in the time axis direction (except for processing related to noise components such as integration processing in the time axis direction).

For example, the result of the differential processing in the time axis direction does not include the original change of the image signal, but includes only the noise component. Therefore, in a solid-state imaging device that outputs the same image signal a plurality of times, if signal processing in the time axis direction is performed as before, adverse effects such as erroneous determination and malfunction due to noise components frequently occur.

However, in the solid-state imaging device according to the fifth aspect, the signal processing circuit selects a pixel output immediately before and after the pixel output is transferred by the pixel output transfer unit,
Signal processing in the time axis direction is performed on the selected pixel outputs. The pixel outputs before and after such a transfer point include:
Contains valid information about the time axis direction. Therefore, in the solid-state imaging device according to the fifth aspect, it is possible to generate an effective processing result.

According to a sixth aspect of the present invention, in the solid-state imaging device according to the fifth aspect, the signal processing circuit is configured to control the signal processing circuit to immediately before and after the pixel output transfer unit transfers the pixel output. It is characterized in that a pixel output from a pixel output holding unit is fetched, and these successive pixel outputs are compared to generate a moving object signal of an image.

In the solid-state imaging device having such a configuration, the above-described signal processing circuit generates a moving object signal by comparing pixel outputs immediately before and after the pixel output transfer unit transfers the pixel output. The pixel outputs before and after such a transfer point include effective information on the movement of the subject. Therefore, the signal processing circuit can efficiently generate an effective moving object signal.

(Seventh Aspect) According to a seventh aspect, in the solid-state imaging device according to any one of the first to sixth aspects, the pixel output holding unit holds the pixel output in the gate capacitance. And a non-destructive field effect transistor circuit for outputting the pixel output held in the gate capacitance as a source follower output.

In the solid-state imaging device having such a configuration, the pixel output is held in the gate capacitance of the field effect transistor.
Therefore, it is not necessary to separately provide a capacitor for holding the pixel output. In addition, since the pixel output is output as a source follower output, the input impedance on the gate side is very high. Therefore, even in the case of a plurality of read scans,
The pixel output accumulated in the gate capacitance can be held nondestructively.

As described above, a sufficient function required for the pixel output holding section can be simply realized by the source follower circuit including the field effect transistor.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> The first embodiment is an embodiment corresponding to the first, second, third and seventh aspects of the present invention. FIG. 1 shows a solid-state imaging device 1 according to the first embodiment.
FIG. 3 is a diagram illustrating a circuit configuration of a zero. 1, in the solid-state imaging device 10, unit pixels 1 are arranged in a matrix of n rows and m columns. The outputs of these unit pixels 1 are commonly connected for each vertical column, and form m vertical read lines 2.

Further, the solid-state imaging device 10 is provided with a vertical scanning circuit 3 for determining the timing of vertical transfer. The vertical scanning circuit 3 supplies three types of control pulses φTG1, φPX1, φRG1 to the unit pixel 1 in the first row.
Are supplied respectively. Similarly, three types of control pulses φTG2 to n, φPX2 to n, and φPX2 output from the vertical scanning circuit 3 are also applied to the remaining unit pixels 1 in the second to nth rows.
RG2 to RG are supplied respectively.

A current source 4 for supplying a bias current and MOS switches QRSV1 to QRSV1 for resetting the vertical read line 2 are connected to the m vertical read lines 2 described above.
m and MOS switches QH1 to QH for horizontal scanning are connected to each other. The MOS switches QRSV1 to QRSV
A control pulse φRSV for controlling the reset timing is commonly applied to the gate of SVm. Such a control pulse φRSV is output from, for example, the vertical scanning circuit 3.

The gates of the MOS switches QH1 to QHm supply control pulses φH1 to φH from the horizontal scanning circuit 8.
m are respectively given. These MOS switches QH1 to QH1
The other ends of m are connected in common to form a horizontal read line 7. The image signal output on the horizontal readout line 7 is output to the outside of the solid-state imaging device 10 via the video amplifier circuit 7a and the like.

The horizontal read line 7 is connected to a MOS switch QRSH for resetting the horizontal read line 7. A reset control pulse φRSH is supplied to the gates of these MOS switches QRSH.
Such a control pulse φRSH is output from, for example, the horizontal scanning circuit 8 or the like. (Circuit Configuration of Unit Pixel 1) Next, a specific circuit configuration and connection relationship of the unit pixel 1 located in the first row and the first column will be described with reference to FIG. Note that the other unit pixels 1 also differ only in the subscript of the control pulse.
The circuit configuration is the same as that of the unit pixel 1 in the first row and first column.

First, a photodiode PD is arranged in the unit pixel 1. The anode of the photodiode PD is connected to the gate of an amplifying element QA composed of a junction field effect transistor via a charge transfer MOS switch QT. The control pulse φTG1 output from the vertical scanning circuit 3 is supplied to the gate of the charge transfer MOS switch QT.

The gate of the amplifying element QA is connected to a wiring layer maintained at a constant reset potential VRD via a MOS switch QP for resetting the held signal charge. The control pulse φRG1 output from the vertical scanning circuit 3 is supplied to the gate of the MOS switch QP. On the other hand, the source of the amplification element QA is connected to the vertical read line 2 via the vertical transfer MOS switch QX. The control pulse φPX1 output from the vertical scanning circuit 3 is supplied to the gate of the MOS switch QX.

(Correspondence between the present invention and the first embodiment)
Here, the correspondence between the present invention and the first embodiment will be described. First, the invention described in claims 1, 3, and 7 and the first
The light receiving section corresponds to the photodiode PD, the pixel output holding section corresponds to the amplifying element QA, and the pixel output transfer section includes the charge transfer MOS switch QT and the signal charge reset MOS. The image scanning circuit corresponds to (vertical scanning circuit 3, vertical transfer MOS switch QX, vertical readout line 2, horizontal transfer MOS switch QH, horizontal readout line 7, and horizontal scanning circuit 8). I do.

As for the correspondence between the invention described in claim 2 and the first embodiment, the vertical readout line corresponds to the vertical readout line 2, and the vertical scanning section includes the vertical scanning circuit 3 and the vertical transfer MOS switch. The horizontal scanning section corresponds to the horizontal scanning circuit 8, the horizontal transfer MOS switch QH, and the horizontal readout line 7. (Operation of First Embodiment) FIG. 2 is a diagram showing the drive timing of the solid-state imaging device 10. Here, for the sake of simplicity, the drive timing of the first horizontal line (1H shown in FIG. 2) is extracted and shown for read scanning for four vertical periods. From this fourth vertical period onward, the same readout scanning as in the first to third vertical periods is repeatedly performed.

Hereinafter, the scanning operation in each vertical period will be described with reference to FIG. (A) Scanning Operation in First Vertical Period First, at the timing of the period t10 shown in FIG. 2, the control pulse φPX1 is held at a low level, and the control pulse φRG1 falls to a low level. The fall of the control pulse φPX1 causes the MOS switch Q
X conducts, and the source of the amplifying element QA is connected to the vertical read line 2
Connected to.

On the other hand, when the control pulse φRG1 falls, in the unit pixel 1 in the first row, the MOS switch QP is turned on, and the previous signal charge remaining in the gate region of the amplifier QA is discharged. This control pulse φRG1 rises to the high level again immediately before the end of the period t10. As a result, the gate region of the amplifying element QA enters a floating state and maintains a reset state.

Next, at the timing of the period t11 shown in FIG. 2, the control pulse φTG1 falls to a low level. Then, in the unit pixel 1 in the first row, the MOS
The switch QT is turned on, and the signal charge stored in the photodiode PD in the first row is transferred to the gate region of the amplification element QA. Immediately before the end of this period t11, the control pulse φT
G1 is set to the high level again. As a result, MO
S switch QT is turned off, and the gate region of amplifying element QA maintains the state in which the potential has increased according to the signal charge.

In this state, since the control pulse φPX1 is still at the low level, the pixel outputs of the unit pixels 1 arranged in the first row are output to the vertical readout line 2 via the source follower circuit including the amplifying element QA. . Subsequently, FIG.
The horizontal scanning circuit 8 sets the control pulses φH1 to φHm to the high level instead of the control pulses φH1 to φHm at the timing of the period t12 shown in FIG.

For this reason, the vertical read line 2 composed of m columns
Are sequentially connected to the horizontal readout line 7 in the order of 1 to m columns. As a result, the pixel outputs of the first row are sequentially output in the horizontal direction on the horizontal readout line 7 to become image signals. Note that while setting the control pulses φH1 to φHm to a high level, φRSH is temporarily set to a high level. By such an operation, the residual charges on the horizontal read line 7 are
It is discharged every time via the MOS switch QRSH. Therefore, there is no possibility that the residual charges are mixed with the image signal horizontally transferred. The image signal becomes an intermittent signal by such a reset operation. Therefore, a zero-order hold operation or the like may be performed in the video amplifier circuit 7a or the like.

Immediately before the end of the period t12, the control pulse φ
PX1 is returned to a high level. As a result, the MOS switches QX arranged in the first row are turned off, and the amplification element QA in the first row is disconnected from the vertical read line 2. By repeating the series of scanning operations for the first row as described above for the other rows 2 to n in the same manner,
The read scanning in the first vertical period is completed.

(B) Scanning operation in the second vertical period During the second vertical period, the control pulses φRG1 to φRGn and φRG
TG1-n are always set to the high level. Therefore, the gate regions of all the amplifying elements QA keep the floating state, and keep the potential set in the first vertical period.

On the other hand, the anode regions of all the photodiodes PD also keep the floating state and accumulate signal charges continuously from the first vertical period. In such a state, the control pulse φPX1 falls to the low level at the timing of the period t20 shown in FIG. As a result, the MOS switches QX arranged in the first row become conductive, and the source of the amplification element QA in the first row is connected to the vertical read line 2. At this time, the gate region of the amplification element QA is maintained at the same potential as in the first vertical period. Therefore, the same pixel output as in the first vertical period is output to the vertical read line 2 again via the source follower circuit of the amplifier element QA.

Next, the pixel output on the vertical readout line 2 is sequentially output to the horizontal readout line 7 by performing the horizontal transfer operation of the pixel output at the timing of the period t21 shown in FIG. Just before the end of this period t21, the control pulse φPX1 is returned to the high level. As a result, the MOS switches QX arranged in the first row are turned off, and the amplification element QA in the first row is disconnected from the vertical read line 2.

By repeating the series of scanning operations for the first row as described above for the other rows 2 to n, the read scanning in the second vertical period is completed. (C) Scanning operation in third vertical period The same scanning operation as in the second vertical period is performed. (D) Scanning operation in fourth vertical period The same scanning operation as in the first vertical period is performed.

(Effects of First Embodiment, etc.) According to the operation described above, in the first embodiment, no signal charges are read from the photodiode PD in the second vertical period and the third vertical period. Therefore, the photodiode PD
Is the period from the first vertical period to the fourth vertical period,
The photoelectric conversion is continuously performed. As a result, the accumulation time of the signal charge in the photodiode PD is set to be three times the readout scanning period.

On the other hand, the amplification element QA outputs the same pixel output in the second vertical period and the third vertical period as in the first vertical period. Therefore, also in the second vertical period and the third vertical period, the periodic readout scanning can be executed without interruption. In this manner, in the first embodiment, it is possible to set the accumulation time of the signal charges to be longer than the period of the read scan while performing the read scan without interruption.

Further, for example, the read scanning cycle is set to 1/3.
If it is 0 second, the accumulation time of the signal charge in the first embodiment is 1/10 second. This accumulation time corresponds to ten times the blinking period of the illumination light described above of 1/100 second. Therefore, as shown in FIGS. 3A and 3B, the amount of received light per accumulation time does not depend on the phase relationship with the blinking cycle.
The amount of light received is constant for 10 blink cycles. As a result, the luminance level of the image signal output from the solid-state imaging device 10 is substantially constant even under the environment of flickering illumination light, and the flicker phenomenon can be reliably eliminated.

In the above-described first embodiment, a case has been described in which an image signal is read out in frame units by progressive scanning. However, the present invention is not limited to this. For example, an interlaced scanning or other interlaced scanning may be performed to read out an image signal in field units. In the first embodiment described above,
The operation of transferring the signal charge from the photodiode PD to the amplifying element QA is performed on a row-by-row basis, but is not limited to this. For example, the control pulses φTG1 to φTG1 to n may be simultaneously dropped to a low level during the vertical retrace period at a rate of once for each of a plurality of read scans. In such an operation, all the photodiodes PD to all the amplifying elements Q
Since the signal charges are collectively transferred to A, the timing of the accumulation time for each row can be made uniform.

Further, in the first embodiment described above, the configuration in which the electronic shutter operation is not performed has been described, but the present invention is not limited to this. For example, as shown in FIG. 7, the anode of each photodiode PD may be connected to a reset wiring layer or the like via a MOS switch QS for discharging signal charges. In such a configuration, the MO
By intermittently turning on the S switch QS, an electronic shutter function can be realized. By using such an electronic shutter operation together with the present invention, it is possible to set the accumulation time of the signal charges to a time other than a multiple of the scanning cycle.

In the solid-state imaging device 30 shown in FIG.
By using the electronic shutter function, the accumulation time of the signal charge may be set to a multiple period of the "blink cycle of the illumination light". Even with such an operation, it is possible to reliably eliminate the flicker phenomenon caused by the flickering of the illumination light. In the first embodiment described above, the junction field-effect transistor is used as the amplifying element arranged in each unit pixel. However, the present invention is not limited to this. For example, as an amplifying element, an electrostatic induction transistor,
Bipolar transistor, MOS transistor, CMD
May be used.

Further, in the above-described first embodiment, X
Although the circuit configuration of the Y address system has been described, the present invention is not limited to this. For example, the vertical readout line 2 and / or the horizontal readout line 7 may be replaced with a CCD transfer line or the like. Next, another embodiment will be described. <Second Embodiment> A second embodiment is described in claims 1 to 3,
This is an embodiment corresponding to the inventions described in 5 to 7.

FIG. 4 is a diagram showing a circuit configuration of a solid-state imaging device 20 according to the second embodiment. The solid-state imaging device 20 has the following configuration added to the solid-state imaging device 10 shown in FIG. First, m vertical read lines 2
Are connected to m different value detection circuits 6, respectively. These outlier detection circuits 6 include control pulses φSA,
φSB is commonly given. Note that this control pulse φS
A and φSB are generated by the vertical scanning circuit 3, for example.

The outputs of the m different value detection circuits 6 are connected to the parallel input terminals of the shift register 9. The shift register 9 is supplied with a control pulse φLD for determining the timing of capturing the parallel input and a transfer clock φCK for serial transfer. The pulses φLD and φCK are generated by, for example, the vertical scanning circuit 3 and the horizontal scanning circuit 8.

The serial output of the shift register 9 is
It is output to the outside as a moving object signal. FIG. 5 is a diagram illustrating a circuit example of the outlier detection circuit 6 described above. Hereinafter, a specific circuit configuration of the outlier detection circuit 6 provided in the first column of the vertical read line 2 will be described with reference to FIG. The outlier detection circuits 6 in the second and subsequent columns have the same circuit configuration as the outlier detection circuits 6 in the first column, except for the subscripts of the output signals.

First, one ends of two capacitors CCA and CCB are connected to the vertical read line 2. The other end of the capacitor CCA is connected to the input terminal of the first inverter INV1, and only the change of the input component is transmitted. Further, a voltage VR1 (= VT−Vth) for determining a threshold is supplied to an input terminal of the first inverter INV1 via the MOS switch QB1. The control pulse φSA is supplied to the gate of the MOS switch QB1.

The output terminal of the first inverter INV1 is connected to the input terminal of the third inverter INV3. A MOS switch QB3 for interrupting a positive feedback loop is connected between the output terminal of the third inverter INV3 and the input terminal of the first inverter INV1.
The control pulse φ is applied to the gate of the MOS switch QB3.
SB is supplied.

On the other hand, the other end of the capacitor CCB is
Is connected to the input terminal of the inverter INV2, and only the change of the input component is transmitted. Further, a voltage VR2 (= VT + Vt) for determining a threshold is input to the input terminal of the second inverter INV2 via the MOS switch QB2.
h) is supplied. The control pulse φSA is supplied to the gate of the MOS switch QB2.

The output terminal of the second inverter INV2 is connected to the input terminal of the fourth inverter INV4. A MOS switch QB4 for interrupting the positive feedback loop is connected between the output terminal of the fourth inverter INV4 and the input terminal of the second inverter INV2.
The control pulse φ is applied to the gate of the MOS switch QB4.
SB is supplied.

The fourth inverter I connected in this manner
The output of NV4 is input to one input terminal of NAND circuit NA. Further, after the output of the third inverter INV3 is inverted via the fifth inverter INV5,
The signal is input to the other input terminal of the NAND circuit NA. The output of the NAND circuit NA is supplied to the parallel input terminal Q1 of the shift register 9.

The voltage VT described above is applied to the inverter I
This is a voltage corresponding to the threshold voltages of NV1 and INV2. Further, the voltage Vth is a voltage corresponding to a threshold when determining whether a difference between image signals is significant. (Correspondence between the present invention and the second embodiment) Here, the correspondence between the present invention and the second embodiment will be described.

First, regarding the correspondence between the first and third aspects of the present invention and the second embodiment, the light receiving section corresponds to the photodiode PD, and the pixel output holding section corresponds to the amplifying element QA.
And a pixel output transfer unit includes a charge transfer MOS switch QT and a signal charge reset MOS switch QP.
And the image scanning circuit corresponds to (vertical scanning circuit 3, vertical transfer MOS switch QX, vertical readout line 2, horizontal transfer MOS switch QH, horizontal readout line 7, and horizontal scanning circuit 8).

In the correspondence between the second embodiment and the second embodiment, the vertical readout line corresponds to the vertical readout line 2, and the vertical scanning section includes the vertical scanning circuit 3 and the vertical transfer MOS switch. The horizontal scanning section corresponds to the horizontal scanning circuit 8, the horizontal transfer MOS switch QH, and the horizontal readout line 7.

Regarding the correspondence between the inventions described in claims 5 and 6 and the second embodiment, the signal processing circuit corresponds to the outlier detection circuit 6, and the processing result scanning circuit corresponds to the shift register 9. (Operation of Second Embodiment) FIG. 6 is a diagram showing the drive timing of the solid-state imaging device 20. Here, for the sake of simplicity, the drive timing of the first horizontal line (1H shown in FIG. 6) for the read scan for four vertical periods is extracted and shown. From this fourth vertical period onward, the same readout scanning as in the first to third vertical periods is repeatedly performed.

The scanning operation in each vertical period will be described below with reference to FIG. (A) Scanning Operation in First Vertical Period First, at the timing of the period t10 shown in FIG. 6, the control pulse φSB falls to a low level. as a result,
The MOS switches QB3 and QB4 in the different value detection circuit 6 are cut off, and the other ends of the capacitors CCA and CCB are set in a floating state.

Next, at the timing of the period t11 shown in FIG. 6, the control pulse φPX1 is held at a low level,
Further, the control pulse φSA is raised to a high level. By the fall of the control pulse φPX1, the MOS of the first row
Switch QX conducts. At this time, the gate region of the amplifier element QA holds the previously transferred signal charge. Therefore, the source follower circuit including the amplifying element QA outputs the pixel output Vold of the previous and first row to the vertical read line 2.

On the other hand, on the side of the different value detection circuit 6, the rise of the control pulse φSA causes the MOS switches QB1, QB
2 conducts. As a result, a charging path passing through the capacitors CCA and CCB is temporarily formed. As a result, a voltage of (Vold-VT + Vth) is charged at both ends of the capacitor CCA.

On the other hand, (V
old-VT-Vth). This period t
Immediately before the end of 11, the control pulse φSA falls. Therefore, the other ends of the capacitors CCA and CCB enter a floating state again. As a result, the above voltage is held as the voltage between both ends of the capacitors CCA and CCB.

Next, at the timing of the period t12 shown in FIG. 6, the control pulse φRG1 falls to a low level. Then, in the unit pixel 1 in the first row, the MOS switch QP is turned on, and the signal charges of the previous frame held in the gate region of the amplification element QA are discharged. As a result, the gate region is initialized to the reset voltage VRD via the wiring layer.

Just before the end of the period t12, the control pulse φ
RG1 is returned to the high level. As a result, the MOS switch QP is shut off, and the gate region of the amplifier element QA holds the voltage at the time of reset, while remaining in a floating state.
Next, at the timing of the period t13, the control pulse φ
TG1 falls to a low level. Then, in the unit pixel 1 in the first row, the MOS switch QT is turned on,
The signal charge accumulated in the photodiode PD in the first row is
The data is transferred to the gate region of the amplification element QA.

Just before the end of this period t13, the control pulse φ
TG1 is returned to the high level. As a result, the MOS switch QT is shut off, and the gate region of the amplifier element QA maintains a state in which the potential has increased in accordance with the transferred signal charge while the gate region is in a floating state. At this time, the control pulse φ
Since PX1 is still maintained at the low level, the latest pixel output Vnow of the first row is output from the vertical read line 2 via the source follower circuit of the amplifier QA.

In this state, (Vnow−Vold + VT) is connected to the other end of the capacitor CCA on the different value detection circuit 6 side.
−Vth) appears. Further, a voltage of (Vnow-Vold + VT + Vth) appears on the other end of the capacitor CCB. These voltages are supplied to the inverters INV1, IV
The signal is inverted at the threshold voltage VT via NV2.

According to the above voltage relationship, when the pixel output difference (Vnow-Vold) between frames exceeds Vth, the inverter INV1 outputs a low level. On the other hand, when the pixel output difference (Vnow-Vold) between frames is lower than Vth, the inverter INV1 outputs a high level. The pixel output difference (Vnow−Vold) between frames is (−V
When th) is exceeded, the inverter INV2 outputs a low level. On the other hand, the pixel output difference between frames (Vnow-Vo
When (ld) falls below (−Vth), the inverter INV2 outputs a high level.

These logic outputs are connected to the inverter INV3
After passing through ５5, they are respectively input to the NAND circuit NA. As a result, from the NAND circuit NA, the value of the pixel output difference (Vnow−Vold) between the frames is (−Vth) to Vt.
If it is within the allowable range of h, a low level is output.
When the value of the pixel output difference (Vnow−Vold) between frames is outside the allowable range of (−Vth) to Vth, a high level is output. With such an operation, the NAND circuit NA outputs a binarized signal indicating whether or not the pixel output between frames matches within an allowable range.

Subsequently, in a period t14 shown in FIG.
The control pulse φLD is raised to a high level. As a result, the binary signals output from the m NAND circuits NA are output to the parallel input terminals Q1 to Qm of the shift register 9.
And the internal value D of the shift register 9
1 to Dm. Next, at the timing of the period t15 shown in FIG. 6, the control pulse φSB rises to cause the MOS switches QB3, QB4
Becomes conductive. As a result, inverters INV3 and INV4
, The capacitors CCA and CCB are recharged in the positive feedback direction, and the output of the NAND circuit NA is stabilized.

In this state, transfer pulse φCK is sequentially applied to shift register 9. This transfer pulse φCK
, The internal values D1 to Dm are output as moving object signals from the serial output of the shift register 9. On the other hand, the horizontal scanning circuit 8 controls the control pulses φH1 to φH1.
φHm is set successively to the high level instead of φHm. Therefore, the vertical read lines 2 for m columns are sequentially connected to the horizontal read lines 7 in the order of 1 to m columns. As a result, the image signals of the first row are sequentially output on the horizontal read line 7.

By repeating the above-described series of scanning processes for the first row in the order of the second to n-th rows, an image signal is output from the horizontal readout line 7 and a moving object signal is output from the shift register 9. Is done. (B) Scanning operation in second vertical period During this second vertical period, control pulses φRG1 to n and n
TG1-n are always set to the high level. Further, the transfer clock φCK stops.

Therefore, the gate regions of all the amplifying elements QA are set to the floating state, and hold the potential set in the first vertical period as it is. On the other hand, the anode regions of all the photodiodes PD are also set to the floating state, and accumulate signal charges continuously from the first vertical period. In such a state, the control pulse φPX1 falls to the low level at the timing of the period t21 shown in FIG. As a result, M
The OS switch QX conducts, and the source of the amplification element QA in the first row is connected to the vertical read line 2. At this time, the gate region of the amplification element QA is maintained at the same potential as in the first vertical period. Therefore, the same pixel output as in the first vertical period is output to the vertical readout line 2 via the source follower circuit of the amplification element QA.

Next, the pixel output on the vertical read line 2 is sequentially output to the horizontal read line 7 by performing the horizontal transfer operation of the pixel output at the timing of the period t25 shown in FIG. Just before the end of this period t25, the control pulse φPX1 is returned to the high level. As a result, the MOS switches QX arranged in the first row are turned off, and the amplification element QA in the first row is disconnected from the vertical read line 2.

By repeating the series of scanning operations for the first row as described above for the other rows 2 to n, the read scanning in the second vertical period is completed. (C) Scanning operation in third vertical period The same scanning operation as in the second vertical period is performed. (D) Scanning operation in fourth vertical period The same scanning operation as in the first vertical period is performed.

(Effects of Second Embodiment, etc.) According to the operation described above, in the second embodiment, the same effects as those of the first embodiment can be obtained for image signals.
In addition, in the second embodiment, a moving object signal can be efficiently generated by comparing pixel outputs immediately before and after the signal charge transfer operation by the charge transfer MOS switch QT. .

In the second embodiment, the flicker phenomenon is suppressed by setting the accumulation time. Therefore, a high-precision moving object signal can be generated without erroneously detecting a luminance level change due to the flicker phenomenon as a moving object. Further, in the second embodiment, there is a temporal difference corresponding to a plurality of scanning periods between the pixel outputs to be compared. For this reason, an image change (for example, a band-like difference region caused by the movement of an edge portion in an image) is large even for a slowly moving subject. As a result, a slow-moving subject can be reliably and accurately detected.

In the above-described first and second embodiments, signal charges are read from the photodiode PD to the amplifying element QA at a rate of once in three read scans. However, the present invention is not limited to this. is not. Generally, the effect of the present invention can be obtained by reading out the signal charges once in a plurality of readout scans.

[0090]

According to the first or second aspect of the present invention, the pixel output is not read out from the light receiving section during a period of a plurality of readout scans. for that reason,
In the light receiving section, photoelectric conversion is continued during a period required for a plurality of read scans. With such an operation, the accumulation time of the light receiving section is set longer than the period of the readout scan.

On the other hand, the image scanning circuit repeatedly scans the pixel output held in the pixel output holding section. As a result, the same pixel output is read from the pixel output holding unit a plurality of times. Therefore, the periodic read scan is not interrupted. As described above, according to the present invention, it is possible to easily realize a conventionally contradictory operation of performing the periodic read scan and making the accumulation time of the light receiving unit longer than the read scan cycle. Become.

In particular, by taking advantage of the advantage that the storage time of the light receiving section is not limited to the read-out scanning cycle in the present invention, a photographing method such as setting the storage time to be longer than the read-out scanning cycle (a kind of photography) Sensitized shooting). In addition, by taking advantage of the advantage of the present invention that the periodic reading scan is not interrupted regardless of the length of the accumulation time, the rewriting operation of the monitor screen is interrupted even during the long-time accumulation operation of the light receiving unit. It is possible to configure an electronic camera or the like that executes independently and at a small size and at low cost.

Further, in the present invention, when the accumulation time is made sufficiently long, the fluctuation of the amount of received light due to the blinking of the illumination light is averaged, so that the flicker phenomenon caused by the blinking of the illumination light can be reduced. (Claim 3) In the invention according to claim 3, since the accumulation time of the light receiving section is set to a multiple of the "blink cycle of illumination light", the amount of received light per accumulation time depends on the phase of the blink cycle. Without becoming, it becomes almost constant. Therefore, in an environment of flickering illumination light, it is possible to make the luminance level of the image signal substantially constant and suppress the flicker phenomenon more reliably.

(Claim 4) In the invention according to claim 4,
By the operation of the electronic shutter circuit, the accumulation time of the light receiving unit is set to a multiple of the “blink cycle of illumination light”. for that reason,
The amount of received light per accumulation time is substantially constant without depending on the phase of the blinking cycle. Therefore, under the environment of blinking illumination light, the luminance level of the image signal is almost constant,
It is possible to more reliably suppress the flicker phenomenon.

(Claim 5) In the invention according to claim 5,
The pixel output before and after the transfer operation of the pixel output transfer unit is subjected to signal processing in the time axis direction. Since effective signal information in the time axis direction is included between such pixel outputs, it is possible to efficiently generate an effective signal processing result.

(Claim 6) In the invention according to claim 6,
A moving object signal is generated by comparing pixel outputs before and after the transfer operation of the pixel output transfer unit. Since effective information regarding the movement of the subject is included between such pixel outputs,
Effective moving object signals can be efficiently generated.

Further, according to the invention of claim 6, since the accumulation time of the light receiving section can be set longer than the period of the reading scan, the flicker phenomenon is reduced. For this reason, the possibility that the fluctuation of the luminance level due to the flicker phenomenon is erroneously detected as a moving object is reduced, and a more reliable moving object signal can be generated.

Further, in the invention according to claim 6, there is a temporal gap corresponding to a plurality of scanning periods between pixel outputs before and after the transfer operation of the pixel output transfer unit. Therefore, image change (for example,
A band-like area generated with movement of an edge portion in an image) becomes large. As a result, a slowly moving subject can be reliably detected as a moving object.

(Seventh Aspect) According to the seventh aspect of the present invention, the function required for the pixel output holding unit is realized by a source follower circuit including a field effect transistor. for that reason,
The circuit scale per unit pixel can be reduced, and the aperture ratio of the light receiving unit can be further increased.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a circuit configuration of a solid-state imaging device according to a first embodiment.

FIG. 2 is a timing chart illustrating read scanning in the first embodiment.

FIG. 3 is a diagram illustrating an effect of suppressing a flicker phenomenon in the first embodiment.

FIG. 4 is a diagram illustrating a circuit configuration of a solid-state imaging device according to a second embodiment.

FIG. 5 is a diagram illustrating a circuit example of an outlier detection circuit 6;

FIG. 6 is a timing chart illustrating read scanning in the second embodiment.

FIG. 7 is a diagram showing an embodiment having an electronic shutter function.

FIG. 8 is a diagram showing a conventional motion detection image processing apparatus 100.

FIG. 9 is a diagram illustrating a flicker phenomenon accompanying flickering of illumination light.

[Explanation of symbols]

Reference Signs List 1 unit pixel 2 vertical readout line 3 vertical scanning circuit 4 current source 6 outlier detection circuit 7 horizontal readout line 7a video amplifier circuit 8 horizontal scanning circuit 9 shift register 10 solid-state imaging device 20 solid-state imaging device 100 image processing device for motion detection PD Photodiodes QRSV1 to m MOS switch for resetting vertical readout line 2 MOSH for resetting horizontal readout line 7
S switch QH1 to m MOS switch for horizontal scanning QA amplifying element QT MOS switch for charge transfer QP MOS switch for resetting signal charges held QX MOS switch for vertical transfer

Claims (7)

[Claims] 1. A plurality of light receiving units arranged in a matrix and generating pixel outputs according to the amount of received light, provided for each of the light receiving units, holding the pixel output, and non-destructing the held pixel output. A pixel output holding unit that outputs a pixel output from the light receiving unit to the pixel output holding unit, and a pixel output holding unit that updates a pixel output held by the pixel output holding unit; and An image scanning circuit that scans the output pixel output and generates an image signal of a frame unit or a field unit or a part thereof, wherein the pixel output transfer unit performs a plurality of read scans by the image scanning circuit. 1 in
A solid-state imaging device wherein a pixel output is transferred from the light receiving unit to the pixel output holding unit each time. 2. The solid-state imaging device according to claim 1, wherein the image scanning circuit outputs a vertical read line provided for each vertical column of the light receiving unit, and a pixel output of the pixel output holding unit to a horizontal line. A vertical scanning unit that sequentially selects the unit and connects to the vertical readout line, and a horizontal scanning unit that horizontally scans a pixel output of a horizontal line unit sequentially output from the group of the vertical readout lines. Characteristic solid-state imaging device. 3. The solid-state imaging device according to claim 1, wherein the pixel output transfer unit sets a common multiple of “a period of readout scanning in the image scanning circuit” and “blinking period of illumination light”. A solid-state imaging device, wherein a pixel output is transferred from the light receiving unit to the pixel output holding unit at a corresponding cycle. 4. The solid-state imaging device according to claim 1, wherein the pixel output transfer section transfers a pixel output from a light receiving section by a multiple period of a “blink cycle of illumination light”. And an electronic shutter circuit for initializing the pixel output of the light receiving section. 5. The solid-state imaging device according to claim 1, wherein the pixel output from the pixel output holding unit is set immediately before and after the pixel output is transferred by the pixel output transfer unit. A signal processing circuit that captures an output and performs signal processing in a predetermined time axis direction on these successive pixel outputs; and a processing result scanning circuit that scans and outputs a processing result by the signal processing circuit. A solid-state imaging device. 6. The solid-state imaging device according to claim 5, wherein the signal processing circuit fetches a pixel output from the pixel output holding unit immediately before or after a pixel output is transferred by the pixel output transfer unit. A solid-state imaging device for generating a moving object signal of an image by comparing these successive pixel outputs. 7. The solid-state imaging device according to claim 1, wherein the pixel output holding unit holds the pixel output in a gate capacitance, and the pixel output held in the gate capacitance. A solid-state imaging device comprising a field-effect transistor circuit that non-destructively outputs as a source follower output.