JPH11205151A - Modulator and oversample type a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a modulator of high modulation accuracy. SOLUTION: An integrator 14 turns the difference voltage between input analog signals and feedback signals to an integrated input voltage, and integrates the difference voltage between the integrated input voltage and a first reference voltage. A quantization circuit 4 quantizes the integrated output of the integrator 14 by size relation with a second reference voltage. A sampling capacitor column 9 is constituted of weight plural capacitors, and generates the feedback signals from the output of the quantization circuit 4. A switch group 11 is constituted of plural switches for switching and connecting the plural capacitors for constituting the sampling capacitor column 9 to the two kinds or respective voltage sources Vrefp and Vrefm to be a reference for generating the feedback signals. Digital logic 13 switches the switch group 11 at a timing set beforehand. The quantization circuit 14 is constituted by using a comparator and is provided with an inverter 42 the capacitor 41 and the switch 40. Then, an operation is performed so as to turn the first reference voltage and the second reference voltage to the voltage equal to the offset voltage of a unit gain amplifier 131.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulator and an oversampled A / D converter, and more particularly, to an oversampled A / D converter for digitally encoding an analog signal, and the A / D converter. The present invention relates to a modulator used in a converter.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a basic configuration of an oversampled A / D converter. The oversampled A / D converter includes an input terminal 1, a modulator 80, a digital filter 81, and an output terminal 100.

[0003] A modulator 80 samples an analog signal input from an input terminal 1 at a frequency much higher than the frequency of the analog signal, and quantizes the sampled analog signal to convert the analog signal. Modulate to a digital signal. The digital filter 81 is
The quantization noise included in the high frequency band of the digital signal output from the modulator 80 is removed, and the sampling rate of the digital signal is reduced. The digital signal from which the quantization noise has been removed and the sampling rate has been reduced is output from the output terminal 100.

FIGS. 10A to 10C are block diagrams showing various types of the modulator 80. FIG. In FIG. 10, FIG.
The same reference numerals are used for the same components as those shown in FIG. FIG. 10A is a block diagram illustrating a basic configuration of a first-order ΔΣ modulator 80.

A first-order ΔΣ modulator 80 has an input terminal 1,
The adder 91, the integrator 14, the quantization circuit 4, the delay unit 90,
It comprises a D / A converter 93 and an output terminal 101. The adder 91 subtracts the output of the D / A converter 93 from the analog signal input from the input terminal 1. Integrator 1
4 integrates the output of the adder 91, and the quantization circuit 4 quantizes the output of the integrator 14. The output of the quantization circuit 4 is output from the output terminal 101 and is also fed back to the D / A converter 93 via the delay unit 90.

That is, the primary ΔΣ modulator 80 integrates the difference between the analog signal input from the input terminal 1 and the quantized signal output from the quantization circuit 4 by the integrator 14, This is a modulator that obtains a quantized signal that minimizes the integration result. Here, when the modulator 80 is operated at an extremely high frequency as compared with the frequency of the analog signal input from the input terminal 1, the quantization noise is distributed in a high frequency band due to the characteristics of the integrator 14. . Since the quantization noise distributed in the high frequency band is removed by the digital filter 81 to which the output from the output terminal 101 is input, a high-precision A / D conversion is performed on the analog signal input from the input terminal 1. It can be performed.

FIG. 10B shows a second-order ΔΣ modulator 80.
FIG. 2 is a block diagram illustrating a basic configuration of FIG. The second-order ΔΣ modulator 80 includes an input terminal 1, adders 91 and 92, an integrator 1
4, 15; quantization circuit 4; delay unit 90; D / A converter 9
3. An output terminal 101 is provided.

The adder 91 subtracts the output of the D / A converter 93 from the analog signal input from the input terminal 1.
The integrator 14 integrates the output of the adder 91. Adder 92
Subtracts the output of the D / A converter 93 from the output of the integrator 14. The integrator 15 integrates the output of the adder 92, and the quantization circuit 4 quantizes the output of the integrator 15. The output of the quantization circuit 4 is output from the output terminal 101 and is also fed back to the D / A converter 93 via the delay unit 90.

That is, the second-order ΔΣ modulator 80 is a modulator in which an integrator is provided in two stages by extending the first-order ΔΣ modulator, and is higher than the first-order ΔΣ modulator. Accurate A /
D conversion can be performed. FIG. 10C is a block diagram illustrating a basic configuration of a primary prediction primary noise shaping type modulator 80.

A primary prediction primary noise shaping type modulator 80 has an input terminal 1, adders 91 and 92, an integrator 1
4, 15; quantization circuit 4; delay unit 90; D / A converter 9
3. An output terminal 101 is provided. Adder 91
Is D / A from the analog signal input from the input terminal 1.
The output of the converter 93 is subtracted. The integrator 14 is an adder 91
, And the quantization circuit 4 quantizes the output of the integrator 14. The output of the quantization circuit 4 is passed through a delay unit 90,
The signal is sent to the adder 92 and also sent to the integrator 15.
The integrator 15 integrates the output of the delay unit 90. Integrator 15
Is output from the output terminal 101 and sent to the adder 92. The adder 92 adds the output of the delay unit 90 and the output of the integrator 15. The output of the adder 92 is D
The signal is fed back to the / A converter 93.

That is, the primary prediction primary noise shaping type modulator 80 integrates the quantized signal output from the quantization circuit 4 by the integrator 15 and uses the integration result as a prediction signal for predicting an analog signal. This is a modulator that integrates the difference between the predicted signal and the analog signal input from the input terminal 1 by the integrator 14 and obtains a quantized signal that minimizes the integration result. Therefore, according to the primary prediction primary noise shaping type modulator 80, A / D conversion with higher accuracy than the primary ΔΣ type modulator can be performed in order to predict an analog signal with a prediction signal. it can.

FIG. 11 is a block diagram showing a first-order predictive first-order noise shaping type modulator 80 disclosed in Japanese Patent Publication No. 7-79243. In FIG. 11, the same components as those of the modulator 80 shown in FIG. 10C are denoted by the same reference numerals. The integrator 14 includes the operational amplifier 2,
It comprises switches 20 to 24, an integration capacitor 5, and sampling capacitors 7 and 8. Input terminal 1 and operational amplifier 2
The switch 20, the sampling capacitor 7, and the switch 23 are connected in series in this order. The node between the switch 20 and the sampling capacitor 7 is grounded via the switch 21. A node between the sampling capacitor 7 and the switch 23 is a switch 22
, And is connected to a sampling capacitor array 9 via a sampling capacitor 8. The node between the sampling capacitor 8 and the sampling capacitor array 9 is grounded via the switch 24. An integration capacitor 5 is connected between the inverting input terminal and the output terminal of the operational amplifier 2,
The non-inverting input terminal of the operational amplifier 2 is grounded.

The quantizing circuit 4 comprises a comparator 102, the non-inverting input terminal of the comparator 102 is connected to the output terminal of the operational amplifier 2, the inverting input terminal of the comparator 102 is grounded, Output terminal is digital logic 1
3 is connected. The D / A converter 93 is composed of a digital logic 13, a sampling capacitance array 9, and a switch group 11. The sampling capacity array 9 is composed of a plurality of binary weighted capacitors, and switches a0, b0, a1, b1, a2, b connected in series to each of the capacitors.
Each capacitance is set to a D / A converter 9 by a switch group 11 composed of 2, a3, b3, a4, b4, a5, and b5.
3 is connected to one of the reference voltage sources Vrefp and Vrefm. The digital logic 13 controls the on / off operation of each switch constituting the switch group 11 based on the output of the quantization circuit 4. The digital logic 13
Has also the functions of the delay unit 90 and the integrator 15 and is connected to the output terminal 101.

FIG. 12 shows the switches 20 to 20 of the integrator 14.
4 is a timing chart of a control signal for controlling the on / off operation of the H.24. Each of the control signals f1 and f2 is a two-phase clock in which there is no overlap period in which the logic levels of both are “1” and there is a non-overlap period in which the logic levels of both are “0”.

The on / off operation of each of the switches 20, 22 is controlled in accordance with the control signal f1, and the switches are turned on when the logical level is "1" and turned off when the logical level is "0". The on / off operations of the switches 21, 23, and 24 are controlled in accordance with the control signal f2. The switches are turned on when the logical level is "1" and turned off when the logical level is "0".

[0016]

The integrator 1 shown in FIG.
4 is an analog signal input from the input terminal 1 and D /
A two-input integrator that inputs a feedback signal input from an A-converter 93 (sampling capacitor array 9). The integrator receives the analog input signal, the feedback signal, and the non-inverting input of the operational amplifier 2. It works to integrate the difference voltage from the input ground voltage. Here, in order to simplify the description, as shown in FIG. 13, a problem of the conventional technique will be described by taking an example of a one-input integrator 14a in which the switch 24 and the sampling capacitor 8 are omitted from the integrator 14. .

In the integrator 14a, first, the integration capacity 5
When the logic level of the control signal f1 is "1" (the logic level of the control signal f2 is "0"), the charge Q1 charged in the integration capacitor 5 and the charge in the sampling capacitor 7 are set to zero. The charge Q2 to be charged is obtained by the equations (1) and (2). At this time, the voltage (input voltage) of the analog signal input to the input terminal 1 is Vin, and the output voltage output from the output terminal 110 of the operational amplifier 2 is Vout1. Further, the capacitance value of the integration capacitance 5 is C0, and the capacitance value of the sampling capacitance 7 is C1.

Since the ground voltage input to the non-inverting input terminal of the operational amplifier 2 is 0 V, Q1 and Q2 are Vout1,
It is represented by the product of the difference voltage between Vin and the ground voltage 0V and each of the capacitance values C0 and C1, and is obtained as follows. Q1 = C0. (Vout1-0) = 0 (Equation 1) Q2 = C1 (Vin-0) (Equation 2) Then, the logic level of the control signal f1 is "0" (the control signal f2 Is switched to "1"), the charge Q3 charged in the integration capacitor 5 and the charge Q4 charged in the sampling capacitor 7 are obtained by equations (3) and (4). At this time, the output voltage (output voltage of the integrator 14) output from the output terminal 110 of the operational amplifier 2 is defined as Vout2.

Q3 = C0 · (Vout2-0) (Equation 3) Q4 = 0 (Equation 4) Since the charge stored in the integration capacitance 5 and the sampling capacitance 7 satisfies the charge conservation law, The sum is constant, and equation (5) is obtained from equations (1) to (4).

Vout2 = (C1 / C0) · Vin (Equation 5) By the way, when the operational amplifier 2 has the offset voltage Voff, the equivalent circuit of the integrator 14a shown in FIG.
This is like an integrator 14b shown in FIG. In the integrator 14b, the DC power supply 11 is connected to the non-inverting input terminal of the operational amplifier 2.
1 is connected, and an offset voltage Voff is applied.

In the integrator 14b, when the analysis is performed under the same conditions as the equations (1) to (5), the equations (6) to (1)
0) is required. Q1 = C0 · (Vout1−Voff) = 0 (Equation 6) Q2 = C1 · Vin (Equation 7) Q3 = C0 · (Vout2−Voff) (Equation 8) Q4 = C1 · (−Voff) (Equation 9) Vout2 = Voff + (C1 / C0) · (Vin + Voff) (Equation 10) As shown in the equation (10), if the operational amplifier 2 has the offset voltage Voff, The effect of the offset voltage Voff appears on the output voltage Vout2 of the operational amplifier 2, and when viewed from the output side of the integrator 14b, this is the same as the increase in the input voltage Vin by the offset voltage Voff. , The output voltage Vout2 increases.

Similarly, a two-input integrator 1 shown in FIG.
Also in 4, when the operational amplifier 2 has an offset voltage, the output voltage of the operational amplifier 2 is affected by the offset voltage, and the output voltage becomes unnecessarily large corresponding to the offset voltage. In the modulator 80 of the conventional primary prediction primary noise shaping type, the comparator 102 forming the quantization circuit 4 has an intermediate potential of the maximum input amplitude of the analog signal input from the input terminal 1 (in this example, ground). Voltage) is used as a reference to determine whether the output of the integrator 14 is large or small to perform quantization. Therefore, when the operational amplifier 2 has an offset voltage, the output of the integrator 14 becomes inaccurate due to the influence of the offset voltage.
The output of the quantization circuit 4 also becomes inaccurate. As a result, the modulation accuracy of the modulator 80 of the primary prediction primary noise shaping type is reduced.

By the way, as shown in FIG.
The modulator 80 has a configuration in which the integrator 15 and the adder 92 are omitted from the modulator 80 of the primary prediction primary noise shaping type, and the integrator 15 in the modulator 80 of the primary prediction primary noise shaping type. Is constituted by a digital logic 13. Therefore, the first-order ΔΣ modulator 8
Even at 0, when the operational amplifier 2 forming the integrator 14 has an offset voltage, the modulation accuracy is reduced as in the case of the primary prediction primary noise shaping type modulator 80.

FIG. 15 is a block diagram showing a concrete example of the modulator 80 of the second order Δ８０ type. In FIG. 15, FIG.
0 (b) and the same components as those of the modulator 80 shown in FIG. 11 have the same reference numerals. The integrator 14 includes the operational amplifier 2, switches 20 to 23, 28, an integration capacitor 5, and a sampling capacitor 7. A switch 20 is connected between the input terminal 1 and the inverting input terminal of the operational amplifier 2.
The sampling capacitor 7 and the switch 23 are connected in series in this order. The node between the switch 20 and the sampling capacitor 7 is grounded via the switch 21. The node between the sampling capacitor 7 and the switch 23 is grounded via the switch 22 and connected to the switch group 11 via the sampling capacitor 9a. A node between the sampling capacitor 9a and the switch group 11 is
It is grounded via a switch 28. The integration capacitor 5 is connected between the inverting input terminal and the output terminal of the operational amplifier 2, and the non-inverting input terminal of the operational amplifier 2 is grounded.

The integrator 15 includes the operational amplifier 3 and the switch 2
4 to 27, 29, an integrating capacitor 6, and a sampling capacitor 8. A switch 24, a sampling capacitor 8, and a switch 27 are connected in series in this order between the output terminal of the operational amplifier 2 and the inverting input terminal of the operational amplifier 3. The node between the switch 24 and the sampling capacitor 8 is grounded via the switch 25. The node between the sampling capacitor 8 and the switch 27 is connected to the switch 2
6, and is connected to the switch group 12 via the sampling capacitor 9b. The node between the sampling capacitor 9b and the switch group 12 is grounded via the switch 29. An integrating capacitor 6 is connected between the inverting input terminal and the output terminal of the operational amplifier 3, and the non-inverting input terminal of the operational amplifier 3 is grounded.

The D / A converter 93 is a digital logic 1
3, sampling capacitors 9a, 9b, switch groups 11, 1
2 is comprised. The sampling capacitor 9a is connected to one of the reference voltage sources Vrefp and Vrefm of the D / A converter 93 by a switch group 11 including switches f11 and f12 connected in series to the sampling capacitor 9a. The sampling capacitor 9b is connected to one of the voltage sources Vrefp and Vrefm, which are the reference of the D / A converter 93, by the switch group 12 including the switches f15 and f16 connected in series to the sampling capacitor 9b. . The digital logic 13 controls the on / off operation of each switch constituting each of the switch groups 11 and 12 based on the control signals f1 and f2 and the output of the quantization circuit 4 shown in FIG. Note that the digital logic 13 also has the function of the delay unit 90.

Each switch 20, 22, 25, 27, 29
Is turned on / off in accordance with a control signal f1 shown in FIG. 12, and is turned on when its logical level is "1".
Turns off when "0". In addition, each of the switches 21 and
3, 24, 26 and 28 are turned on in accordance with the control signal f2.
The off operation is controlled, and when the logic level is "1", the circuit is turned on, and when the logic level is "0", the circuit is turned off.

The integrator 14 of the thus-configured second-order ΔΣ modulator 80 converts the analog signal input to the input terminal 1 and the feedback signal formed by the sampling capacitor 9a and the switch group 11 and the like. This is a two-input integrator that functions to integrate the difference voltage between the voltage of each of the analog input signal and the feedback signal and the ground voltage input to the non-inverting input terminal of the operational amplifier 2. The integrator 15 is also a two-input integrator that inputs an output signal of the integrator 14 and a feedback signal formed by the sampling capacitor 9b and the switch group 12, and the like. The output signal of the integrator 14 and the feedback signal , And a function of integrating a difference voltage between the ground voltage input to the non-inverting input terminal of the operational amplifier 3 and the ground voltage.

However, as in the case of the first-order prediction first-order noise shaping type modulator 80 shown in FIG. 11, the integrators 14 and 15 shown in FIG. , 3 (the sampling capacitors 9a, 9b and the switch groups 11, 12 are omitted in FIG. 15, and the effects of the offset voltages of the operational amplifiers 2, 3 are examined).

The voltage (input voltage) of the analog signal input to the input terminal 1 is Vin, and the output voltage (output voltage of the integrator 15) output from the output terminal of the operational amplifier 3 is Vo1. The capacitance value of the integration capacitance 5 is C2, the capacitance value of the integration capacitance 6 is C0, the capacitance value of the sampling capacitance 7 is C3, and the capacitance value of the sampling capacitance 8 is C1.

Then, the operational amplifier 2 outputs the offset voltage V
off1 and the operational amplifier 3 has an offset voltage Voff2, an analysis similar to equation (10) yields equation (1)
1) is required. Vo1 = Voff2 + (C1 / C0) · {Voff1 + (C3 / C2) · (Vin + Voff1) + Voff2} (Equation 11) As shown in the equation (11), the operational amplifiers 2 and 3 respectively have offset voltages Voff1 and Voff1. With Voff2, the output voltage Vo1 of the operational amplifier 3 has the offset voltages Voff1, Voff
The effect of off2 appears, and each offset voltage Vo
The output voltage Vo1 increases corresponding to ff1 and Voff2.

Equation (11) is considered with a one-input integrator.
Similarly, even if the integrators 14 and 15 are two-input integrators as shown in FIG. 15, the output voltage of the integrator 15 increases corresponding to the offset voltages Voff1 and Voff2. In the conventional second-order ΔΣ modulator 80, the comparator 102 forming the quantization circuit 4 uses the intermediate potential (the ground potential in this example) of the maximum input amplitude of the analog signal input from the input terminal 1 as a reference. Next, it is determined whether the output of the integrator 15 is large or small, and quantization is performed. Therefore, if each of the operational amplifiers 2 and 3 has an offset voltage, the integrator 14 and the integrator 14 are affected by the offset voltage.
Since the output of 15 becomes inaccurate, the output of the quantization circuit 4 also becomes inaccurate. As a result, the modulation accuracy of the second-order ΔΣ modulator 80 is reduced.

As described above, in any of the modulators 80 shown in FIG. 10, when the operational amplifiers 2 and 3 constituting the integrators 14 and 15 have offset voltages, the modulator 8
The modulation accuracy of 0 is reduced. By the way, even when the integrators 14 and 15 do not have the configuration shown in FIGS. 11 and 15, if the integrators 14 and 15 are configured using operational amplifiers or other amplifiers, the operational amplifiers or other amplifiers may be used. If the amplifier has an offset voltage, the modulation accuracy of the modulator 80 also decreases.

When the modulation accuracy of the modulator 80 decreases, the A / D conversion accuracy of the oversampled A / D converter also decreases. The present invention has been made to solve the above problems, and an object of the present invention is to provide a modulator having high modulation accuracy. Another object of the present invention is to provide an oversampled A / D converter with high A / D conversion accuracy using a modulator with high modulation accuracy.

[0035]

According to the first aspect of the present invention, there is provided an integrator for integrating a difference voltage between an integrated input voltage and a first reference voltage.
A comparator, wherein the integrated output of the integrator is a second
And a quantization circuit that determines whether the voltage is higher or lower than the reference voltage and performs quantization. The integrator is configured using an amplifier having an offset voltage, and the first and second reference voltages are voltages equal to the offset voltage of the amplifier forming the integrator.

Thus, according to the invention, the integrator integrates the difference voltage between the integrated input voltage and the first reference voltage equal to the offset voltage. The quantization circuit determines whether the integrated output of the integrator is larger or smaller than the second reference voltage equal to the offset voltage and performs quantization. Therefore, even when the amplifier has an offset voltage, the integration operation by the integrator and the comparison operation by the comparator of the quantization circuit are performed based on the offset voltage of the amplifier, and the offset voltage affects the integration operation and the comparison operation. Will not give. Therefore, the influence of the offset voltage of the amplifier can be avoided, and high modulation accuracy can be obtained.

Next, according to the present invention, a difference voltage between the input analog signal and the feedback signal is used as an integral input voltage, and the difference voltage between the integral input voltage and the first reference voltage is integrated. An integrator and an integral output of the integrator is a second
A quantization circuit that determines whether the reference voltage is higher or lower than the reference voltage and performs quantization, a first sampling capacitor that generates a first reference voltage from an output of the quantization circuit, and A modulator comprising: a first switch group composed of switches connected to each of various types of reference voltage sources; and control logic for switching the first switch group at a preset timing. The integrator includes an amplifier having an offset voltage, an integration capacitance for holding a voltage of an integration result,
A second switch group composed of a second sampling capacitor and a plurality of switches; sampling an input analog signal at a constant period; transferring an obtained charge to the integration capacitor; And a circuit operable to input the first reference voltage to the first reference voltage and generate an offset voltage corresponding to the first reference voltage in the amplifier. Further, the first sampling capacitor is connected to the amplifier in parallel with the second sampling capacitor to sample a feedback signal. Further, the quantization circuit includes an inverter connected via an output terminal of an amplifier constituting the integrator and a capacitor, and a switch for short-circuiting an input / output terminal of the inverter during a sampling period of the integrator. And the first and second reference voltages are voltages equal to an offset voltage of an amplifier constituting the integrator.

Therefore, according to the present invention, the offset voltage of the amplifier forming the integrator is not included in the input voltage of the inverter forming the quantization circuit by the same operation as the first aspect of the present invention. The influence of the offset voltage of the amplifier can be avoided, and a modulator with high modulation accuracy can be obtained.

By the way, in the modulator according to the second aspect, when the first sampling capacity is composed of a capacity array having a plurality of weighted capacitors as in the invention according to the third aspect, one is used. A second-order prediction first-order noise shaping type modulator can be obtained. Further, in the modulator according to the second or third aspect, the amplifier constituting the integrator comprises a unit gain amplifier as in the invention according to the fourth aspect, or the amplifier according to the fifth aspect. It consists of an operational amplifier as in the invention.

Next, the invention according to claim 6 is directed to claim 2
6. The modulator according to any one of items 1 to 5, wherein the integrator sets a difference voltage between the input analog signal and the first feedback signal as a first integrated input voltage, A first voltage for integrating a difference voltage from the reference voltage
And the difference voltage between the integration output of the first integrator and the second feedback signal is defined as the second integration input voltage, and the difference voltage between the second integration input voltage and the third reference voltage is defined as And a second integrator for integration. Further, the quantization circuit determines whether the integrated output of the second integrator is higher or lower than a second reference voltage, and performs quantization. A first sampling capacitor for generating a first feedback signal from an output of the quantization circuit; a third sampling capacitor for generating a second feedback signal from an output of the quantization circuit; A first switch group composed of switches that switch and connect a sampling capacitor to each of two types of voltage sources serving as a reference for generating a feedback signal; A modulator comprising: a third switch group composed of switches connected to each of the sources by switching; and control logic for switching the first and third switch groups at a preset timing.
The first integrator includes a first amplifier having an offset voltage, a first integration capacitor for holding a voltage of a first integration result, a second sampling capacitor, and a plurality of switches. The second analog switch group, samples the input analog signal at a constant period, transfers the obtained charge to the first integration capacitor, and supplies the first amplifier to the first amplifier during a sampling period. And a circuit operable to input a reference voltage and to cause the first amplifier to generate an offset voltage corresponding thereto. Further, the first sampling capacitor is connected to the first amplifier in parallel with the second sampling capacitor to sample a first feedback signal. The second integrator includes a second amplifier having an offset voltage, a second integration capacitor for holding a voltage of a second integration result, a fourth sampling capacitor, and a plurality of switches. A fourth switch group, which samples the first integrated output at a constant period, transfers the obtained charge to the second integration capacitor, and supplies the third amplifier to the second amplifier during a sampling period. And a circuit operable to input a reference voltage and generate an offset voltage for the reference voltage in the second amplifier. Further, the third sampling capacitor is connected to the second sampling capacitor in parallel with the fourth sampling capacitor.
To sample the second feedback signal. The quantization circuit includes an inverter connected via a capacitor to an output terminal of a second amplifier constituting the second integrator, and an input / output terminal of the inverter during a sampling period of the second integrator. And a switch for short-circuiting an output terminal.
And the third reference voltage is a voltage equal to the offset voltage of the second amplifier constituting the second integrator.

Therefore, according to the present invention, the input voltage of the inverter constituting the quantization circuit does not include the offset voltage of the second amplifier, so that the influence of the offset voltage of the second amplifier can be avoided. become. Further, by setting the fourth sampling capacitance sufficiently smaller than the second integration capacitance, it is possible to reduce the influence of the offset voltage of the first amplifier so much that the modulation with high modulation accuracy is achieved. You can get a bowl.

Next, the invention according to claim 7 is directed to claim 4
In the modulator described in (1), the unit gain amplifier is constituted by a source follower circuit. The source follower circuit has a large offset voltage. However, according to the modulator of the fourth aspect, it is possible to avoid the influence of the offset voltage, so that a unit gain amplifier including a simple source follower can be used. . Further, since the unit gain amplifier has a gain of 1, it is less affected by noise than an operational amplifier having an infinite gain.

Therefore, according to the present invention, low power consumption, high speed, and high accuracy are provided with the excellent characteristics of the unit gain amplifier constituted by the source follower (low power consumption and high speed operation are possible with a simple structure). A modulator can be obtained.
Then, as in the invention according to claim 8, the modulator according to any one of claims 1 to 7, which has high modulation accuracy, is combined with a filter that removes quantization noise from the output of the modulator. Then, an oversampled A / D converter with high A / D conversion accuracy can be obtained.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. In the present embodiment, the same components as those in the conventional embodiment shown in FIGS. 9 to 12 have the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 is a block diagram showing a modulator 80 of the first-order prediction first-order noise shaping type according to the present embodiment.
The integrator 14 includes a unit gain amplifier 131, switches 20 to 25 as a second switch group, an integration capacitor 5, and a first sampling capacitor 7. The unit gain amplifier 131 is an amplifier having a gain of 1. Unit gain amplifier 1
The input terminal of the switch 31 is connected to each of the switches 21,
20, is connected to the input terminal 1 via the switch 22, is grounded via the switch 22, and is grounded via the switch 23 and the integrating capacitor 5 connected in series.
It is connected to the switch group 11 via the switches 24 and 25. A sampling capacitor 7 is connected between a node between the switches 20 and 21 and an output terminal of the unit gain amplifier 131. The sampling capacitor array 9 is connected to the output terminal of the unit gain amplifier 131.

The quantizing circuit 4 is composed of a comparator. The comparator comprises a switch 40, a capacitor 41, and an inverter 4.
2, 43 and a latch circuit 44. The inverters 42 and 43 are connected in series, the capacitor 41 is connected between the input terminal of the inverter 42 and the output terminal of the unit gain amplifier 131, and the switch 40 is connected between the input and output terminals of the inverter 42. Are connected to the digital logic (control logic) 13 via a latch circuit 44.

The D / A converter 93 is a digital logic 1
3, a sampling capacitor array 9 and a first switch group 11. The sampling capacitor array 9 is composed of a plurality of binary weighted capacitors, and switches S0, S1, S2, S3, and S4 connected in series to the respective capacitors are connected to the input terminal of the unit gain amplifier 131 via the switch 25. And the reference voltage sources Vrefp, Vrefp of the D / A converter 93 through the respective switches f13, f14.
Vrefm. In addition, the sampling capacity column 9
Is connected to the input terminal of the unit gain amplifier 131 via the switch 24, and the D / A is connected via the switches f11 and f12, respectively.
The converter 93 is connected to voltage sources Vrefp and Vrefm serving as references. The digital logic 13 switches the switches S0, S1, S2, S constituting the switch group 11 based on the control signal f1 and the output of the quantization circuit 4 shown in FIG.
3, S4, on / off operations of f11, f12, f13, f14 are controlled. Note that the digital logic 13 also has the functions of the delay unit 90 and the integrator 15 and that the output terminal 10
1 connected.

The on / off operation of each of the switches 20, 22, and 40 is controlled according to a control signal f1 shown in FIG.
It turns on when the logic level is "1" and turns off when it is "0". Also, the switches 21, 23, 24, 25
Has an on / off operation controlled according to a control signal f2,
It turns on when the logic level is "1" and turns off when it is "0".

Next, the operation of the present embodiment will be described. An integrator 14 shown in FIG. 1 is a two-input type that inputs an analog signal (input analog signal) input from an input terminal 1 and a feedback signal input from a D / A converter 93 (sampling capacitor array 9). Integrator. Here, in order to simplify the description, as shown in FIG. 2, a one-input integrator 14a in which the switches 24 and 25 are omitted from the integrator 14 will be described as an example.

Assuming that the offset voltage of the unit gain amplifier 131 is Voff, the input voltage Vui and the output voltage Vuo of the unit gain amplifier 131 are expressed by equation (12). Vuo = Vui + Voff (Equation 12) First, in the integrator 14a, the charge accumulated in the integration capacitor 5 is set to zero, and the logic level of the control signal f1 is "1" (the logic level of the control signal f2 is "0"). ), The charge Q1 charged in the integration capacitor 5 and the charge Q2 charged in the sampling capacitor 7 are obtained by the equations (13) and (14). At this time, the voltage (input voltage) of the analog signal input to the input terminal 1 is Vin. Further, the capacitance value of the integration capacitance 5 is C0, and the capacitance value of the sampling capacitance 7 is C1.

Q1 = 0 (Equation 13) Q2 = C1 · (Vin−Voff) (Equation 14) At this time, in the quantization circuit 4, the charge Q41 stored in the capacitor 41 is turned on. Since the input / output terminal of the inverter 42 is short-circuited by the switch 40, the equation (1)
5). Here, the capacitance value of the capacitor 41 is C4, and the threshold voltage of the inverter 42 is Vith.

Q41 = C4 · (Voff−Vith) (Equation 15) When the logic level of the control signal f1 is switched to “0” (the logic level of the control signal f2 is “1”), the integration capacitance The charge Q3 charged to 5 and the charge Q4 charged to the sampling capacitor 7 are obtained by equations (16) and (17).

Q3 = C0 · Vui (Equation 16) Q4 = C1 · (Vui−Vuo) (Equation 17) The electric charge stored in the integration capacitor 5 and the sampling capacitor 7 holds the charge conservation law. Therefore, the sum is constant, and Expression (18) is obtained from Expressions (12) to (17).

Vuo = Voff + (C1 / C0) · Vin (Equation 18) At this time, since the electric charge accumulated in the capacitor 41 is stored, the input voltage Vii of the inverter 42 is obtained by Expression (19). . Vii = Vuo− (Voff−Vith) (Equation 19) The equation (20) is obtained from the equations (18) and (19).

Vii = Vith + (C1 / C0) · Vin (Equation 20) As shown in the equation (20), the input voltage V
ii does not include the offset voltage Voff of the unity gain amplifier 131. The output voltage of the inverter 42 is based on the threshold voltage Vith. When the input voltage Vii is higher than the threshold voltage Vith, the output voltage is a value corresponding to the logic level “0”. become.

Similarly, the two-input integrator 14 shown in FIG.
In this case, the offset voltage Voff of the unit gain amplifier 131 is not included in the input voltage Vii of the inverter 42. That is, when the switch 22 is turned on in accordance with the control signal f1, the input terminal of the unit gain amplifier 131 is grounded via the switch 22, and the unit gain amplifier 1
The integrator 14 uses the offset voltage Voff output from the first reference voltage 31 as a first reference voltage, and calculates the difference voltage between the first reference voltage (= offset voltage Voff) and the input analog signal input from the input terminal 1. Integrate. When the switch 40 is turned on according to the control signal f1, the quantization circuit 4 outputs the unit gain amplifier 131 input from the integrator 14.
Is used as the second reference voltage, and when the switch 40 is turned off in accordance with the control signal f1, the second
Is determined by determining whether the reference voltage (= offset voltage Voff) is larger or smaller than the integrated output of the integrator 14.

In other words, the integration operation of the integrator 14 and the comparison operation of the quantization circuit 4 are performed by the unit gain amplifier 13.
That is, the offset voltage Voff is used as a reference. Therefore, in the modulator 80 of the primary prediction primary noise shaping type of the present embodiment, the integrator 1
Even when the unit gain amplifier 131 of the fourth circuit has an offset voltage, the offset voltage does not affect the output of the quantization circuit 4. Therefore, according to the first-order prediction first-order noise shaping type modulator 80 of the present embodiment, it is possible to avoid the influence of the offset voltage of the unit gain amplifier 131, and to obtain high modulation accuracy. As a result, as shown in FIG.
According to the oversampled A / D converter configured using the modulator 80 of the secondary prediction primary noise shaping type, a high A / D conversion accuracy can be obtained.

FIGS. 3A to 3C show the unit gain amplifier 1.
FIG. 31 is a circuit diagram illustrating a specific example of No. 31. The unit gain amplifier 131 shown in FIG. 3A is configured by a CMOS circuit including an N-channel MOS transistor 32 and a P-channel MOS transistor 33. The drain of the N-channel MOS transistor 32 is connected to the high potential power supply VDD. The drain of the channel MOS transistor 33 is connected to the low-potential-side power supply -VDD.
The gate of 33 is connected to the input terminal 30 of the unit gain amplifier 131, and the sources of the transistors 32 and 33 are connected to the output terminal 31 of the unit gain amplifier 131.

The unit gain amplifier 131 shown in FIG.
Are constituted by N-channel MOS transistors 32 and 35, and the drain of the N-channel MOS transistor 32 is connected to the high potential side power supply VDD.
The source of the transistor 35 is connected to the low potential side power supply -VDD, the gate of the N-channel MOS transistor 32 is connected to the input terminal 30 of the unit gain amplifier 131, the gate of the N-channel MOS transistor 35 is connected to the bias terminal 34, The source of the N-channel MOS transistor 32 and the drain of the N-channel MOS transistor 35 are connected to the output terminal 31 of the unit gain amplifier 131. A voltage slightly higher than the voltage of the low-potential-side power supply -VDD is applied to the bias terminal 34, and an N-channel MOS
Transistor 35 functions as the source resistance of N-channel MOS transistor constant 32.

The unit gain amplifier 131 shown in FIG.
Is constituted by P-channel MOS transistors 33 and 36, the source of the P-channel MOS transistor 36 is connected to the high-potential power supply VDD, the drain of the P-channel MOS transistor 33 is connected to the low-potential power supply -VDD, The gate of MOS transistor 33 is connected to input terminal 30 of unity gain amplifier 131, the gate of P-channel MOS transistor 36 is connected to bias terminal 34, and the source of P-channel MOS transistor 33 and the drain of P-channel MOS transistor 36 are unity. It is connected to the output terminal 31 of the gain amplifier 131. A voltage slightly lower than the voltage of the high-potential-side power supply VDD is applied to the bias terminal 34, and the P-channel MOS transistor 36
3 functions as a source resistance.

A unit gain amplifier 131 constituted by a source follower circuit as shown in FIGS.
Since the offset voltage is large, it is not generally used in applications requiring high accuracy. However, in the first embodiment,
According to the modulator 80 of the first-order prediction first-order noise shaping type, the influence of the offset voltage of the unit gain amplifier 131 is avoided, so that the unit gain amplifier 131 constituted by a simple source follower circuit can be used.

The unit gain amplifier 131 constituted by the source follower circuit has the following advantages. Since the number of cascaded stages of the MOS transistors is two, M
The power supply voltage can be reduced as compared with an operational amplifier having three cascaded OS transistors.

The current consumption is smaller than that of the operational amplifier. As described above, it is advantageous for low power consumption. Since no phase compensation capacitance is required, high-speed operation is possible. Since the gain is 1, it is less susceptible to the thermal noise of the MOS transistor than an operational amplifier having an infinite gain.

As described above, the integrator 14 using the unit gain amplifier 131 constituted by the source follower circuit
According to this, it is possible to obtain a high-speed and high-accuracy modulator 80 and an oversampling A / D converter with low power consumption. (Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the drawings. In this embodiment, the same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 4 is a block diagram showing a first-order prediction first-order noise shaping type modulator 80 of the present embodiment.
The integrator 14 includes the operational amplifier 2, switches 20 to 25 as a second switch group, an integration capacitor 5, and a first sampling capacitor 7. The inverting input terminal of the operational amplifier 2 is connected to the input terminal 1 via the sampling capacitor 7 and the switch 20 connected in series, and is connected to the output terminal of the operational amplifier 2 via the switch 22. Are connected to the output terminal of the operational amplifier 2 via the integrating capacitor 5 and the switch 23 connected to the sampling capacitor array 9. The non-inverting input terminal of the operational amplifier 2 is grounded. The node between the sampling capacitor 7 and the switch 20 is grounded via the switch 21.

The configuration of the quantization circuit 4 is the same as that of the first embodiment, and the capacitor 41 is connected between the input terminal of the inverter 42 and the output terminal of the operational amplifier 2. D /
The A-converter 93 includes the digital logic 13, the sampling capacitance array 9, and the first switch group 11.
The sampling capacitor array 9 is composed of a plurality of capacitors weighted in binary, and switches S0, S1, S2, S3, and S4 connected in series to the respective capacitors are connected to the non-inverting input of the operational amplifier 2 via the switch 25. Connected to the terminal,
The switches are connected to voltage sources Vrefp and Vrefm, which serve as references for the D / A converter 93, via the switches f13 and f14, respectively. A sampling capacitor 9a constituting the sampling capacitor array 9 is connected to a non-inverting input terminal of the operational amplifier 2 via a switch 24, and is connected to each switch f1.
1 and f12 are connected to voltage sources Vrefp and Vrefm, which are the reference of the D / A converter 93, respectively. The digital logic 13 switches S0, S1, S2, S3, S4, f11, f constituting the switch group 11 based on the control signal f1 shown in FIG.
On / off operations of 12, f13 and f14 are controlled.
The digital logic 13 also has functions of the delay unit 90 and the integrator 15 and is connected to the output terminal 101.

The on / off operation of each of the switches 20, 22, and 40 is controlled according to a control signal f1 shown in FIG.
It turns on when the logic level is "1" and turns off when it is "0". Also, the switches 21, 23, 24, 25
Has an on / off operation controlled according to a control signal f2,
It turns on when the logic level is "1" and turns off when it is "0".

Next, the operation of the present embodiment will be described. The integrator 14 shown in FIG. 4 is a two-input integrator that inputs an analog signal input from the input terminal 1 and a feedback signal input from the D / A converter 93 (sampling capacitance array 9). . Here, in order to simplify the description, the switches 24 and 25 are omitted from the integrator 14.
An input type integrator will be described as an example.

In the integrator 14, first, the charge accumulated in the integration capacitor 5 is set to zero, and when the logic level of the control signal f1 is "0" (the logic level of the control signal f2 is "1"), the input terminal The voltage (input voltage) of the analog signal input to 1 is Vin, the output voltage (output voltage of the integrator 14) output from the output terminal of the operational amplifier 2 is Vout1, and the offset voltage of the operational amplifier 2 is Voff. .

When the logic level of the control signal f1 is switched to "1" (the logic level of the control signal f2 is "0"), the charge Q1 charged in the integration capacitor 5 and the sampling capacitor 7 are charged. The charge Q2 is calculated by the equation (21).
Determined by (22). Here, the capacitance value of the integration capacitance 5 is C0, and the capacitance value of the sampling capacitance 7 is C1.

Q1 = C0 · (Vout1−Voff) = 0 (Equation 21) Q2 = C1 · (Vin−Voff) (Equation 22) At this time, in the quantization circuit 4, the data is accumulated in the capacitor 41. Since the input Q41 is short-circuited between the input and output terminals of the inverter 42 by the switch 40 that is turned on, the equation (2)
3). Here, the capacitance value of the capacitor 41 is C4, and the threshold voltage of the inverter 42 is Vith.

Q41 = C4 · (Voff−Vith) (Expression 23) When the logical level of the control signal f1 is switched to “0” (the logical level of the control signal f2 is “1”), the integration capacity The charge Q3 charged to 5 and the charge Q4 charged to the sampling capacitor 7 are obtained by equations (24) and (25). At this time, the output voltage (output voltage of the integrator 14) output from the output terminal of the operational amplifier 2 is defined as Vout2.

Q3 = C0 · (Vout2−Voff) (Equation 24) Q4 = C1 · (−Voff) (Equation 25) The electric charge stored in the integration capacitance 5 and the sampling capacitance 7 is stored. Since the rule holds, the sum is constant, and Expression (26) is obtained from Expressions (21) to (25).

Vout2 = Voff + (C1 / C0) · Vin (Equation 26) At this time, since the electric charge accumulated in the capacitor 41 is stored, the input voltage Vii of the inverter 42 is obtained by Expression (27). . Vii = Vout2- (Voff-Vith) (Expression 27) Expression (28) is obtained from Expressions (26) and (27).

Vii = Vith + (C1 / C0) · Vin (Expression 28) As shown in Expression (28), the input voltage V
ii does not include the offset voltage Voff of the operational amplifier 2. The output voltage of the inverter 42 is based on the threshold voltage Vith. When the input voltage Vii is higher than the threshold voltage Vith, the output voltage is a value corresponding to the logic level “0”. become. This means that the integration operation in the integrator 14 and the comparison operation in the quantization circuit 4 are:
That is, the operation is performed based on the offset voltage Voff of the operational amplifier 2.

Similarly, the two-input integrator 14 shown in FIG.
In this case, the input voltage Vii of the inverter 42 does not include the offset voltage Voff of the operational amplifier 2. That is, when the switch 22 is turned on according to the control signal f1, the inverting input terminal and the output terminal of the operational amplifier 2 are connected via the switch 22, so that the non-inverting input terminal of the operational amplifier 2 is grounded. The offset voltage Voff output from the operational amplifier 2 is input to the inverting input terminal of the operational amplifier 2 via the switch 22. Therefore, the integrator 14 uses the offset voltage Voff output from the operational amplifier 2 as the first reference voltage, and calculates the first reference voltage (= offset voltage Voff) and the input analog signal input from the input terminal 1. Is integrated. Then, the quantization circuit 4 switches the switch 4 according to the control signal f1.
When 0 is turned on, the offset voltage Voff of the operational amplifier 2 input from the integrator 14 is used as a second reference voltage. When the switch 40 is turned off according to the control signal f1, the second reference voltage (= offset voltage Voff) ) Is the integrator 1
Quantization is performed by judging whether the integrated output is larger or smaller than the integral output of No. 4.

This is the only operation in which the integration operation in the integrator 14 and the comparison operation in the quantization circuit 4 are performed with reference to the offset voltage Voff of the operational amplifier 2. Therefore, in the primary prediction primary noise shaping type modulator 80 of the present embodiment, even if the operational amplifier 2 forming the integrator 14 has an offset voltage,
The offset voltage does not affect the output of the quantization circuit 4. Therefore, according to the modulator 80 of the first-order prediction first-order noise shaping type of the present embodiment, it is possible to avoid the influence of the offset voltage of the operational amplifier 2 and obtain high modulation accuracy. As a result, FIG.
As shown in (1), according to the oversampled A / D converter configured using the primary prediction primary noise shaping type modulator 80 of the present embodiment, high A / D conversion accuracy can be obtained. .

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings. In this embodiment, the same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 5 is a block diagram showing a first-order ΔΣ modulator 80 of the present embodiment. The modulator 80 of the primary ΔΣ type shown in FIG. 5 differs from the modulator 80 of the primary prediction primary noise shaping type shown in FIG. 1 only in the following points. [1] The capacities other than the second sampling capacitors 9a among the capacitors constituting the sampling capacitor array 9 are omitted.

[2] Switch 25 Constituting Integrator 14
Has been omitted. Further, switches excluding switches f11 and f12 among the switches constituting the switch group 11 are omitted. [3] The digital logic 13 has the function of the delay unit 90, and the latch circuit 44 constituting the quantization circuit 4 is connected to the output terminal 101.

Therefore, according to the modulator 80 of the first-order ΔΣ type of the present embodiment, similarly to the modulator 80 of the first-order prediction first-order noise shaping type of the first embodiment, the unit gain constituting the integrator 14 is used. Even when the amplifier 131 has an offset voltage, the offset voltage does not affect the output of the quantization circuit 4. Therefore, the first-order ΔΣ of the present embodiment
According to the modulator 80 of the shape, the influence of the offset voltage of the unit gain amplifier 131 can be avoided, and high modulation accuracy can be obtained. As a result, as shown in FIG. 9, according to the oversampled A / D converter configured using the first-order ΔΣ modulator 80 of the present embodiment, a high A is obtained.
/ D conversion accuracy can be obtained.

In this embodiment, as in the first embodiment, the unit gain amplifier 13 constituted by a simple source follower circuit as shown in FIGS.
1 can be used, the unit gain amplifier 13
Taking advantage of (1), it is possible to obtain a high-speed and high-accuracy modulator 80 and an oversampling A / D converter with low power consumption.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to the drawings. In this embodiment, the same components as those in the second embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 6 is a block diagram showing a first-order ΔΣ modulator 80 of the present embodiment. The modulator 80 of the primary ΔΣ type shown in FIG. 6 differs from the modulator 80 of the primary prediction primary noise shaping type shown in FIG. 4 only in the following points. [1] The capacities other than the sampling capacity 9a among the capacities constituting the sampling capacity row 9 are omitted.

[2] Switch 25 Constituting Integrator 14
Has been omitted. Further, switches excluding switches f11 and f12 among the switches constituting the switch group 11 are omitted. [3] The digital logic 13 has the function of the delay unit 90, and the latch circuit 44 constituting the quantization circuit 4 is connected to the output terminal 101.

Therefore, according to the modulator 80 of the first-order ΔΣ type of the present embodiment, similarly to the modulator 80 of the first-order prediction first-order noise shaping type of the second embodiment, the operational amplifier constituting the integrator 14 is used. Even if 2 has an offset voltage, the offset voltage does not affect the output of the quantization circuit 4. Therefore, according to the first-order ΔΣ modulator 80 of the present embodiment, it is possible to avoid the influence of the offset voltage of the operational amplifier 2 and to obtain high modulation accuracy. As a result, as shown in FIG. 9, according to the oversampled A / D converter configured using the first-order ΔΣ modulator 80 of the present embodiment, high A / D conversion accuracy can be obtained. it can.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to the drawings. In this embodiment, the same components as those in the conventional embodiment shown in FIG. 15 are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 7 is a block diagram showing a second-order ΔΣ modulator 80 of this embodiment. The first integrator 14 includes a first operational amplifier 2, switches 20 to 23, 28 as a third switch group, a first integration capacitor 5, and a third sampling capacitor 7. The inverting input terminal of the operational amplifier 2 is connected to the input terminal 1 via a sampling capacitor 7 and a switch 20 connected in series.
The first sampling capacitor 9a is connected to the output terminal of the operational amplifier 2 via the switch 22 and to the output terminal of the operational amplifier 2 via the switch 23 and the integrating capacitor 5 connected in series. It is connected to the first switch group 11 via the switch. The non-inverting input terminal of the operational amplifier 2 is grounded. The node between the sampling capacitor 7 and the switch 20 is grounded via the switch 21. A node between the sampling capacitor 9a and the switch group 11 is grounded via the switch 28.

The second integrator 15 includes a second operational amplifier 3 and switches 24 to 27, 2 as a fourth switch group.
9, a second integration capacitor 6, and a fourth sampling capacitor 8. The inverting input terminal of the operational amplifier 3 is connected to the output terminal of the operational amplifier 2 via the sampling capacitor 8 and the switch 24 connected in series, and to the output terminal of the operational amplifier 3 via the switch 26. At the same time, it is connected to the output terminal of the operational amplifier 3 via the integrating capacitor 6 and the switch 27 connected in series, and to the second switch group 12 via the second sampling capacitor 9b. The non-inverting input terminal of the operational amplifier 3 is grounded. The node between the sampling capacitor 8 and the switch 24 is grounded via the switch 25. The node between the sampling capacitor 9b and the switch group 12 is grounded via the switch 29.

The configuration of the quantization circuit 4 is the same as that of the first embodiment, and the capacitor 41 is connected between the input terminal of the inverter 42 and the output terminal of the operational amplifier 3. D /
The A converter 93 includes a digital logic 13, sampling capacitors 9a and 9b, and switch groups 11 and 12. By a switch group 11 composed of switches f11 and f12 connected in series to the sampling capacitor 9a,
The sampling capacitor 9a is connected to one of the voltage sources Vrefp and Vrefm serving as a reference of the D / A converter 93. Also,
Switch f1 connected in series to sampling capacitor 9b
The sampling capacitor 9b is connected to one of the voltage sources Vrefp and Vrefm that is the reference of the D / A converter 93 by the switch group 12 composed of the switches 5 and f16. The digital logic 13 outputs a signal to each switch group 11, 1 based on the control signals f1, f2 and the output of the quantization circuit 4 shown in FIG.
2 controls the on / off operation of each switch.
Note that the digital logic 13 also has the function of the delay unit 90.

Each switch 20, 22, 25, 27, 29
Is turned on / off in accordance with a control signal f1 shown in FIG. 12, and is turned on when its logical level is "1".
Turns off when "0". In addition, each of the switches 21 and
The on / off operations of 3, 24, 26, 28, and 40 are controlled in accordance with the control signal f2.

Next, the operation of the present embodiment will be described. Incidentally, as described with reference to the conventional configuration of FIG. 15 by obtaining the equation (11), the integrators 14 and 15 of FIG.
The influence of the offset voltage of the operational amplifiers 2 and 3 is analyzed as an input integrator (in FIG.
a, 9b and the switch groups 11 and 12 are omitted to analyze the influence of the offset voltages of the operational amplifiers 2 and 3).

In the second-order Δ 次 modulator 80 of this embodiment, the voltage (input voltage) of the analog signal input to the input terminal 1 is Vin, and the output voltage (integrator) output from the output terminal of the operational amplifier 3 is 15 (the output voltage at 15) is Vo1.
The capacitance value of the integration capacitance 5 is C2, the capacitance value of the integration capacitance 6 is C0, the capacitance value of the sampling capacitance 7 is C3, and the capacitance value of the sampling capacitance 8 is C1.

Then, the operational amplifier 2 outputs the offset voltage V
off1 and the operational amplifier 3 has an offset voltage Voff2, an analysis similar to equation (11) yields equation (2)
9) is required. Vo1 = Voff2 + (C1 / C0) ｛{Voff1 + (C3 / C2) Vin} (Equation 29) That is, when the switch 22 is turned on according to the control signal f1, the inverted input terminal and the output terminal of the operational amplifier 2 Since the connection is made via the switch 22, the non-inverting input terminal of the operational amplifier 2 is grounded and the offset voltage Voff1 output from the operational amplifier 2 is connected to the inverting input terminal of the operational amplifier 2 via the switch 22. Is entered. Therefore, the integrator 14 uses the offset voltage Voff1 output from the operational amplifier 2 as the first reference voltage, and sets the first reference voltage (= offset voltage Voff1) and the input terminal 1
Integrates the difference voltage between the input analog signal and the input analog signal.

Further, according to the control signal f2, the switch 26
Is turned on, the inverting input terminal and the output terminal of the operational amplifier 3 are connected via the switch 26. Therefore, since the non-inverting input terminal of the operational amplifier 3 is grounded, the offset output from the operational amplifier 3 is output. The voltage Voff2 is input to the inverting input terminal of the operational amplifier 3 via the switch 26. Therefore, the integrator 15 uses the offset voltage Voff2 output from the operational amplifier 3 as the first reference voltage, and calculates the difference voltage between the first reference voltage (= offset voltage Voff2) and the integrated output of the integrator 14. Integrate.

Then, the quantizing circuit 4 changes the offset voltage Voff2 of the operational amplifier 3 input from the integrator 15 when the switch 40 is turned on according to the control signal f2 to the second.
When the switch 40 is turned off according to the control signal f2, the quantization is performed by determining whether the second reference voltage (= offset voltage Voff2) is larger or smaller than the integrated output of the integrator 15.

This is nothing other than that the integration operation in the integrator 15 and the comparison operation in the quantization circuit 4 are performed with reference to the offset voltage Voff2 of the operational amplifier 3. Therefore, the second-order ΔΣ modulator 8 of the present embodiment is used.
At 0, the offset voltage Voff2 of the operational amplifier 3 constituting the integrator 15 does not affect the output of the quantization circuit 4. Also, as can be seen by comparing Equation (11) and Equation (29), the second-order ΔΣ modulator 8 of the present embodiment is used.
At 0, the effect of the offset voltage Voff1 of the operational amplifier 2 constituting the integrator 14 on the output of the quantization circuit 4 is smaller than that of the conventional second-order ΔΣ modulator 80 shown in FIG.

In general, it is known that the output of the integrator 15 in the second-order △ Σ modulator 80 has a large amplitude, and in order to prevent the saturation of the output voltage Vo1 of the operational amplifier 3,
(C1 / CO) in equations (11) and (29) is usually
It is set to a value of 1 or less (for example, 1/4). Therefore, as can be seen by comparing Expression (11) and Expression (29), the dominant output voltage Vo1 of the integrator 15 is the offset voltage Voff2.

Equation (29) is considered with a one-input integrator.
The same applies to the case where the integrators 14 and 15 are two-input integrators as shown in FIG.
The effect of off2 is canceled, and the offset voltage Voff1 of the operational amplifier 2 is also changed to the conventional secondary ΔΔ shown in FIG.
The effect is smaller than in the case of the Σ-shaped modulator 80.

Therefore, according to the second-order ΔΣ modulator 80 of the present embodiment, higher modulation accuracy can be obtained as compared with the conventional second-order ΔΣ modulator 80 shown in FIG. As a result, as shown in FIG. 9, according to the oversampled A / D converter configured using the second-order ΔΣ modulator 80 of the present embodiment, high A / D conversion accuracy can be obtained. it can.

FIG. 8 is a simulation result comparing the second-order ΔΣ modulator 80 of the present embodiment with the conventional second-order ΔΣ modulator 80 shown in FIG. FIG. 8 (a)
2 shows a waveform of an analog signal input from the input terminal 1. FIG. 8B shows a second-order ΔΣ modulator 8 of the present embodiment.
2 shows a digital signal output from an output terminal 101 of 0.

FIG. 8C shows the conventional second order ΔΔ shown in FIG.
9 shows a digital signal output from the output terminal 101 of the Σ-shaped modulator 80. As shown in FIG. 8C, in the conventional modulator 80, the digital signal tends to be biased to “1” when the offset voltage is present even a little, and the digital signal changes to “1” when the offset voltage is increased. On the other hand, as shown in FIG. 8B, in the modulator 80 of the present embodiment, even when the offset voltage is large, no bias is observed in the digital signal, and the modulation accuracy does not decrease due to the offset voltage. Can be confirmed.

The present invention is not limited to the above embodiments. For example, even if the timings of the control signals f1 and f2 are reversed, the same operations and effects as those of the above embodiments can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a modulator according to a first embodiment.

FIG. 2 is a main part block diagram for explaining the operation of the modulator according to the first embodiment.

FIG. 3 is a circuit diagram illustrating a specific example of a unit gain amplifier used in the first and third embodiments.

FIG. 4 is a block diagram illustrating a modulator according to a second embodiment.

FIG. 5 is a block diagram illustrating a modulator according to a third embodiment.

FIG. 6 is a block diagram illustrating a modulator according to a fourth embodiment.

FIG. 7 is a block diagram illustrating a modulator according to a fifth embodiment.

FIG. 8 is a characteristic diagram for explaining the operation of the modulator according to the fifth embodiment.

FIG. 9 is a block diagram illustrating an oversampled A / D converter.

FIG. 10 is a block diagram illustrating various types of modulators.

FIG. 11 is a block diagram showing a conventional modulator.

FIG. 12 is a timing chart of a control signal for controlling the first to fifth embodiments and a conventional modulator.

FIG. 13 is a main part block diagram for explaining the operation of a conventional modulator.

FIG. 14 is a main block diagram for explaining the operation of a conventional modulator.

FIG. 15 is a block diagram showing a conventional modulator.

[Explanation of symbols]

2,3 ... Operational amplifier 4 ... Quantization circuit 5 ... Integration capacitance 7,8,9a, 9b ... Sampling capacitance 9 ... Sampling capacitance train 11,12 ... Switch group 13 ... Digital logic 14,15 ... Integrator 20-29, 40 ... Switch
41 ... Capacitance 42 ... Inverter 80 ... Modulator 81 ... Digital filter 131 ... Unit gain amplifier Vrefp, Vrefm ... Reference voltage source

Claims (8)

[Claims] 1. An integrator for integrating a difference voltage between an integrated input voltage and a first reference voltage, and a comparator, wherein an integrated output of the integrator is a second output.
A quantizing circuit that determines whether the reference voltage is larger or smaller than the reference voltage and quantizes the reference voltage, wherein the integrator is configured using an amplifier, and the first and second reference A modulator, wherein the voltage is made equal to the offset voltage of an amplifier constituting the integrator, thereby compensating for the influence of the offset voltage even if the amplifier has an offset voltage. 2. The method according to claim 1, wherein a difference voltage between the input analog signal and the feedback signal is defined as an integral input voltage.
An integrator for integrating a difference voltage between the reference voltage and a quantizing circuit that determines whether an integrated output of the integrator is larger or smaller than a second reference voltage and quantizes the integrated output; A first sampling capacitor that generates a feedback signal from an output; and a switch that switches and connects the first sampling capacitor to each of two types of voltage sources serving as references for generating a feedback signal. 1. A modulator comprising: a first switch group; and control logic for switching the first switch group at a preset timing, wherein the integrator includes an amplifier having an offset voltage, and holds a voltage obtained as a result of integration. And a second group of switches including a second sampling capacitor and a plurality of switches. A circuit that performs sampling at a period, transfers the obtained charge to the integration capacitor, inputs the first reference voltage to the amplifier during a sampling period, and generates an offset voltage for the first reference voltage in the amplifier. The first sampling capacitor is connected to the amplifier to sample a feedback signal in parallel with the second sampling capacitor, and the quantization circuit includes an output terminal and a capacitor of an amplifier constituting the integrator. And a switch that short-circuits the input / output terminal of the inverter during the sampling period of the integrator, and wherein the first and second reference voltages are: A modulator having a voltage equal to an offset voltage of an amplifier constituting the integrator. 3. The modulator according to claim 2, wherein said first sampling capacity comprises a capacity array having a plurality of weighted capacitors. 4. The modulator according to claim 2, wherein the amplifier constituting the integrator comprises a unity gain amplifier. 5. The modulator according to claim 2, wherein the amplifier forming the integrator comprises an operational amplifier. 6. The modulator according to claim 2, wherein the integrator sets a difference voltage between an input analog signal and a first feedback signal as a first integrated input voltage. A first integrator for integrating a difference voltage between the first integration input voltage and the first reference voltage, and a difference voltage between an integrated output of the first integrator and a second feedback signal are converted to a second feedback signal. A second integrator for integrating a difference voltage between the second integrated input voltage and a third reference voltage, wherein the quantization circuit integrates the second integrator. Output is second
A first sampling capacity for generating a first feedback signal from an output of the quantization circuit; and a second feedback signal from an output of the quantization circuit. A third sampling capacitor to be generated; a first switch group including switches that switch and connect the first sampling capacitor to each of two types of voltage sources serving as a reference for generating a feedback signal; A third switch group including switches that switch and connect the third sampling capacitor to each of the two types of voltage sources, and a first switch group and a third switch group that are set at predetermined timing. A modulator having switching logic, wherein the first integrator comprises: a first amplifier having an offset voltage; A first integration capacitance for holding a voltage of the first integration result, a second sampling capacitance and a second switch group composed of a plurality of switches, sample an input analog signal at a constant period, The obtained charge is transferred to the first integration capacitor, and the first reference voltage is input to the first amplifier during a sampling period, and an offset voltage corresponding thereto is generated in the first amplifier. The first sampling capacitor is connected to the first amplifier to sample a first feedback signal in parallel with the second sampling capacitor, and the second integrator comprises: A second amplifier having an offset voltage, a second integration capacitor for holding a voltage of a second integration result, a fourth sampling capacitor, and a plurality of switches The first integrated output is sampled at a constant period, and the obtained charge is sampled by the second switch group.
And a circuit for inputting the third reference voltage to the second amplifier during the sampling period and causing the second amplifier to generate an offset voltage for the third reference voltage during the sampling period. The third sampling capacitor is connected to the second amplifier in parallel with the fourth sampling capacitor to sample a second feedback signal, and the quantization circuit comprises a second integrator constituting the second integrator. An inverter connected to the output terminal of the second amplifier via a capacitor, and a switch that short-circuits the input / output terminal of the inverter during the sampling period of the second integrator. 2. The modulator according to claim 1, wherein the second and third reference voltages are equal to an offset voltage of a second amplifier constituting the second integrator. 7. The modulator according to claim 4, wherein said unity gain amplifier is constituted by a source follower circuit. 8. An oversampled A / D converter comprising: the modulator according to claim 1; and a filter that removes quantization noise from an output of the modulator.