JPH11204576A - Structure of semiconductor wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reproduce a semiconductor wafer, in which a defective is discovered in a rearrangement process by constituting a material for re-wiring which is brought into contact with an original bonding pad of a material having an etching rate higher than that of the material of the original bonding pad. SOLUTION: An aluminum pad 2 for original wire bonding is brought into contact with chromium 5 as a material for rearrangement wiring, and aluminum 6 is connected to the aluminum pad 2. When chromium 5 constituting a re-wiring patter 9 is etched by a chromium etchant, the etching rate of chromium at normal temperature is approximately 40 Å/sec, the etching rate of aluminum is approximately 20 Å/sec and there is approximately double the difference in the rate. Since the thickness of chromium is approximately 400 Å, approximately 10 sec is required for etching all the aluminum with a thickness of approximately 8,000 Å. Accordingly, chromium 5 for re-wiring can be etched with the aluminum pad 2 being left as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring material for a semiconductor chip, and more particularly to a rewiring material for rewiring a bonding pad for wire bonding to an area array pad for a flip chip.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high density of semiconductor packages, flip chip bonding has been developed in which bare chips are directly mounted face down on a substrate. With the advent of camera-integrated VTRs and mobile phones, portable devices equipped with a small package having substantially the same dimensions as a bare chip, that is, a so-called CSP (chip size / scale package) are appearing one after another. Recently, CSP development has progressed rapidly, and the market demand has been in full swing. However, since the flip chip bonding pitch is larger than the wire bonding pitch, the wire bonding IC cannot be used as it is for the flip chip. Therefore, first, the wire bonding pads around the semiconductor chip must be rewired inside the semiconductor chip to move to the flip chip pads so that they can be used for flip chip mounting.

FIG. 4 shows a conventional rewiring process. FIG.
In the semiconductor wafer manufacturing process shown in FIG. 1A, an active element is formed on a wafer (not shown), an aluminum pad 2 for wire bonding is formed around a semiconductor chip, and the active element surface is formed on a passivation film 3. Protect.

In the backside lapping step shown in FIG. 4B, the thickness of the semiconductor wafer is usually 635 μm in the semiconductor wafer manufacturing process, but when the package is subsequently packaged, the thickness of the wafer is reduced to 400 μm in order to make the package thinner. Need to be thin enough. Therefore, after attaching the element surface of the semiconductor wafer to the adhesive sheet, the back surface 1 of the semiconductor wafer is scraped, the adhesive sheet is peeled off, and the thickness of the semiconductor wafer is reduced.

In the interlayer polyimide forming step shown in FIG. 4C, an aluminum pad 2 is opened on a semiconductor wafer to protect pinholes in the passivation film 3 and to relieve stress on flip chip bumps. The film 4 is formed.

In the aluminum deposition step shown in FIG. 4D, aluminum 6 as a rewiring metal is deposited on a semiconductor wafer by sputtering or the like.

In the pattern forming step shown in FIG. 4E, wiring from the aluminum pad 2 for wire bonding to the new bonding pad 8 which is a flip chip pad is formed by a photolithographic method.

In the final polyimide film forming step shown in FIG. 4F, the semiconductor wafer surface is protected with the final polyimide film 7 while leaving a new bonding pad 8 serving as a flip chip pad.

[0009]

However, the above-mentioned rewiring material has the following problems. That is, the remaining adhesive material remaining on the surface of the semiconductor wafer in the backside lapping step causes cracks in the interlayer polyimide after the rewiring metal deposition step. Further, an increase in connection resistance between the rewiring metal and the aluminum pad for wire bonding due to the rewiring metal deposition step is found in a connection resistance test after the pattern forming step or the flip chip bump formation. Since these become defects of the entire semiconductor wafer, the amount of the defects becomes enormous, so that they need to be regenerated. This regeneration is performed by combining a relocation metal etching step, a polyimide etching step, a flip chip bump etching step, and the like. However, in the conventional structure, since the aluminum pad for wire bonding and the relocation metal in contact with the same are the same, when etching the relocation metal, only the relocation metal cannot be etched. When they are etched together and the re-distributed metal is deposited again, it cannot be electrically connected to the aluminum pad for wire bonding, so that a semiconductor wafer in which a defect is found in the middle of the process cannot be regenerated, resulting in a huge loss. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor wafer in which a bonding pad of a semiconductor chip needs to be rearranged. To provide a material for a semiconductor wiring that can be regenerated.

[0011]

In order to achieve the above object, a semiconductor wiring material according to the present invention is provided in a structure for rewiring an original bonding pad on a semiconductor chip to a new bonding pad position having a different position. The material of the rewiring in contact with the bonding pad is made of a material having a higher etching rate than the material of the original bonding pad.

[0012] Further, the etching rate of the rewiring material in contact with the original bonding pad is approximately twice as fast as the material of the original bonding pad.

Further, the material of the original bonding pad is aluminum.

Further, the material of the rewiring contacting the original bonding pad is chromium.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a semiconductor wiring material according to the present invention. FIG. 1 is an explanatory view showing a reproducing step in the case of using a material of a semiconductor wiring in the embodiment of the present invention. FIG. 2 is an explanatory view showing a manufacturing process of a semiconductor wiring using a semiconductor wiring material in the embodiment of the present invention. FIG. 3 is an explanatory view showing a sectional view of a semiconductor wiring according to the embodiment of the present invention. The same members as those in the prior art are denoted by the same reference numerals.

FIG. 2 shows a process for manufacturing a semiconductor wiring according to the present invention. The semiconductor wafer manufacturing process shown in FIG.
After an active element is formed on the wafer (not shown), an aluminum pad 2 for wire bonding is formed around the semiconductor chip, and the active element surface is protected by a passivation film 3.

In the backside lapping step shown in FIG. 2B, the semiconductor wafer backside 1 is scraped off after the element surface of the semiconductor wafer is adhered to the adhesive sheet, and the adhesive sheet is peeled off to reduce the thickness of the semiconductor wafer from 635 μm. 400μ
m.

In the step of forming an interlayer polyimide shown in FIG. 2C, a photosensitive polyimide is applied on a semiconductor wafer with a spinner to protect a pinhole of the passivation film 3 and to relieve a stress of a flip chip bump. 2 is opened, exposed, developed, and cured to form an interlayer polyimide film 4.

In the step of depositing chromium + aluminum shown in FIG. 2 (d), chromium 5 as a rewiring metal and aluminum 6 for lowering electrical resistance are deposited on the semiconductor wafer by sputtering, for example, at about 400 ° and 8000 °, respectively.

In the pattern forming step shown in FIG. 2E, a resist is applied to the wiring from the aluminum pad 2 for wire bonding to the new bonding pad 8 serving as a flip chip pad, exposed and developed, and then the aluminum 6 is removed. The rewiring pattern 9 is formed by etching with a mixed solution of phosphoric acid, nitric acid, and acetic acid, etching chromium 5 with a mixed solution of cerium ammonium nitrate / perchloric acid, and removing the resist.

In the final polyimide film forming step shown in FIG. 2 (f), a photosensitive polyimide is applied on the semiconductor wafer with a spinner, a new bonding pad 8 is opened, exposed, developed, and cured to form a final polyimide film. A polyimide film 7 is formed. Thereafter, flip chip bumps are formed on the new bonding pads 8 by a plating bump forming method (not shown).

FIG. 3 is a sectional view of the relocation wiring of the present invention. The original aluminum pad 2 for wire bonding is in contact with the chrome 5 of the material of the redistribution wiring of the present invention, and the aluminum 6 is connected thereon.

FIG. 1 shows an aluminum pad 2 for wire bonding after completion up to a flip chip bump.
4 shows a reproduction step of the present invention in the case where a problem such as electric resistance / adhesion force occurs between the wiring pattern and the rewiring pattern 9. The bump etching step shown in FIG.
Solder bump / UBM (UnderBumpMeta)
l) (not shown) is removed with the respective etchants.

In the polyimide etching step shown in FIG. 1B, the polyimide film excluding the interlayer polyimide film 4 under the rewiring pattern 9, specifically, the final polyimide film 7 and the interlayer polyimide film 4 are etched with a hydrazine etching solution. To remove.

In the aluminum etching step shown in FIG. 1C, the upper layer of aluminum 6 of the rewiring pattern 9 is etched with a mixed solution of phosphoric acid, nitric acid and acetic acid. At this time,
Since the chromium 5 thereunder is not etched, the wire bonding aluminum pad 2 remains protected.

In the chromium etching step shown in FIG. 1D, the chromium 5 constituting the rewiring pattern 9 is etched with a chromium etchant. For example, when a mixed solution of 10% cerium nitric ammonium nitrate / 5% perchloric acid is used as an etching solution, the etching rate of chromium at room temperature is about 40 ° / second, and the etching rate of aluminum is about 20 ° / second. And there is a difference of about twice the etching rate. Since the thickness of the chromium is about 400 °, the etching time is about 10 seconds. On the other hand, the aluminum thickness of the aluminum pad for wire bonding is about 8
000 °, it takes about 400 seconds to etch all of the aluminum underlying the chromium. Therefore, it is possible to etch the chromium 5 for rewiring while leaving the aluminum pad for wire bonding.

In the polyimide etching step shown in FIG. 1E, the remaining polyimide corresponding to the rewiring pattern 9 is etched with hydrazine. In these steps, the regenerating step is completed with the aluminum of the wire bonding aluminum pad 2 left so that the rearrangement wiring step can be started again.

[0028]

As described above, according to the relocation wiring material of the present invention, even in the case of a semiconductor wafer having a problem in the relocation wiring step, it is possible to maintain the original pad electrode in an almost initial state. It is possible to recover semiconductor wafers. This makes it possible to reuse a semiconductor wafer that has become defective in the rearrangement wiring step or the like, thereby preventing loss of the semiconductor wafer.

Further, since the etching rate of the original pad electrode material is different from the repositioning material in contact with the material by about twice or more, the control becomes easy.

Also, since the original pad electrode material is aluminum, it can be applied to all ordinary semiconductor chips.

Further, since the redistribution material in contact with the original pad electrode material is chromium, a difference in etching rate from aluminum can be easily obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a semiconductor wafer regenerating step after relocation wiring according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a rearrangement wiring step according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a cross-sectional view of the relocation wiring according to the embodiment of the present invention;

FIG. 4 is an explanatory view showing a conventional rearrangement wiring step.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wafer back surface 2 Aluminum pad 3 Passivation film 4 Interlayer polyimide film 5 Chromium 6 Aluminum 7 Final polyimide film 8 New bonding pad 9 Rewiring pattern

Claims (4)

[Claims] In a structure for rewiring an original bonding pad on a semiconductor chip to a new bonding pad position having a different position, a material of the rewiring contacting the original bonding pad has a higher etching rate than a material of the original bonding pad. The structure of a semiconductor wiring, wherein the structure is made of a material having a high speed. 2. The semiconductor wiring structure according to claim 1, wherein an etching rate of the rewiring material in contact with the original bonding pad is almost twice as fast as that of the material of the original bonding pad. 3. The semiconductor wiring structure according to claim 1, wherein the material of the original bonding pad is aluminum. 4. The semiconductor wiring structure according to claim 3, wherein the material of the rewiring contacting the original bonding pad is chromium.