JPH11163708A - Electronic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain speeding up of a signal outputted from a buffer circuit without being dominated by an input slow rising waveform, even when an IN1 signal that is outputted from a logic circuit and an IN2 signal that is an inverse signal of the IN1 signal have a voltage waveform the rising time of which is longer than trailing time. SOLUTION: A voltage level of an output signal of a NOR circuit 6 rises in a trailing timing of a voltage level of IN1 and IN2 signals outputted from a logic circuit 1. A flip-flop 7 provides an output of an inverse of a high level of low level signal in a rising timing of the output signal of the NOR circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electronic circuit having a logic circuit and a buffer circuit.

[0002]

2. Description of the Related Art FIG. 8 shows a block diagram of a logic circuit 1 using pass transistors and a buffer circuit 2 for amplifying an output of the logic circuit 1 and driving a next-stage load. As the logic circuit 1, "Technical white paper on low power LSI" (Nikkei BP
CPL (Complement)
ary Pass Transistor Logi
c) can be used. An example of this is shown in FIG. The logic circuit 1 includes N-channel MOS transistors (hereinafter referred to as NMOS transistors) 13a to 13d
When a normal rotation signal and its inverted signal are input to the input terminals 4a to 4f as appropriate, AND, OR, EXOR
, And its negative logic (hereinafter referred to as a normal signal and its inverted signal) are output from output terminals 4g and 4h.

In the above-described logic circuit 1, NMOS
Due to the characteristics of the transistor, the output waveforms of the normal signal and the inverted signal output from the output terminals 4g and 4h become longer as compared with the fall time as shown in FIG. The result shown in FIG.
As shown in FIG. 11, 16 NMOSs are used as the logic circuit 1.
Transistors are connected in cascade, and 16 NMOS
7 shows a simulation of an output waveform of a pulse-input voltage in a state where a transistor is turned on. (In the example of the logic circuit 1 shown in FIG. 9, one NMOS transistor is connected in series from the input terminal to the output terminal. However, if more complicated logic is to be obtained, the NMOS transistor is connected between the input terminal and the output terminal. The number of NMOS transistors connected in series is 1
There is a case where the number is more than 16 and the simulation result is shown on the assumption that the number is 16. )Also,
The buffer circuit 2 includes, as shown in FIG.
Generally, it is composed of a and 5b. in this case,
The inverters 5a and 5b output a signal obtained by inverting the input signal using the threshold voltage Vth shown in FIG. 10, for example, so that the signal output from the logic circuit 1 rises in FIG.
If it is late as shown by 0, the time when the signals output from the inverters 5a and 5b are determined is delayed by the signal whose rising time is slow. Therefore, the inverters 5a,
A time delay similarly occurs in the circuit operation at the next stage of 5b.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to increase the speed of a buffer circuit.

[0005]

According to the first aspect of the present invention, there are provided a first output terminal and a second output terminal for outputting a logical operation result and its negative logic, and a first output terminal. And a signal output from the second output terminal are both output from the first output terminal of the logic circuit (1) having a voltage waveform whose rise time is longer than the fall time and the first output terminal of the logic circuit (1). A signal of the first voltage level is output at the timing of the voltage waveform, and the second signal of the logic circuit (1) is output.
And a buffer circuit (2) for outputting a signal of a second voltage waveform different from the signal of the first voltage level at the falling timing of the voltage waveform output from the output terminal.

Therefore, even if the first signal and the second signal output from the logic circuit (1) are signals having a voltage waveform in which the rise time is longer than the fall time, the rise of the first signal and the second signal. By using the falling timing, the speed of the buffer circuit (2) can be increased without being influenced by the slow rising waveform of the input. Further, in the invention according to claims 2 to 4, the logic circuit (1) for outputting a signal having a voltage waveform whose rise time is longer than the fall time, and the voltage level of the signal output from the logic circuit (1) Becomes higher than the first threshold voltage.
A buffer circuit (2) that outputs a signal of a voltage level and outputs a signal of a second voltage level different from the first voltage level when a signal output from the logic circuit (1) becomes lower than a second threshold voltage; Wherein the first threshold voltage is set lower than the second threshold voltage.

Therefore, even if the output signal from the logic circuit (1) is a signal having a voltage waveform in which the rise time is longer than the fall time, the threshold voltage for the rise of the output signal is made lower than the threshold voltage for the fall. Thereby, the speed of the buffer circuit (2) can be increased without being influenced by the slow rising waveform of the input.

[0008]

(First Embodiment) FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a logic circuit 1 and a buffer circuit 2 using pass transistors according to the present invention. Numeral 1 denotes a logic circuit which is composed of NMOS transistors as shown in FIG.
When a forward signal and its inverted signal are appropriately input to f, the forward rotation of the voltage waveform whose rising time is longer than the falling time is obtained from the output terminals 4g and 4h as a result of a logical operation such as AND, OR and EXOR. Signal IN1 signal and inverted signal I
An N2 signal is output.

Reference numeral 2 denotes a buffer circuit having a NOR circuit 6 and a flip-flop 7, and configured to output a signal whose voltage level is inverted at the falling timing of the IN1 signal and the falling timing of the IN2 signal. . The flip-flop 7 uses a T-type flip-flop whose output is inverted at the rising timing of the signal input to the input terminal T.

The operation of the above configuration will be described with reference to a signal waveform diagram shown in FIG. As shown in FIGS. 2A and 2B, the IN1 signal and the IN2 signal output from the logic circuit 1 have voltage waveforms in which the rise time is longer than the fall time. Therefore, the IN1 signal and IN1
The output of the NOR circuit 6 to which the two signals are input is as shown in FIG.
As shown in the figure, the IN1 signal is the threshold voltage V of the NOR circuit 6.
from the time point when the signal becomes lower than th, the NOR circuit 6
From the time when the IN2 signal becomes lower than the threshold voltage Vth of the NOR circuit 6 to the time when the IN1 signal becomes higher than the threshold voltage Vth of the NOR circuit 6. Level signal.

The output signal of the NOR circuit 6 is input to the input terminal T of the flip-flop 7, and at the rising timing of the output signal of the NOR circuit 6, the output signals of the output terminals Q and QB of the flip-flop 7 are respectively shown in FIG. (D),
As shown in (e), the level changes to a high level and a low level. Therefore, the IN1 signal output from the logic circuit 1 and the IN2 signal which is the inverted signal thereof are different from those shown in FIG.
As shown in (b), even if the signal has a voltage waveform in which the rise time is longer than the fall time, the buffer circuit 2 switches from the high or low level signal at the fall timing of the voltage levels of the IN1 signal and the IN2 signal. Since the signals change to inverted signals, the speed of the signal output from the buffer circuit 2 can be increased without being influenced by the slow rising waveform of the input.

In the buffer circuit 2 described above, the logics of the input signals IN1 and IN2 and the signals output from the output terminals Q and QB of the flip-flop 7 must be equalized. For this reason, in the present embodiment, an initialization circuit 8 is provided. When the initialization circuit 8 detects that the power has been turned on,
A signal for setting the N1 signal to a low level and the IN2 signal to a high level is output to the input terminals 4a to 4f of the logic circuit 1, and a control terminal STB of a flip-flop 7 described later.
To output a high-level signal to the control terminal CRB and a low-level signal to the control terminal CRB. After this initialization, signals from a control circuit (not shown) are input to the input terminals 4a to 4f of the logic circuit 1.

Next, the configuration of the flip-flop 7 will be described. As shown in FIG. 3, the flip-flop 7 includes NAND gates 20 to 23 and switches S1 to S
4 and inverters 25-28. Each of the switch circuits S1 to S4 is a switch element including an N-channel MOS transistor and a P-channel MOS transistor.

First, at the time of initial setting when the power is turned on, a high level signal is output from the initial setting circuit 8 to the control terminal STB and a low level signal is output to the control terminal CRB.
The output signal of the gate 20 becomes high level, and the output signal of the inverter 27, that is, the output signal of the output terminal Q becomes low level. Since the output signal of the NAND gate 21 goes low, the output signal of the inverter 28, that is, the output signal of the output terminal QB goes high.

Therefore, according to the initial setting described above, in the buffer circuit 2, the input signals IN1 and IN1
The logic of the two signals and the signals output from the output terminals Q and QB of the flip-flop 7 can be made equal. After this initialization, signals from a control circuit (not shown) are input to the input terminals 4a to 4f of the logic circuit 1. Further, the initial setting circuit 8 switches the signal output to the control terminal CRB from a low level to a high level. By this switching, the flip-flop 7 alternately changes the level of the signal output from the output terminals Q and QB according to the rising change of the signal input to the input terminal T. Hereinafter, the operation of the flip-flop 7 after the initial setting will be described.

In the initial setting described above, since the IN1 signal is at a low level and the IN2 signal is at a high level, a low-level signal is input to the input terminal T of the flip-flop 7. At this time, since the output signal of the inverter 25 is at the high level and the output signal of the inverter 26 is at the low level, the switches S1 and S4 are turned on.
The switches S2 and S3 are off and the NAND gate 2
2 is at a high level.

Thereafter, when the input signal at the input terminal T goes high, the switches S1 and S4 are turned off, and the switches S1 and S4 are turned off.
2. S3 is turned on. Therefore, the output signal of the NAND gate 20 changes to a low level by the high level signal from the NAND gate 22, and the output signal of the inverter 27 (the output signal of the output terminal Q) changes to the high level. Further, the output signal of the NAND gate 21 changes to high level, and the output signal of the inverter 28 (output signal of the output terminal QB) changes to low level.

Next, when the input signal at the input terminal T goes low, the switches S1 and S4 are turned on, and the switches S2 and S2 are turned on.
S3 turns off. Therefore, the output of the NAND gate 22 changes to the low level in response to the high level signal from the NAND gate 21. Next, when the input signal of the input terminal T becomes high level, the switches S1 and S4 are turned off and the switches S2 and S3 are turned on. Therefore, the NAND gate 2
2, the output signal of the NAND gate 20 changes to a high level, and the output signal of the inverter 27 (the output signal of the output terminal Q) changes to a low level. Further, the output signal of the NAND gate 21 changes to low level, and the output signal of the inverter 28 (output signal of the output terminal QB) changes to high level.

Thereafter, the output signal of the inverter 27 (the output signal of the output terminal Q) remains at the low level until the input signal of the input terminal T changes to the low level and then changes to the high level. It operates so that the output signal (the output signal of the output terminal QB) becomes high level. Thereafter, the above operation is repeated, and the voltage level of the output signal from the output terminals Q and QB is changed alternately by the rising change of the input signal of the input terminal T. Note that N
The AND gate 23 and the like are provided for stabilizing the circuit operation. The above-described initial setting operation is only required if the logic between the input and output of the buffer circuit 2 matches, and is not limited to this.

In the buffer circuit 2 described above,
Although the configuration using the flip-flop 7 that inverts the output at the rising timing of the input signal has been described, it may be realized by using a flip-flop that inverts the output at the falling timing of the input signal. (Second Embodiment) FIG. 4 shows the configuration of a buffer circuit 2 according to the second embodiment. The buffer circuit 2 includes inverters 9a and 9b and an output circuit 10, and receives the IN1 signal from the logic circuit 1.

Here, the threshold voltage Vth of the inverter 9a is
L is set lower than the threshold voltage VthH of the inverter 9b. For example, when the inverters 9a and 9b are composed of a CMOS inverter including a PMOS transistor and an NMOS transistor as shown in FIG.
The threshold voltage of the inverter 9a and the threshold voltage VthH of the inverter 9b are reduced by increasing the channel width or shortening the channel length of the NMOS transistor as compared with the PMOS transistor to lower the threshold voltage of the inverter 9a. Can be set.

The output circuit 10 includes an inverter 9c, a NOR
It comprises a circuit 6 and a flip-flop 7. Note that the same flip-flop 7 as that shown in the first embodiment is used. The operation of the above configuration will be described with reference to a signal waveform diagram shown in FIG. The IN1 signal output from the logic circuit 1 has a voltage waveform in which the rise time is longer than the fall time, as shown in FIG.

The inverter 9a outputs a low level signal when the IN1 signal is higher than the threshold voltage VthL. Also, the inverter 9b outputs the IN1 signal to the threshold voltage VthH.
At this time, a low level signal is output. Here, since the threshold voltage VthL is set lower than the threshold voltage VthH, as shown in FIGS. 6B and 6C, the output signal of the inverter 9a falls earlier than the output signal of the inverter 9b and rises later. Will be.

Therefore, the output signal of the inverter 9b is inverted by the inverter 9c (see FIG. 6D) and the output signal of the inverter 9a is input to the NOR circuit 6, so that the output signal of the NOR circuit 6 becomes (E). Then, at the rising timing of the output signal of the NOR circuit 6, the flip-flop 7 outputs the signal shown in FIG.

As described above, the threshold voltage Vt of the inverter 9a is
By making hL lower than the threshold voltage VthH of the inverter 9b, the buffer circuit 2 outputs a high-level signal at the timing when the voltage level of the IN1 signal becomes higher than the threshold voltage VthL of the inverter 9a, and outputs the voltage level of the IN1 signal. Outputs a low-level signal at a timing when it becomes lower than the threshold voltage VthH of the inverter 9b.
Therefore, the signal output from the buffer circuit 2 is as shown in FIG.
Can be faster than the signal output from the buffer circuit 2 having the conventional configuration shown in FIG. (For reference, FIG. 6G shows an output waveform when the threshold voltage of the inverter circuits 5a and 5b constituting the buffer circuit 2 of the conventional configuration is VthH, and FIG. 6H shows an output waveform when the threshold voltage is VthL. Are shown in
FIG. 6F showing the output of the buffer circuit 2 of the second embodiment.
In FIG. 6, the output determination at the time of rising is faster than that of FIG. 6G, and the output determination at the time of rising is faster than that of FIG. In the buffer circuit 2 of the second embodiment shown in FIG. 4, when it is necessary to match the initial logic between the input and output, an initial setting circuit is provided as in the first embodiment, for example. Can be matched.

It should be noted that the voltage level of the IN1 signal output from the logic circuit 1 is equal to the threshold voltage VthL.
The inverter 9b operates as a first circuit that outputs a first signal whose voltage level decreases when the voltage becomes higher, and the inverter 9b sets the voltage level of the signal output from the logic circuit 1 to a threshold voltage V
The second is that the voltage level rises when the voltage becomes lower than thH.
It operates as a second circuit that outputs a signal. The output circuit 10 outputs a first voltage level (high-level signal) when the first signal is output from the inverter 9a, and outputs the second voltage when the second signal is output from the inverter 9b. It operates as a third circuit that outputs a voltage level (low level) signal.

In the above-described second embodiment, the NOR circuit 6 is used as a circuit for detecting the fall timing of the first signal and the second signal. However, the fall timing of the first signal and the second signal is detected. If it is a circuit, a circuit configuration other than the NOR circuit may be used. (Third Embodiment) In the above-described second embodiment, the buffer circuit 2 is realized by using two inverters 9a and 9b having different threshold voltages. 2 is provided with a switching circuit for switching the threshold voltage.

FIG. 7 shows the configuration of the buffer circuit 2 in this case. Reference numeral 11 denotes a comparator circuit. The comparator circuit 11 compares the IN1 signal input to the non-inverting input terminal with the threshold voltage input to the inverting input terminal. When the IN1 signal is higher than the threshold voltage, a high-level signal is output. And outputs a low-level signal when the IN1 signal is lower than the threshold voltage.

Reference numeral 12 denotes a switching circuit, which includes resistance elements R1 to R3,
The threshold voltage is increased when a high-level signal is output from the comparator circuit 11, and is increased when a low-level signal is output from the comparator circuit 11. The threshold voltage of the comparator circuit 11 is switched to lower the threshold voltage.

The resistance value of the on-resistance of the NMOS transistor 13 is set sufficiently lower than the resistance value of the resistance element R3. . As described above, since the threshold voltage of the comparator circuit 11 is switched by the switching circuit 12, the signal output from the buffer circuit 2 is the same as that of the second embodiment shown in FIG. Faster than the signal output from

[Brief description of the drawings]

FIG. 1 is a block diagram of an electronic circuit according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram in FIG.

FIG. 3 is a circuit diagram showing a configuration of a flip-flop 7 shown in FIG.

FIG. 4 shows a buffer circuit 2 used in a second embodiment of the present invention.
FIG.

FIG. 5 is a circuit diagram showing a configuration of inverters 9a and 9b in FIG.

6 is a signal waveform diagram in FIG. 4;

FIG. 7 shows a buffer circuit 2 used in a third embodiment of the present invention.
FIG.

FIG. 8 is a block diagram showing a logic circuit 1 and a buffer circuit 2 according to the related art.

9 is a circuit diagram showing a configuration of a logic circuit 1 in FIG.

10 is a voltage waveform diagram of an input / output signal showing a simulation result when a pulse is input to the logic circuit 1. FIG.

FIG. 11 is a circuit diagram showing a logic circuit 1 for simulation.

FIG. 12 is a circuit diagram showing a configuration of a buffer circuit 2 in FIG.

[Explanation of symbols]

1 ... Logic circuit, 2 ... Buffer circuit, 9a ... Inverter,
9b: inverter, 10: output circuit, 11: comparator.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takeshi Shioya 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Inside Denso Corporation (72) Inventor Hiroaki Tanaka 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Denso Corporation Inside

Claims (4)

[Claims] A first output terminal for outputting a logical operation result and a NOT logic thereof, and a second output terminal, wherein signals output from the first output terminal and the second output terminal are: A logic circuit (1) having a voltage waveform whose rise time is longer than the fall time; and a signal of a first voltage level being output at the timing of the voltage waveform output from the first output terminal of the logic circuit (1). A buffer circuit (2) for outputting a signal having a second voltage level different from the first voltage level at a falling timing of a voltage waveform output from the second output terminal of the logic circuit (1). An electronic circuit, comprising: 2. A logic circuit (1) for outputting a signal having a voltage waveform in which a rise time is longer than a fall time, and a voltage level of a signal output from the logic circuit (1) is higher than a first threshold voltage. And outputs a signal of a first voltage level, and outputs a signal of a second voltage level different from the first voltage level when a signal output from the logic circuit (1) becomes lower than a second threshold voltage. An electronic circuit, comprising: a buffer circuit (2) for setting the first threshold voltage to be lower than the second threshold voltage. 3. The buffer circuit (2) includes: a first circuit (9a) that outputs a first signal when a voltage level of a signal output from the logic circuit (1) becomes higher than the first threshold voltage. ), A second circuit (9b) that outputs a second signal when a voltage level of a signal output from the logic circuit (1) is lower than the second threshold voltage, and A third circuit that outputs the signal of the first voltage level when one signal is output, and outputs the signal of the second voltage level when the second signal is output from the second circuit; The electronic circuit according to claim 2, comprising: 4. The buffer circuit (2) compares a signal output from the logic circuit (1) with a threshold voltage, and when a signal output from the logic circuit (1) is higher than the threshold voltage. A comparison circuit (11) that outputs a signal of the first voltage level to the first circuit, and outputs a signal of the second voltage level when a signal output from the logic circuit (1) is lower than the threshold voltage; When the signal of the first voltage level is output from the circuit, the threshold voltage is switched to the second threshold voltage, and when the signal of the second voltage level is output from the comparison circuit, the threshold voltage is changed. The electronic circuit according to claim 2, further comprising a switching circuit (12) for switching to the first threshold voltage.