JPH11163366A - Manufacture of thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a thin-film transistor which can provide a uniform LDD region at low cost as a thin-film transistor which uses polycrystalline silicon for a semiconductor layer. SOLUTION: An invented manufacture of the thin-film transistor includes a process for forming a semiconductor layer on an insulating substrate 1, a process for laminating an insulating film 5 and a conductive layer 6 on the semiconductor layer, a process for forming a gate electrode by patterning the conductive layer, and a process for forming an offset area 9 by forming mask 7A, by reducing the width of a mask used for the formation of the gate electrode through a desired quantity and injecting impurity ions of high density into a part, where there is neither the mask nor the conductive layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor in an active matrix type liquid crystal display device using the thin film transistor.

[0002]

2. Description of the Related Art In recent years, display devices using liquid crystals have become widespread. Therefore, further miniaturization and lower power consumption of the liquid crystal display device are required. Accordingly, a method of integrally forming a thin film transistor as a switching element used as a driving element on a glass substrate of a liquid crystal panel has been put to practical use. Note that a method based on polycrystalline silicon is used as a method for forming a semiconductor region of a thin film transistor.

As a method of forming a thin film transistor, as disclosed in Japanese Patent Application Laid-Open No. 3-148834, first, a channel isolation region (11) is formed on a P-type Si substrate (10). Separation area (1
A gate electrode (13) is formed in a region defined by 1) via a gate oxide film (12) (FIG. 1a). The gate electrode (13) is formed by forming a Poly-Si film on a Si substrate (10), forming a resist film (14) having a predetermined pattern, and forming the resist film (14) in the same manner as in the prior art. It is obtained by etching and removing the Poly-Si film as a mask. At this time, the gate insulating film (13)
Is formed to be longer than the final length by a predetermined amount, that is, by an amount corresponding to the sidewall (6) shown in FIG.

Next, without removing the resist film (14) on the gate insulating film (13), regions other than the source and drain regions, for example, the channel isolation region (1)
1) and a resist film (15) covering the region of the P-channel type MOS transistor and the like are formed.
4) Using (15) as a mask, an N-type impurity such as arsenic (A
s ⁺ ) is implanted at a high concentration to form an N ⁺ type diffusion region (16S).
(16D) is formed (FIG. 1b). This diffusion region (1
6S) and (16D) become source and drain regions, respectively.

Subsequently, the resist films (14) and (15) are isotropically removed by a predetermined amount by a plasma treatment containing oxygen (FIG. 1c). In this plasma treatment, the resist film (14) is removed by an amount corresponding to the gate electrode (13) being formed in a size larger than necessary. That is, a part of the resist film (14) is removed so that the size of the resist film (14) remaining after the plasma processing becomes the final size of the gate electrode (13 '). Then, the gate electrode (13) is etched using the resist film (14 ') having a predetermined size as a mask to remove both ends of the gate electrode (13), and then the resist films (14') and (15 ') are masked. As an N-type impurity such as P ⁺ ,
Injected at a lower concentration than during the formation of S) (16D), N ^-
There is a method of forming the diffusion regions (17S) and (17D) of the mold.

[0006]

However, in the method of manufacturing a thin film transistor described in JP-A-3-148834, an LDD (Lightly Doped Drain) is used.
Is defined by photolithography, the LDDs formed on both sides of the gate due to the deflection of the glass substrate holding Si and the misalignment when aligning the mask
There is a problem that the width of the substrate becomes different between the left and right, or the width becomes different for each substrate. This causes a problem that the yield and reliability of the product cannot be improved because the on-state current of the thin film transistor is not uniform. Therefore, there is a problem that the cost as the liquid crystal display device is increased.

An object of the present invention is to provide a method of manufacturing a thin film transistor which can provide an LDD (Lightly Doped Drain) region having a uniform width at a low cost in a thin film transistor using polycrystalline silicon as a semiconductor layer. .

[0008]

SUMMARY OF THE INVENTION The present invention has been made based on the above problems, and comprises a step of forming an insulating film and a conductive film on a semiconductor layer, and a step of forming a resist on a first pattern on the conductive film. Forming a mask, patterning the conductive film into a first pattern, and forming a second pattern resist mask by removing an outer peripheral portion of the first pattern resist mask; A first implantation step of implanting impurities into the semiconductor layer using the conductive film of the first pattern as a mask, a step of patterning the conductive film into a second pattern using the second pattern as a mask, Removing the resist mask of the second pattern; and removing the resist mask of the second pattern, and then removing the resist mask of the second pattern by using the conductive film of the second pattern as a mask. A thin film transistor manufacturing method comprising the second implantation step of implanting second impurity.

In the method of manufacturing a thin film transistor according to the present invention, the step of removing the resist mask having the first pattern is an isotropic etching.

Further, in the method of manufacturing a thin film transistor according to the present invention, the concentration of the impurity implanted in the first implantation step is higher than the concentration of the impurity implanted in the second implantation step.

Still further, in the thin film transistor according to the present invention, the semiconductor layer contains polycrystalline silicon. Still further, the invention provides a step of forming an insulating film and a conductive film on a semiconductor layer having a first semiconductor region and a second semiconductor region, and a step of forming a first pattern having a first pattern on the semiconductor region. Forming a resist mask so as to cover one semiconductor region; patterning the conductive film into a first pattern; and forming a P-type using the conductive film patterned into the first pattern as a mask. A first implantation step of implanting impurities into the second semiconductor region, a step of removing the resist mask of the first pattern, and a second semiconductor having a second pattern covering the first semiconductor region Forming a resist mask for masking a region, patterning the conductor film into the second pattern, and forming an outer peripheral portion of the resist mask having the second pattern. A step of making a resist mask of a third pattern by to, the N to the first semiconductor region the conductor film of the second pattern as a mask
A second implantation step of implanting an impurity of a mold, a step of patterning the conductor film into a third pattern,
Removing the third resist mask from the semiconductor region, and implanting an N-type impurity into the first semiconductor region using the conductive film of the third pattern as a mask.
And a method of manufacturing a thin film transistor.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a thin film transistor used in a liquid crystal display device will be described in detail with reference to FIGS. In the process shown in FIG. 1, for example, PE (plasma enhanced)
-A passivation film 2 having a predetermined thickness is formed by a CVD method, a sputtering method, or the like, and an amorphous silicon (a-Si) layer 3 is subsequently deposited to a predetermined thickness. Preferably, silicon nitride (SiO _x ) is selected as the material of the passivation film 2 from the viewpoint of ion blocking for Na and the like. Further, the thickness of the amorphous silicon layer 3 is set to 50 to 100 nm.

Next, in order to reduce the amount of hydrogen contained in the amorphous silicon layer 3, for example, an annealing furnace is used.
Heat (thermal annealing) at about 500 ° C. for 1 hour. Subsequently, the amorphous silicon layer 3 is irradiated with an energy beam (laser light) typified by an excimer laser such as XeCl or the like to be heated and melted once, and then cooled (heat radiation). Thereby, the melted amorphous silicon layer 3 is crystallized to form a polycrystalline silicon layer (4).

Next, as shown in FIG. 2, a resist mask (not shown) having a predetermined pattern is formed on the polysilicon layer 4, and the polysilicon layer is patterned by etching. At this time, for example, a fluorine-based gas typified by CF ₄ or the like is used to perform dry etching by downflow so that the processed end is tapered, for example. Next, the resist mask (not shown) used for the etching is removed by plasma ashing using O ₂ or an organic alkali solution.

Subsequently, as shown in FIG.
The first insulating film 5 is formed by a method or an AP-CVD method by using, for example, TEOS (tetraethoxysilane) as a source gas. Note that the film thickness is 50 to 150 nm. Next, a molybdenum-tungsten alloy (hereinafter abbreviated as MoW) layer 6 having a thickness of about 250 nm is formed as a first conductive layer on the first insulating film 5 by sputtering or the like. Note that MoW has a columnar crystal structure and can be easily processed in the vertical direction, and is useful for application to products that require pattern accuracy. Also, because it is a high melting point metal,
Less susceptible to subsequent thermal processes.

Next, as shown in FIG. 4, the first conductive layer 6
A resist mask (photomask) 7 is formed thereon and patterned into a predetermined shape.
The MoW layer 6 in a region corresponding to a portion of the polysilicon layer 4 where a p-type transistor is to be formed is etched.

Subsequently, a group III compound such as B ₂ H ₆ is
Using a non-mass separation type ion implanter, the MoW layer 6 is etched into the polysilicon layer 4 in a region corresponding to a portion below the portion removed by etching, for example, at an accelerating voltage of 50 keV, at 4 ×.
A dose of 10 ¹⁵ atoms / cm ² is implanted to form p ⁺ polysilicon region 8. After the implantation of a group III compound such as B ₂ H ₆ , the mask 7 is removed.

Next, as shown in FIG. 5, an organic mask 7A is formed by photolithography on the MoW (first conductive layer) 6 in a portion of the polysilicon layer 4 where an N-type transistor is to be formed, and etching is performed. I do. The mask 7A
Is M for the p-type transistor formed in the process of FIG.
It is also used to protect the oW 6 and the p ⁺ polysilicon region 8 from a subsequent etching step.

By the way, when the MoW (first conductive layer) 6 in the portion for forming the N-type transistor is etched,
Since MoW6 is used as a gate line, high processing accuracy is required for the shape of MoW6. For this reason, etching is performed by dry etching using plasma containing, for example, fluorine, chlorine and oxygen gas. In addition, by using a fluorine-based or chlorine-based gas as the gas material,
A high etching selectivity with respect to the underlying TEOS film (first insulating film) 5 is obtained. This is because the volatility of SiCl ₄ which is a reaction product between the chlorine gas contained in the gas and the silicon oxide film which is the main component of the TEOS film is low. Further, by adjusting the amount of oxygen contained in the gas, the etching rate of the MoW layer 6 can be reduced.
The etching rate can be increased. In experiments, it has been confirmed that adding O _{2 in an} amount of 30% with respect to the amounts of fluorine and chlorine is most effective.

When the MoW layer 6 is processed, T
Since the EOS film 5 may also be etched, it is necessary to use an etching apparatus capable of controlling the amount of fluorine ions and chlorine ions to control the gas so that the TEOS film 5 is not etched (by etching). desirable.
Note that when the TEOS film 5 is lost by etching, the underlying polysilicon layer 4 is also etched. In addition, as an etching apparatus, a power supply for generating plasma and a power supply for irradiating a material to be etched with fluorine ions or chlorine ions in plasma are used independently, thereby ensuring a high etching rate. In addition, it is possible to ensure high selectivity to the underlying TEOS film 5.

After the MoW layer 6 is etched, the organic mask (resist) used for the etching is etched in the same direction by plasma etching used for plasma etching mainly using O ₂ gas. In this case, a small amount of fluorine or chlorine may be added to the O ₂ gas.
Since the layer 6 and the TEOS layer 5 are also shaved, it is desirable not to add them more than necessary.

As described above, by etching the mask 7A isotropically, the offset region 9 is formed at the end of the processed MoW layer 6 and the end of the mask 7A. The width of the offset region 9 finally becomes LDD (Li
ghtly Doped Drain) The width of the area.

The LDD width is, for example, 0.2 to 1.0 μm.
m is desirable, and the offset region 9 is formed by optimizing the thickness of the mask 7A and the inclination angle of the end of the mask 7A.
It is set so that an appropriate LDD width can be provided. The mask 7A is etched (ashed) on the first conductive layer 6 by isotropic etching from the two directions orthogonal to the surface direction of the glass substrate 1 by substantially equal distances.

Next, in the step shown in FIG. 6, using a first conductive film 6 provided with an offset 9 as a mask, a group V compound such as PH ₃ is ion-implanted using a non-mass separation type ion implantation apparatus. Then, 1 × 10 ¹⁵ at an acceleration voltage of 65 keV is applied to a portion of the polysilicon layer 4 where the MoW layer 6 does not exist.
An n ⁺ polysilicon region 10 is formed by implanting a dose of atom / cm ² .

Subsequently, as shown in FIG. 7, the mask is etched isotropically in the step shown in FIG.
The oW layer 6 is etched again. The etching condition at this time is dry etching using the above-described fluorine, oxygen, and chlorine gas. Hereinafter, after the etching is completed, the mask 7A is removed. Since the mask 7A contains phosphorus, it is preferable to remove the mask 7A by ashing with an O ₂ gas or the like after reducing with a hydrogen-based gas.

Next, a group V compound such as PH ₃ is
Using a non-mass separation type ion implanter, MoW
1 × 10 ¹³ atom / c at an accelerating voltage of 80 keV in the polysilicon layer 4 under the portion where the layer 6 is etched.
Implantation is performed at a dose of m ² to form n ⁻ polysilicon region 11. That is, the n ^- polysilicon (LDD)
The width of 11 is limited by the width of the offset area 9.
The width of the offset region 9 may be misaligned by optimizing the thickness of the mask 7A or the inclination angle of the end of the mask 7A as compared with a method using another (new) mask. In addition, since the width is substantially equal by the isotropic etching, the element in which the LDD width changes for each substrate is extremely low, and an LDD having a uniform width can be provided.

Next, in the step shown in FIG.
As a second insulating film, for example, a silicon oxide 12 having a film thickness of 50 is formed by a VD method, an AP-CVD method, a sputtering method, or the like.
A film is formed to a thickness of 0 nm. Subsequently, dry etching using a CHF ₃ gas, a CF ₄ + H 2 mixed gas, or a CF ₄ + CO mixed gas is applied to the first insulating film 5 and the second insulating film 12 on the n ⁺ polysilicon layer 10 by photolithography. Thereby, a contact hole 12a is opened. In the processing of the contact hole, a conductive material having excellent acid resistance is used, and when the pattern accuracy is relatively low, wet etching with dilute HF may be used.

As shown in FIG. 9, after removing the mask used to form the contact hole 12a, the second conductive layer serving as the signal line 13 is made of, for example, Al or Al--N.
d, metal such as Al-Si-Cu and Mo + Al + Mo
Is deposited by sputtering or the like, and then patterned into a predetermined shape by photolithography.

Subsequently, in a step shown in FIG. 10, a silicon nitride film 14 is formed as a protective film on the entire surface, and a contact hole 15a is formed in a region located above the signal line of the N-type thin film transistor. Then, a transparent conductive film serving as the contact hole 15a and the pixel electrode 15 is formed and patterned to provide a thin film transistor for an active matrix type liquid crystal display device.

[0030]

The thin film transistor thus formed can reduce the leakage current when the gate voltage is 0 V by about two to three digits as compared with the conventional thin film transistor.
This alleviates the concentration of the electric field at the drain end, reduces charge injection into the gate oxide film, and improves the reliability of the thin film transistor.

Further, by using one mask in two steps, the number of masks can be reduced and the throughput can be improved. Further, the mask used for forming the LDD does not require alignment, and is further subjected to isotropic etching.
Since the width is controlled, it is possible to prevent the width of the LDD from changing for each substrate.

[Brief description of the drawings]

FIG. 1 is a schematic view showing a first step for describing a manufacturing process of a thin film transistor of the present invention in the order of steps.

FIG. 2 is a schematic view for explaining a step following the step of manufacturing the thin film transistor shown in FIG.

FIG. 3 is a schematic diagram for explaining a step that follows the manufacturing step of the thin film transistor shown in FIG. 2;

FIG. 4 is a schematic view for explaining a step further following the step of manufacturing the thin film transistor shown in FIG. 3;

FIG. 5 is a schematic view for explaining a step further following the step of manufacturing the thin film transistor shown in FIG. 4;

FIG. 6 is a schematic view for explaining a step further following the step of manufacturing the thin film transistor shown in FIG. 5;

FIG. 7 is a schematic view for explaining a step further following the manufacturing step of the thin film transistor shown in FIG. 6;

FIG. 8 is a schematic view for explaining a step further following the step of manufacturing the thin film transistor shown in FIG. 7;

FIG. 9 is a schematic view for explaining a step that follows the manufacturing step of the thin film transistor shown in FIG. 8;

FIG. 10 is a schematic diagram for explaining a step further subsequent to the step of manufacturing the thin film transistor shown in FIG. 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Glass substrate (insulating substrate), 3 ... Amorphous silicon layer, 4 ... Polycrystalline (poly) silicon layer, 5 ... First insulating film, 6 ... First conductive layer , 7 ... resist mask, 7A ... resist mask, 8 ... p ⁺ polysilicon region, 9 ... offset region, 10 ... n ⁺ polysilicon region, 11 ... n ^- polysilicon Region 12 ... second insulating film, 13 ... second conductive layer.

Claims (13)

[Claims] A step of forming an insulating film and a conductive film on the semiconductor layer; a step of forming a resist mask on a first pattern on the conductive film; and a step of patterning the conductive film into a first pattern. Forming a resist mask of a second pattern by removing an outer peripheral portion of the resist mask of the first pattern; and implanting impurities into the semiconductor layer using the conductive film of the first pattern as a mask. A first implanting step, a step of patterning the conductive film into a second pattern using the second pattern as a mask, a step of removing the resist mask of the second pattern, and a step of removing the resist mask of the second pattern. After removing the resist mask,
A second implantation step of implanting a second impurity into the semiconductor layer using the conductive film of the second pattern as a mask. 2. The method according to claim 1, wherein the step of forming the second pattern resist mask includes an isotropic etching step. 3. The method according to claim 2, wherein the isotropic etching uses an etching gas containing oxygen gas as a main component in a plasma atmosphere. 4. The method according to claim 3, wherein the etching gas contains at least one of a fluorine gas and a chlorine gas. 5. The first impurity and the second impurity have substantially the same conductivity type, and the concentration of the first impurity is
2. The method according to claim 1, wherein the concentration of the second impurity is higher than the concentration of the second impurity. 6. The method according to claim 1, wherein the first implantation step is performed after removing an outer peripheral portion of the resist mask of the first pattern. 7. The method according to claim 1, wherein the conductive film is a refractory metal having a columnar crystal structure. 8. The method according to claim 1, wherein said semiconductor layer is formed on an insulating substrate. 9. The method according to claim 1, wherein said semiconductor layer is made of polycrystalline silicon. 10. A step of forming an insulating film and a conductive film on a semiconductor layer having a first semiconductor region and a second semiconductor region; and forming the first pattern having a first pattern on the semiconductor region. A step of forming a resist mask so as to cover a semiconductor region; a step of patterning the conductor film into a first pattern; and a step of removing P-type impurities using the conductor film patterned in the first pattern as a mask. A first implantation step of implanting into the second semiconductor region; a step of removing the resist mask of the first pattern; and a step of removing a second semiconductor region having a second pattern covering the first semiconductor region. Forming a resist mask to be masked; patterning the conductive film into the second pattern; removing an outer peripheral portion of the resist mask having the second pattern Forming a resist mask of a third pattern by using the conductive film of the second pattern as a mask, a second implantation step of implanting an N-type impurity into the first semiconductor region, Patterning a film into a third pattern; removing the third resist mask from the first semiconductor region; and using the conductor film of the third pattern as a mask to form the first semiconductor region. And a third implantation step of implanting an N-type impurity into the thin film transistor. 11. The method according to claim 10, wherein the concentration of the impurity implanted in the third implantation step is higher than the concentration of the impurity implanted in the second implantation step. . 12. The method according to claim 11, wherein said semiconductor layer is formed on an insulating substrate. 13. The method according to claim 10, wherein said semiconductor layer is made of polycrystalline silicon.