JPH11162181A - Non-volatile semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the dispersion in the writing characteristics of the electric charge of a floating gate by controlling the writing current between a bit line being adjacent to a drain region and the ground. SOLUTION: A writing current control circuit 15 is provided at a bit line BL being connected to the ground, where the circuit 15 controls a writing current for each of first and second flash memory transistors. Each writing characteristic of the first and second flash memory cell transistors is measured, and the writing current is set by the control circuit 15 so that those with longer writing time are equivalent to those with shorter writing time. For setting the writing current of the flash memory cell transistor with the longer writing time, a specific electric charge is written to a multilevel flash memory transistor 19 or 20 of the current control circuit 15 in advance. Then, a selection transistor 17 or 18 is turned on reading, thus setting the writing current to a specific setting value and making equal the writing time of both flash memories.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly, to a floating gate and a control gate formed so as to extend from an upper portion to a side portion of the floating gate so as to be adjacent to the floating gate and the control gate. A so-called split gate type flash memory cell transistor having a source / drain region on the substrate surface layer and writing data by accumulating hot electrons generated between the source / drain region in the floating gate. A nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art An electrically erasable nonvolatile semiconductor memory device in which a memory cell comprises a single transistor, in particular, a programmable ROM (EEPROM: Electronically Erasable an).
d Programmable ROM, also called flash memory. 3), each flash memory cell transistor is formed by a transistor having a double gate structure having a floating gate and a control gate. In the case of such a double-gate flash memory cell transistor, data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. Then, data is erased by extracting charges (electrons) from the floating gate to the control gate by FN conduction (Fowler-Nordheim tunnelling).

FIG. 3 is a plan view of a flash memory cell transistor having a floating gate, and FIG.
It is sectional drawing of the XX line. This figure shows a split gate structure in which the control gate 6 is arranged so as to extend from the upper part to the side part of the floating gate 4 via an insulating film. A plurality of isolation regions 2 made of a selectively thick oxide film (LOCOS) are formed in a strip shape in a surface region of a P-type silicon substrate 1 to partition an element region. A floating gate 4 is arranged on a silicon substrate 1 with an oxide film 3 interposed between adjacent isolation regions 2. This floating gate 4
Each flash memory cell transistor is independently arranged. Further, the selective oxide film 5 on the floating gate 4 is formed thick at the center of the floating gate 4 by a selective oxidation method, and the end of the floating gate 4 is formed at an acute angle. This makes it easier for electric field concentration to occur at the end of the floating gate 4 during data erasing operation.

On the silicon substrate 1 on which a plurality of floating gates 4 are arranged, control gates 6 are arranged corresponding to each column of the floating gates 4. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3. The floating gate 4 and the control gate 6 are arranged such that adjacent rows are plane-symmetric with each other.

An N-type drain region 7 and a source region 8 are formed in the substrate region on the control gate 6 side and the substrate region on the floating gate 4 side. The drain region 7 is surrounded by the isolation region 2 between the control gates 6 and is independent, and the source region 8 is continuous in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, drain region 7 and source region 8 constitute a flash memory cell transistor composed of a floating gate transistor and a control gate transistor.

Then, on the control gate 6,
Aluminum wiring 10 is arranged via oxide film 9 in a direction crossing control gate 6. This aluminum wiring 10 is connected to drain region 7 through contact hole 11. Then, as shown in FIG. 5, each control gate 6 becomes a word line WL, and a source region 8 extending in parallel with the control gate 6 becomes a source line SL. The aluminum wiring 10 connected to the drain region 7 becomes the bit line BL, and the bit line B
L is connected to ground via a sense amplifier (not shown) and a MOS transistor 13 used when reading data. The MOS transistor 13 serves to set the write current of each flash memory cell transistor to a certain value.
It is set to 50 nA.

In the case of such a double gate flash memory cell transistor, the floating gate 4
The on-resistance value between the source and the drain fluctuates depending on the amount of charge injected into the device. Therefore, floating gate 4
The on-resistance value of a specific flash memory cell transistor is varied by selectively injecting electric charges into the memory cells, and a difference in operating characteristics of each flash memory cell transistor caused by the change is associated with data to be stored.

The above-described data write, erase, and read operations in the flash memory cell transistor are performed, for example, as follows. First, in a write operation, the potential of the selected control gate 6 is set to 2 V, and the potential of the drain region 7 is set to a write current (Icel).
l) is 150 nA, and the potential of the source region 8 is 9 V
And As a result, hot electrons generated near the drain region 7 are accelerated toward the floating gate 4 and injected into the floating gate 4 through the oxide film 3 to write data.

On the other hand, in the erasing operation, the potentials of the drain region 7 and the source region 8 are set to 0 V, and the control gate 6 is set to 14 V. As a result, electric charges (electrons) accumulated in the floating gate 6 penetrate through the tunnel oxide film from the acute corner of the floating gate 4 by FN conduction, and pass through the control gate 6.
And the data is erased.

In a read operation, the potential of the control gate 6 is set to 4 V and the drain region 7 is set to 2 V.
V and the source region 8 is set to 0V. At this time, if charges (electrons) are injected into the floating gate 4, the potential of the floating gate 4 becomes low, so that no channel is formed below the floating gate 4 and no drain current flows. Conversely, if charges (electrons) are not injected into the floating gate 4, the potential of the floating gate 4 increases, so that a channel is formed below the floating gate 4 and a drain current flows. Therefore, by detecting the current flowing from the drain region 7 by the sense amplifier, it is possible to determine whether the flash memory cell transistor is on or off, that is, determine the written data.

[0011]

In the above-mentioned flash memory cell transistor, the control gate 6 formed so as to extend from the upper portion to the side portion of the floating gate 4 has a conductive film formed so as to cover the floating gate 4. Then, the conductive film is formed by patterning using a dedicated mask, that is, since the floating gate 4 and the control gate 6 are not formed in a self-aligned manner, they are used as a mask in the process of processing the floating gate 4. On the other hand, when the mask in the process of processing the control gate 6 is misaligned, the gate length of the control gate transistor (see L1 and L2 in FIG. 6) between the adjacent flash memory cell transistors with the source region 8 interposed therebetween is reduced. Change, emit hot electrons when writing Electric field may change to, also,
When the degree of overlap between the floating gate 4 and the control gate 6 changes, the capacitance ratio between the capacitance between the floating gate 4 and the control gate 6 and the capacitance between the floating gate 4 and the source region 8 changes.

As a result, the write characteristics of each flash memory cell transistor become asymmetric. 7 and 8 are characteristic diagrams showing the write characteristics of the respective flash memory cell transistors. In the above-described write operation, the potential of the selected control gate 6 is set to 2 V, and the potential of the drain region 7 is set to the write current. (Icell) is set to 150 nA, and the potential of the source region 8 is set to various values (8 V, 9 V, 10 V, 11 V).
A write time (Program Time) is shown until hot electrons generated near the drain region 7 are accelerated toward the floating gate 4 and a predetermined amount of charge (electrons) is written to the floating gate 4 through the oxide film 3. . For example, as described above, when writing is performed by setting the potential of the source region 8 to 9 V, the first flash memory cell transistor (hereinafter, the flash memory cell transistor to which the word line WL1 shown in FIG. Readout current (Cell Curren)
t) The writing time when Ir becomes 0.1 μA is about 18
At μsec (point A indicated by a two-dot chain line in FIG. 7), the read current of the second flash memory cell transistor (hereinafter, this refers to the flash memory cell transistor to which the word line WL2 shown in FIG. 6 is connected). Ir is 0.1
The writing time of μA takes about 30 μsec (point B indicated by a two-dot chain line in FIG. 8).

That is, in order for both the flash memory cell transistors to have a read current Ir of 0.1 μA, the flash memory cell transistor having a lower write characteristic (here, the second flash memory cell transistor) must be used. Since a corresponding writing time (for example, about 30 μsec) was required, there was a demand to improve the variation in the writing characteristics of both flash memory cell transistors.

Accordingly, the present invention provides a flash memory cell transistor adjacent to a source region, which is caused by misalignment of a mask in a process of processing a control gate with respect to a mask in a process of processing a floating gate. It is an object of the present invention to provide a nonvolatile semiconductor memory device having improved write characteristics by suppressing variations in the write time when writing charges (electrons) to each floating gate.

[0015]

According to the nonvolatile semiconductor memory device of the present invention, a bit line BL connected to a drain region 7 is provided.
A write current control circuit 15 including a plurality of multi-level flash memory cell transistors 19 and 20 for controlling the write current of each flash memory cell transistor is inserted between the write current control circuit 15 and the ground.

Each of the select transistors 17 and 1 corresponding to each flash memory cell transistor is connected to a bit line BL connected to the drain region 7 through a node 16.
8 is connected to each of the drains D1 and D2, and between the respective sources S1 and S2 of the selection transistors 17 and 18 and the ground, a multi-level flash memory cell transistor capable of setting a desired write current for each flash memory cell transistor A write current control circuit 15 comprising 19 and 20 is inserted.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. The planar and cross-sectional structures of the nonvolatile semiconductor memory device of the present invention are the same as the structures shown in FIGS. The features of the present invention are:
As shown in FIG. 1, the flash memory cell transistors adjacent to each other with the source region 8 interposed therebetween (the first flash memory cell transistor connected to the word line WL1, the second flash memory cell transistor connected to the word line WL2) ), A multi-level flash memory cell transistor for controlling the write current of each flash memory cell transistor to a desired set value for each of the first and second flash memory cell transistors on a bit line BL connected to the ground 19,
20 in that a write current control circuit 15 comprising 20 is provided.

In the write current control circuit 15, the drains D1 and D2 of the select transistors 17 and 18 corresponding to the memory cell transistors are connected to the bit line BL via the node 16, and the source S1 of the select transistor 17 is connected to the bit line BL. A multi-level flash memory cell transistor 19 composed of a non-volatile semiconductor memory device is connected between the ground and a ground, and a multi-level flash memory cell transistor 20 also composed of a non-volatile semiconductor memory device is connected between the source S2 of the select transistor 18 and the ground. ing. In this embodiment, the multi-level flash memory cell transistors corresponding to the first and second flash memory cell transistors via the selection transistors 17 and 18 are “00”, “01”, “10”, and A four-valued multi-level flash memory cell transistor to which data of "11" can be written, wherein each data "00", "01",
A write current of 150 nA, 3 to the first and second flash memory cell transistors for each of "10" and "11".
It is assumed that 00 nA, 600 nA and 900 nA are generated. ) Is provided.

A method for controlling the write current of the nonvolatile semiconductor memory device of the present invention using the write current control circuit 15 having the above-described configuration will be described. First, TEG
The write characteristics of the above-described first and second flash memory cell transistors are measured by the flash memory cell transistor of FIG. 1 or the flash memory cell transistor in the LSI, and the bit line BL and the ground are corresponded to the measured write characteristics. By writing desired data “00”, “01”, “10” and “11” into the desired multi-valued flash memory cell transistors 19 and 20 inserted between them, the first flash memory cell transistor or The write current of the second flash memory cell transistor is adjusted.

That is, after measuring the write characteristics of the first flash memory cell transistor and the second flash memory cell transistor, the flash memory cell transistor (eg, the second
Of the flash memory cell transistor (for example, the first flash memory cell transistor) having the shorter write time (for example, about 30 μsec if the mask misalignment amount is the same as that of the conventional flash memory cell transistor). Write time (approximately 18 μs if the mask misalignment amount is the same as the conventional one)
ec) so as to be substantially equivalent to the second one as shown in FIG.
Current I of the flash memory cell transistor
By changing the cell from 150 nA (the write current used for acquiring the write time measurement data described above) to 600 nA, the write time of the second flash memory cell transistor is about 30 μsec (B shown by a dotted line in FIG. 2).
(Point A) to 18 μsec (point A shown by a dashed line in FIG. 2).

Therefore, in order to enable the write current of the second flash memory cell transistor to be set to 600 nA in advance, the multi-level flash memory cell transistor 20 is charged (electrons) so that desired data "10" is obtained.
Is written, the selection transistor 18 for selecting the second flash memory cell transistor is turned on at the time of reading of the second flash memory cell transistor, so that the multi-value flash memory cell transistor 20 becomes conductive. , The write current of the second flash memory cell transistor is set to 600 nA. Thereby, as shown in FIG. 2 described above, the write time of the second flash memory cell transistor becomes almost equal to the write time of the first flash memory cell transistor, and the write characteristics can be improved.

In the above description, the present invention has been described on the assumption that the write characteristics of the second flash memory cell transistor are inferior to the write characteristics of the first flash memory cell transistor. The same applies to the case where the writing characteristics of the second flash memory cell transistor are inferior.
By writing desired data to the multi-level flash memory cell transistor 19 on the first flash memory cell transistor side based on the write characteristic data measured in advance, the first flash memory cell transistor can be used to read the first flash memory cell transistor. By turning on the selection transistor 17 for selecting a memory cell transistor, the multi-level flash memory cell transistor is turned on, and the write current of the first flash memory cell transistor is set to a desired write current. As a result, the write time of the first flash memory cell transistor becomes substantially equal to the write time of the second flash memory cell transistor, and the write characteristics can be improved.

[0023]

According to the nonvolatile semiconductor memory device of the present invention, since each flash memory cell transistor is provided with a write current control circuit composed of a corresponding multi-level flash memory cell transistor via each select transistor, floating Charges (electrons) are applied to each floating gate of the flash memory cell transistors adjacent to each other across the source region, which was caused by the misalignment of the mask in the process of processing the control gate with the mask in the process of processing the gate. In this case, it is possible to improve the write characteristics by suppressing the variation in the write time when writing data.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram for explaining an example of improvement in write characteristics of the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a plan view for explaining a conventional nonvolatile semiconductor memory device.

FIG. 4 is a sectional view taken along line XX of FIG. 3;

FIG. 5 is a circuit diagram for explaining a conventional nonvolatile semiconductor memory device.

FIG. 6 is a circuit diagram for explaining a problem of a conventional nonvolatile semiconductor memory device.

FIG. 7 is a characteristic diagram for explaining write characteristics of a first memory cell transistor;

FIG. 8 is a characteristic diagram for describing write characteristics of a second memory cell transistor.

Claims (2)

[Claims] A memory cell array in which a plurality of flash memory cell transistors each including a floating gate, a control gate, first and second impurity diffusion regions and a channel are arranged, and the floating gate is charged by hot electrons. A nonvolatile semiconductor memory device for writing data comprising a multilevel flash memory cell transistor capable of setting a desired write current for each flash memory cell transistor between a bit line connected to the first impurity diffusion region and ground. A nonvolatile semiconductor memory device having a write current control circuit inserted therein. 2. A memory cell array in which a plurality of flash memory cell transistors each including a floating gate, a control gate, first and second impurity diffusion regions, and a channel are arranged, and the floating gate is charged by hot electrons. In the nonvolatile semiconductor memory device for writing, the drain of each select transistor corresponding to each flash memory cell transistor is connected to a bit line connected to the first impurity diffusion region via a node. A write current control circuit comprising a multi-level flash memory cell transistor capable of setting a desired write current for each flash memory cell transistor between each source and the ground.