JPH11121468A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent short-circuiting between electrodes, while avoiding reduction of a manufacturing yield and blockage of microminiaturization. SOLUTION: On a semi-insulating GaAs substrate 1, there is formed a gate electrode 8. The electrode 8 is formed to have a comb shape which has a plurality of gate electrode parts 8a and a gate base part 8c connected to one ends of the gate electrode parts 8a. Bent portions 8b of the gate electrode parts 8a positioned at both sides of source electrode parts 5a are bent as not interconnected each other but intersected toward the source electrode parts 5a. In a semi-insulating GaAs substrate 1 below the bent portions 8b, a depletion layer is formed to prevent a short current from passing through between the source electrode parts 5a and a drain lead electrode part 6b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a Schottky junction type semiconductor device.

[0002]

2. Description of the Related Art FIG. 12 is a plan view of a conventional semiconductor device. In FIG. 12, GaAs is used as an example of a conventional semiconductor device.
The structure of a MESFET (metal-semiconductor field effect transistor) using an s substrate is shown.

A plurality of ion implantation operation regions (not shown) are formed on the semi-insulating GaAs substrate 1, and a high-concentration ion implantation region (not shown) is formed between the ion implantation operation regions.

The gate electrode 18 includes a plurality of gate electrode portions (finger portions) 18a extending over each ion implantation operation region of the semi-insulating GaAs substrate 1, and a plurality of gate electrodes 18a.
And a gate base 18b for connecting one end of the gate.
The source electrode 5 connects a plurality of source electrode portions (finger portions) 5a formed on every other high-concentration ion-implanted region of the semi-insulating GaAs substrate 1 with one end of the plurality of source electrode portions 5a. And a source extraction electrode portion 5b. Further, the drain electrode 6 is made of semi-insulating Ga.
A plurality of drain electrode portions (finger portions) 6 formed on the remaining alternate high-concentration ion-implanted regions of the As substrate 1.
a and a drain extraction electrode portion 6b connecting one end of the plurality of drain electrode portions 6a. Gate base 18b of gate electrode 18 and source lead electrode 5
b is arranged on one side in the gate width direction, and the drain extraction electrode portion 6b is arranged on the other side in the gate width direction.

[0005] The MESFET as described above is used, for example, in a high-frequency amplifier. In operation, the drain electrode 6
, A voltage of +10 to +30 V is applied, and the source electrode 5 is grounded. The gate electrode 18 has a voltage of -4V to + 1V.
Is applied. Then, the high-frequency signal given to the gate electrode 18 is amplified and output from the drain electrode 6.

[0006]

In recent years, as the miniaturization and high integration of semiconductor integrated circuits have progressed, the ME shown in FIG.
In the SFET, the distance between the source electrode portion 5a and the drain extraction electrode portion 6b is approaching. In addition, the above M
The ESFET is required to have a high output, and therefore, the operating voltage applied between the source electrode 5 and the drain electrode 6 is high. For this purpose, for example, when a high voltage, for example, 30 V is applied between the source electrode 5 and the drain electrode 6, as shown by an arrow A in FIG.
a and the drain extraction electrode portion 6b is short-circuited,
In some cases, sparks were generated or the MESFET was destroyed.

In the manufacturing process of the MESFET of FIG. 12, after an ion implantation operation region and a high-concentration ion implantation region are formed on the semi-insulating GaAs substrate 1, a high temperature is used to electrically activate these ion implantation regions. Is performed. At this time, the surface of the semi-insulating GaAs substrate 1 is As
A phenomenon occurs in which the (arsenic) concentration decreases and the resistance near the surface decreases. Therefore, when a high voltage is applied between the source electrode portion 5a and the drain extraction electrode portion 6b which are arranged close to each other, a short-circuit current easily flows near the surface of the semi-insulating GaAs substrate 1. As a result, the above-described discharge and destruction of the MESFET occur.

Therefore, a semiconductor device having a structure capable of preventing a short circuit between the source electrode portion 5a and the drain extraction electrode portion 6b has been proposed. FIG. 13 is a plan view of a semiconductor device according to the present proposal. The semiconductor device of FIG.
The MESFET is the same as the MESFET 2. In this MESFET, the gate electrode 28 has a gate electrode portion 28a and a gate base portion 28b, and the tips of a pair of gate electrode portions 28a adjacent to each other across the source electrode portion 5a are connected by a gate connection portion 28c. . Thereby, the gate electrode portion 28a is extended between the source electrode portion 5a and the drain extraction electrode portion 6b to prevent short circuit.

FIG. 14 is a schematic cross-sectional view for explaining the short-circuit prevention structure of the MESFET of FIG. In FIG.
Arrow B indicates the path of the short-circuit current when the gate connection 28c does not exist, and arrow C indicates the path of the short-circuit current when the gate connection 28c is arranged. Source electrode part 5
a between the gate electrode 2a and the drain extraction electrode portion 6b.
When the gate connection portion 28c of FIG.
A depletion layer 11 is formed in the semi-insulating GaAs substrate 1 in a contact region between the semiconductor substrate 8c and the semi-insulating GaAs substrate 1. Depletion layer 1
1 prevents passage of short circuit current. As a result, the path of the short-circuit current extends from arrow B to arrow C, avoiding the depletion layer 11. In the path indicated by the arrow C, the resistance is increased as compared with the path indicated by the arrow B, and the short-circuit current is less likely to flow. As a result, the withstand voltage between the source electrode portion 5a and the drain extraction electrode portion 6b is improved, and a short circuit is prevented.

In the MESFET shown in FIG. 13, the gate base 28b of the gate electrode 28, the gate electrode 28a and the gate connection 2 are formed around the source electrode 5a.
A pattern in which 8c is closed annularly is formed. When forming such a gate electrode 28, first, semi-insulating GaAs
A resist pattern having an opening for forming a gate electrode is formed on the surface of the substrate 1, and subsequently, a gate electrode material made of a metal is deposited on the surface of the resist pattern and inside the opening for forming a gate electrode. . Then, the gate electrode material on the photoresist is removed together with the photoresist using the lift-off method, and the gate electrode material formed in the opening for forming the gate electrode is left. Thereby, the gate electrode 28 is formed.

However, when the gate electrode material is vapor-deposited on the resist pattern, the gate electrode material in the annular opening of the photoresist and the gate electrode material formed on the photoresist inside the annular opening become inconsistent with the opening. It is easy to be formed by being connected annularly along the inner wall. For this reason, at the time of lift-off, the gate electrode material on the photoresist inside the annular opening and the gate electrode material inside the annular opening are less likely to be separated. Therefore, unnecessary gate electrode material and photoresist remain around the gate electrode 28 formed inside the opening, and there is a possibility that the manufacturing yield of the MESFET may be reduced.

An object of the present invention is to provide a semiconductor device in which a short circuit between electrodes is prevented without lowering the production yield and without hindering miniaturization.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device including a gate electrode having a plurality of gate electrode portions extending in a comb-like shape from a gate base. The tip of each pair of the adjacent gate electrode portions is bent inward.

In the semiconductor device according to the first invention,
The tips of each pair of adjacent gate electrode portions are bent inward. For this reason, the periphery of the electrode portion arranged inside each pair of gate electrode portions can be surrounded by the gate electrode. The bent portion at the tip of the gate electrode portion allows the semiconductor substrate directly under the pair of gate electrodes between the electrode portion disposed inside the pair of gate electrode portions and the electrode portion disposed close to the pair of gate electrode portions. Can form a depletion layer. The depletion layer hinders the flow of short-circuit current. Therefore, by forming the depletion layer, the path in the case where a short-circuit current flows between the electrode portion disposed inside the gate electrode portion and the electrode portion disposed adjacent thereto is lengthened, and the resistance is increased. This makes it difficult for the short-circuit current to flow, thereby improving the dielectric strength between the two electrodes arranged close to each other.

Further, since the tips of the pair of gate electrode portions are separated from each other, unnecessary gate electrode material formed inside the pattern of each pair of gate electrode portions during the manufacture of the gate electrode portions is reduced. It is easy to separate from the gate electrode material for the electrode part. As a result, unnecessary gate electrode material is prevented from remaining, and the manufacturing yield of the semiconductor device can be improved.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the bent portions of each pair of gate electrode portions are shifted from each other in the gate width direction.

In this case, the bent portion of the gate electrode portion displaced in the gate width direction is provided in the semiconductor substrate between the electrode portion disposed inside each pair of gate electrode portions and the electrode portion disposed adjacent thereto. A depletion layer can be formed by the portion. For this reason, the path in the case where a short-circuit current flows between the electrode portion disposed inside the pair of gate electrode portions and the electrode portion disposed in the vicinity of the pair of gate electrode portions is meandered and lengthened, and the resistance is increased by increasing the resistance. The withstand voltage between the electrode portions can be improved.

A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the second aspect of the present invention, wherein the bent portion of one of the pair of gate electrode portions and the folded portion of the other gate electrode portion of the pair of gate electrode portions are provided. The curved portions are arranged so as to be spaced apart from each other in the gate width direction and have overlapping portions along the gate length direction.

In this case, a short-circuit current is formed by a bent portion of the pair of gate electrode portions between an electrode portion disposed inside the pair of gate electrode portions and an electrode portion disposed close to the electrode portion. The depletion layer prevents flow in a straight line, and is forced to flow meandering through a gap between a bent portion of one gate electrode portion and a bent portion of the other gate electrode. For this reason, the path in the case where the short-circuit current flows becomes long, and the resistance increases, so that the short-circuit current hardly flows. Thus, the withstand voltage between the electrode portion disposed inside the pair of gate electrode portions and the electrode portion adjacent thereto can be improved.

According to a fourth aspect of the present invention, there is provided a semiconductor device including a gate having an operation layer formed on a semiconductor substrate and a plurality of gate electrode portions formed on the operation layer and extending in a comb-like shape from a gate base. An electrode, a plurality of first ohmic electrodes formed on every other region among the regions between the plurality of gate electrode portions, and a second ohmic electrode on the remaining every other region among the regions between the plurality of gate electrode portions. A plurality of second ohmic electrodes, a first lead electrode arranged on the same side as the gate base and connecting one end of the plurality of first ohmic electrodes;
A second extraction electrode that is disposed on the opposite side to the gate base and connects one end of the plurality of second ohmic electrodes; and a pair of gate electrode portions disposed on both sides of each first ohmic electrode. The tip is bent toward the first ohmic electrode.

In a semiconductor device according to a fourth aspect,
The tip of each pair of gate electrode portions is bent toward the first ohmic electrode. Therefore, the periphery of the first ohmic electrode can be surrounded by the gate electrode. Then, a depletion layer can be formed in the semiconductor substrate immediately below the gate electrode between the first ohmic electrode and the second lead electrode by the bent portion at the tip of the gate electrode.
The depletion layer hinders the flow of short-circuit current. Therefore, by forming the depletion layer, the path in the case where a short-circuit current flows between the first ohmic electrode and the second lead electrode can be lengthened, and the resistance can be increased. Thereby, the first
Short-circuit current hardly flows between the ohmic electrode and the second extraction electrode, and the withstand voltage can be improved.

Further, since the bent front ends of each pair of gate electrode portions are separated from each other, unnecessary gate electrode material formed inside the pattern of the gate electrode portion at the time of manufacturing the gate electrode portion is formed. Is easily separated from the gate electrode material for the gate electrode portion. As a result, unnecessary gate electrode material is prevented from remaining, and the manufacturing yield of the semiconductor device can be improved.

According to a fifth aspect of the present invention, in the configuration of the semiconductor device according to the fourth aspect of the present invention, the bent portion at the tip of each of the pair of gate electrode portions is connected to the first ohmic electrode portion and the second lead-out portion. The electrode extends in a region facing the electrode.

In this case, since the tip of each pair of gate electrode portions extends in the region where the first ohmic electrode and the second lead electrode face each other, the extended portion of the gate electrode portion is used. A depletion layer can be formed in the semiconductor substrate between the first ohmic electrode and the second lead electrode. The depletion layer makes it possible to lengthen a path in the case where a short-circuit current flows between the first ohmic electrode and the second extraction electrode, increase the resistance, and make it difficult for the short-circuit current to flow. Thereby, the withstand voltage between the first ohmic electrode and the second lead electrode can be improved.

A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the fourth or fifth aspect, wherein the bent portions of each pair of gate electrode portions are shifted from each other in the gate width direction. .

In this case, a depletion layer can be formed in the semiconductor substrate between the first ohmic electrode and the second extraction electrode by a bent portion of the gate electrode portion shifted in the gate width direction. Therefore, the first ohmic electrode and the second ohmic electrode
The path when a short-circuit current flows between the first ohmic electrode and the second lead electrode is increased by increasing the resistance when a short-circuit current flows between the first ohmic electrode and the second lead electrode by increasing the resistance. can do.

A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to the sixth aspect, wherein the bent portion of one of the pair of gate electrode portions and the folded portion of the other gate electrode portion of each of the pair of gate electrode portions are provided. The curved portions are arranged so as to be spaced apart from each other in the gate width direction and have overlapping portions along the gate length direction.

In this case, a short-circuit current between the first ohmic electrode and the second extraction electrode is prevented from flowing linearly by the depletion layer formed by the bent portions of the pair of gate electrode portions. However, it is forced to flow meandering through the gap between the bent portion of one gate electrode portion and the bent portion of the other gate electrode. For this reason, the path in the case where the short-circuit current flows becomes long, and the resistance increases, so that the short-circuit current hardly flows. Thereby, the withstand voltage between the first ohmic electrode and the second lead electrode can be improved.

[0029]

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line XX in FIG. In this embodiment, a MESFET will be described as an example of the semiconductor device of the present invention. In FIG. 1,
2 shows a structure of the MESFET from above the substrate surface.

1 and 2, in the MESFET, a plurality of ion implantation operation regions 3 formed on a semi-insulating GaAs substrate 1 and a high concentration ion implantation region 4 formed between the ion implantation operation regions 3 are formed. I have. On the semi-insulating GaAs substrate 1, a gate electrode 8, a source electrode 5, and a drain electrode 6 are formed.

The gate electrode 8 is provided in each ion implantation operation region 3.
A plurality of gate electrode portions (finger portions) 8a formed on the surface of the semiconductor device, a bent portion 8b in which one end of the gate electrode portion 8a is bent, and the other end of each gate electrode portion 8a are connected. The gate base 8c is formed in a comb shape.

The source electrode 5 includes a source electrode section 5a and a source lead electrode section 5b. Source electrode part 5
a is formed on the surface of one high-concentration ion implantation region 4. Each source electrode portion 5a is a source lead electrode portion 5
b.

A polyimide film 9 is formed on the gate base 8c and the gate electrode 8a. The polyimide film 9 is provided to ensure insulation between the source lead-out electrode portion 5b and the gate base portion 8c.

The drain electrode 6 includes a drain electrode portion (finger portion) 6a and a drain extraction electrode portion 6b. The drain electrode part 6a is a semi-insulating GaAs substrate 1.
It is formed on the surface of the high-concentration ion implantation region 4 formed therein. Each drain electrode section 6a is connected by a drain extraction electrode section 6b.

Further, the gate base 8c of the gate electrode 8 is arranged on one side in the gate width direction. Source electrode 5
Is located on the same side of the gate electrode 8 as the gate base 8c, and the drain lead electrode 6b of the drain electrode 6 is located on the side opposite to the gate base 8c and the source lead electrode 5b.

FIG. 3 is an enlarged plan view of an essential part of the MESFET of FIG. 1, and FIG. 4 is a plan view showing a path of a short-circuit current.
In FIG. 3, the source electrode 5a and the drain extraction electrode portion 6b are arranged close to each other with an interval of about 10 μm. The bent portion 8b of the gate electrode 8 extends to a region near the source electrode portion 5a and the drain extraction electrode portion 6b, and has a bent portion 8b of one gate electrode 8 and a bent portion 8b of the other gate electrode 8. And are arranged to intersect. Therefore, when viewed along the direction in which the source electrode portion 5a and the drain extraction electrode portion 6b face each other in the adjacent region, the bent portion 8b of at least one gate electrode 8 exists.

A depletion layer is formed on the semi-insulating GaAs substrate 1 below the bent portion 8b of the gate electrode 8. This depletion layer becomes semi-insulating GaAs when a negative voltage is applied to the gate electrode.
It spreads in the substrate 1 and contracts when a positive voltage is applied. As shown in FIG. 4, the path of the virtual short-circuit current between the source electrode portion 5a and the drain extraction electrode portion 6b is, as shown by the arrow D, the tip of the bent portion 8b of one gate electrode and the other. Overlapping portion E with the tip of bent portion 8b of the gate electrode
Is formed meandering between the layers avoiding the depletion layer. As a result,
The path of the short-circuit current becomes longer, the resistance increases, and the short-circuit current hardly flows. Thereby, the withstand voltage between the source electrode portion 5a and the drain extraction electrode portion 6b is improved.
Therefore, the source electrode portion 5a and the drain extraction electrode portion 6b can be arranged close to each other, and the element structure of the MESFET can be miniaturized.

In this embodiment, the bent portion 8b of the gate electrode 8 corresponds to the bent portion of the gate electrode portion of the present invention, the source electrode portion 5a corresponds to the first ohmic electrode, and the drain electrode portion 6a Corresponds to the second ohmic electrode, the source lead electrode portion 5b corresponds to the first lead electrode,
The drain extraction electrode portion 6b corresponds to a second extraction electrode.

Next, the above semiconductor device (MESFET)
Will be described. 5 to 11 show M in FIG.
It is process drawing which shows the manufacturing method of ESFET, (a) is sectional drawing, (b) has shown the top view.

First, in FIG. 5, a SiN film 2 is formed on a semi-insulating GaAs substrate 1 to a thickness of 0.03 μm. Further, a mask pattern (not shown) of a photoresist is formed on the SiN film 2 and Si ions are implanted at an energy of 1
The ion implantation is performed under the conditions of 50 keV and a dose of 3 × 10 ¹² cm ⁻² to form the ion implantation operation region 3. After that, the photoresist is removed.

Next, in FIG. 6, a mask pattern of a photoresist is formed in a predetermined region on the SiN film 2,
Ion implantation energy 180 keV, dose 5 × 1
The high-concentration ion-implanted region 4 is formed by implantation under the condition of 0 ¹³ cm ^-2 , and then the photoresist is removed. Further, in order to electrically activate the ion implantation operation region 3 and the high-concentration ion implantation region 4, a short-time annealing process at 850 ° C. for 5 seconds is performed.

Further, in FIGS. 7A and 7B, S
On the iN film 2, a photoresist pattern having an opening on the high-concentration ion-implanted region 4 is formed. Using the photoresist pattern, an opening is formed in the SiN film 2 on the high-concentration ion implantation region 4 by a reactive ion etching (RIE) method using CF ₄ gas (carbon tetrafluoride gas). Then, after depositing an AuGe / Ni / Au film on the entire surface, the photoresist and the AuGe / Ni / Au film deposited on the photoresist are removed by a lift-off method. As a result, S on the high-concentration ion implantation region 4
AuGe / Ni / Au remains in the opening of the iN film 2.
Thereafter, a heat treatment is performed for 2 minutes at a temperature of 400 ° C.
A source electrode portion 5a and a drain electrode portion 6a made of an ohmic electrode of e / Ni / Au are formed.

Further, in FIGS. 8A and 8B, a photoresist is formed on the entire surface and is patterned to form a photoresist pattern 7 from which the photoresist of the gate electrode forming portion 7a has been removed. Then, using the photoresist pattern 7 as a mask, the SiN film 2 in the gate electrode formation portion 7a is removed by plasma etching using a mixed gas of CF ₄ and O ₂ (oxygen).

9 (a) and 9 (b), a Ti / Pt / Au film is deposited on the entire surface. Thus, Ti / Pt / Au films 80a and 80b are formed on the surface of photoresist 7 and inside the opening of gate electrode formation portion 7a.

Further, in FIGS. 10 (a) and 10 (b),
The photoresist 7 and the Ti / Pt / Au film 80a on the photoresist 7 are removed by a lift-off method. The gate electrode forming part 7a surrounds the periphery of the source electrode part 5a, and is formed in a shape where the separated distal ends intersect. Therefore, Ti / Pt / Au on the photoresist 7
Ti / Pt / Au in the film 80a and the gate electrode forming portion 7a
Even when the film 80b is formed continuously along the inner wall of the opening of the gate electrode forming portion 7a, when the photoresist 7 is removed at the time of lift-off, the Ti on the photoresist 7 is removed.
/ Pt / Au film 80a and Ti / Pt / Au film 8 in the opening
The portion continuous with 0b starts to be separated from the vicinity of the front end portion F of the gate electrode forming portion 7a, and the separation proceeds as the photoresist 7 is removed. As a result, the Ti / Pt / Au film 80a in the opening of the electrode forming portion 7a is completely removed, and no residue of the deposited film or the photoresist is generated.

Further, in FIGS. 11A and 11B,
A polyimide film 9 is formed to a thickness of 2 μm on the surface of the gate electrode 8a and on the surface of the gate base 8c.

Further, a photoresist is formed on the entire surface,
By patterning, a mask pattern for forming the source lead-out electrode portion 5b and the drain lead-out electrode portion 6b is formed. Further, using the mask pattern, a source lead electrode portion 5b and a drain lead electrode portion 6b are formed by gold plating. Through the above steps, the MESFET shown in FIGS. 1 and 2 is manufactured.

As described above, the gate electrode 8 is formed so as to surround the source electrode portion 5a, and the bent portions 8b are formed so as to cross each other. For this reason, in the gate electrode forming step shown in FIG. 9, manufacturing defects due to generation of residues of the photoresist and the metal deposition film are prevented, and the MES is prevented.
The manufacturing yield of the FET can be improved.

The shape of the bent portion 8b of the gate electrode 8 in the present invention is not limited to the linear shape as shown in the first and second embodiments, but may be a source electrode portion 5a.
Any other shape, such as an arc shape, may be used as long as it can lengthen the path of the short-circuit current in the region adjacent to the drain extraction electrode portion 6b.

In the case of a MESFET in which the source lead-out electrode portion 5b of the source electrode 5 and the drain lead-out electrode portion 6b of the drain electrode 6 in FIG. The bent portion 8b may be bent toward the drain electrode portion 6a.
Thus, the bent portion 8b of the gate electrode 8 extends in the region adjacent to the drain electrode portion 6a and the source extraction electrode portion 5b, and it is possible to prevent a short circuit from occurring in this region.

The present invention relates to the MESFE of the above embodiment.
Not only T but also various semiconductor devices having a gate electrode, for example, HEMT (high electron mobility transistor) and TMT
(Two-Mode Channel FET) or the like.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line XX in FIG.

FIG. 3 is an enlarged plan view of a main part of the semiconductor device of FIG. 1;

FIG. 4 is a plan view showing a path of a short-circuit current.

FIG. 5 is a process chart showing a method for manufacturing the semiconductor device of FIG. 1;

FIG. 6 is a process chart illustrating a method for manufacturing the semiconductor device of FIG. 1;

FIG. 7 is a process chart showing a method for manufacturing the semiconductor device of FIG. 1;

FIG. 8 is a process chart showing a method for manufacturing the semiconductor device of FIG. 1;

FIG. 9 is a process chart showing a method for manufacturing the semiconductor device of FIG. 1;

FIG. 10 is a process chart showing a method for manufacturing the semiconductor device of FIG. 1;

FIG. 11 is a process chart showing a method for manufacturing the semiconductor device of FIG. 1;

FIG. 12 is a plan view of a conventional semiconductor device.

FIG. 13 is a plan view of another semiconductor device.

14 is a schematic cross-sectional view for explaining a short-circuit prevention structure of the semiconductor device of FIG.

[Explanation of symbols]

 Reference Signs List 1 semi-insulating GaAs substrate 3 ion implantation operation region 4 high-concentration ion implantation region 5 source electrode 5a source electrode portion 5b source lead electrode portion 6 drain electrode 6a drain electrode portion 6b drain lead electrode portion 8 gate electrode 8a gate electrode portion 8b folding Curved part 8c Gate base

Claims (7)

[Claims] In a semiconductor device having a gate electrode having a plurality of gate electrode portions extending in a comb-like shape from a gate base portion, tips of a pair of adjacent gate electrode portions are bent inward. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the bent portions of the pair of gate electrode portions are shifted from each other in a gate width direction. 3. A bent portion of one of the pair of gate electrode portions and a bent portion of the other gate electrode portion are separated from each other in a gate width direction and along a gate length direction. 3. The semiconductor device according to claim 2, wherein the semiconductor device is arranged so as to have an overlapping portion. 4. A gate electrode having an operation layer formed on a semiconductor substrate, a plurality of gate electrode portions formed on the operation layer and extending in a comb-like shape from a gate base, and the plurality of gates A plurality of first ohmic electrodes formed on every other region of the region between the electrode portions; and a plurality of first ohmic electrodes formed on the remaining every other region of the region between the plurality of gate electrode portions. A second ohmic electrode, a first extraction electrode arranged on the same side as the gate base, and connecting one end of the plurality of first ohmic electrodes; and a second extraction electrode arranged on the opposite side to the gate base, A second extraction electrode for connecting one end of each of the plurality of second ohmic electrodes, and a tip of each pair of gate electrode portions disposed on both sides of each first ohmic electrode is connected to the first ohmic electrode. That it was folded Characteristic semiconductor device. 5. The semiconductor device according to claim 1, wherein a bent portion at the tip of each of said pair of gate electrode portions extends in a region where said first ohmic electrode portion and said second extraction electrode face each other. Item 5. The semiconductor device according to item 4. 6. The semiconductor device according to claim 4, wherein the bent portions of the pair of gate electrode portions are shifted from each other in a gate width direction. 7. A bent portion of one of the pair of gate electrode portions and a bent portion of the other gate electrode are separated from each other in a gate width direction and along a gate length direction. 7. The semiconductor device according to claim 6, wherein the semiconductor device is arranged to have an overlapping portion.