JPH11127219A - Data transfer equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer equipment capable of simply and inexpensively constructing an interactive type communication system for performing communication among one master set and many slave sets on both sides of hardware and software. SOLUTION: A UART 30 for loop system is constituted of a data transmission part 15 consisting of a data bus 11, a transmission buffer 12, a transmission shift register 13 and a transmission pin 14, a data reception part 19 consisting of a reception buffer 16, a reception shift register 17 and a reception pin 18, a loop switch 31 for executing a changeover to loop transmission data back to the reception side, a waveform reshape circuit 32 for executing a waveform reshape and high speed retransmission, and a control register 33 for controlling the loop switch 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data transfer device, and more particularly, to a data transfer device having a function of performing bit serial data transfer by an asynchronous method.

[0002]

2. Description of the Related Art Among current microcomputer application technologies, serial data transfer as a connection method between computer systems is one of important interface technologies.

[0003] Regarding the serial data transfer method, from the viewpoint of the characteristics of the IC, the UART (universal asynch
ronous receiver transmitter) and USRT (universal
There is an IC for LAN such as an Ethernet recently.

[0004] The basic structure of a conventional UART of this type is as follows.
Generally, it is as shown in FIG.

In FIG. 4, UART is a data bus 1
1, transmission buffer 12, transmission shift register 13
And a data transmission unit 15 including a transmission pin 14 and a reception buffer 16, a reception shift register 17, and a data reception unit 19 including a reception pin 18.

[0006] The data transmission section 15 has the following signal flow.

CPU (not shown) through data bus 11
The transmission data written in the transmission buffer 12 by the transmission shift register 13 which is a parallel-serial converter is added with a start bit, a stop bit, or a parity bit, becomes a serial signal, and becomes a serial signal with a specified pulse width. Output.

In the data receiving section 19, the following signal flows.

When serial data having a pulse width designated in advance is input to the reception pin 18, the data is input to a reception shift register 17, which is a serial / parallel converter, where the start bit, stop bit, or parity is input. The bits are removed and temporarily stored in the reception buffer 16 as parallel data. The CPU reads this data as received data.

[0010] Among existing UARTs, there is a UART with a loop switch as shown in FIG.

FIG. 5 is a block diagram showing the basic structure of a UART with a loop switch. The same components as those of the UART shown in FIG. 4 are denoted by the same reference numerals.

In FIG. 5, a UA with a loop switch
RT is a data transmission unit 15 including a data bus 11, a transmission buffer 12, a transmission shift register 13, and a transmission pin 14, and a data reception unit including a reception buffer 16, a reception shift register 17, and a reception pin 18. Part 1
9 and loop switches 20 and 21 for switching the transmission data to the receiving side in the test mode.
And a control register 22 for controlling the loop switches 20 and 21.

In the above configuration, the loop is disabled by the control register 22 and the loop switches 20 and 2 are disabled.
When 1 is set, the operation is the same as the operation of the UART shown in FIG. On the other hand, when the loop switches 20 and 21 are set as loop enabled by the control register 22,
The transmission data written in the transmission buffer 12 is output as a serial signal by the transmission shift register 13,
The signal passes through the loop switch 20 and the loop switch 21 and is input to the reception shift register 17 to be converted into parallel data, which is stored in the reception buffer 16 as reception data. This loopback function is a function for testing the IC.

[0014]

In the current microcomputer application system, one master sends data requests and commands to many slaves, and many slaves send data to the master in response to the request. There are a number of serial transfer systems that send data or behave in response to commands. At present, a LAN-IC such as an internet or an arcnet is often used for this purpose. However, these methods have problems in that the hardware cost is high and software control is difficult.

That is, as described above, UART and US
RT is a one-to-one interactive type, and when a large number of connections are made, the burden on hardware and software increases.
In addition, LAN-IC such as Internet and Arcnet
In the case of using, although all the master units and the slave units can communicate with each other, the communication between the slave units is overspecified, and the hardware and software to be controlled are complicated and expensive.

For example, in the case of the UART shown in FIG.
Since there is no path connecting the reception pin 18 and the transmission pin 14, it is not easy to use the connection in a loop connection as shown in FIG. That is, the CPU reads the received data once and writes it again as transmission data in the transmission buffer 12, resulting in poor system efficiency.

Also, in the case of the UART with a loop switch shown in FIG. 5, there is a similar problem because only a loopback function for testing an IC is added.

Further, in the loop system as shown in FIG. 6, it is necessary to receive data while looping the data.
In this case, if transmission and reception are simply performed in multiple stages without performing waveform shaping, the pulse waveform of serial data may be greatly distorted, resulting in a data error, and a problem occurs in an easy loop circuit.

In any case, since the conventional UART is based on a one-to-one connection, application to a loop system in which a master unit and a number of slave units are connected in a loop as shown in FIG. , There was a problem in operation.

An object of the present invention is to provide a data transfer apparatus capable of easily and inexpensively constructing a one-to-many interactive communication system of a master unit and a slave unit using both hardware and software. I do.

[0021]

According to a first aspect of the present invention, there is provided a data transfer apparatus including a data transfer means for performing bit-serial data transfer by an asynchronous system, which receives received data and A waveform shaping unit having a loop path for looping the transmission data as transmission data to the transmission side, being provided on the loop path, and shaping the waveform of the received data; a switch means being provided on the loop path and switching whether or not looping is possible; Control means for switching the means so that the reception data can be looped to the transmission side through the waveform shaping means.

The waveform shaping means may include a register capable of outputting input data at the minimum clock timing, and may retransmit received data to the transmitting side at high speed via the register during a loop.

The data transfer means is a UART (universal asynchronous) using an asynchronous serial transfer method.
receiver transmitter).

The data transfer device is provided with an identification code (ID number) for identifying itself, an identification means for reading the identification code and processing only the corresponding data, and a data for temporarily storing transmission / reception data. And a holding means.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data transfer device according to the present invention comprises:
The present invention can be applied to a serial data transfer device that transfers serial data.

FIG. 1 is a block diagram showing a basic configuration of a serial data transfer device according to an embodiment of the present invention. In the description of the serial data transfer device according to the present embodiment, the same components as those of the UART shown in FIG. 4 are denoted by the same reference numerals.

In FIG. 1, UART for loop system
(Data transfer device) 30 includes a data bus 11, a data transmission unit 15 including a transmission buffer 12, a transmission shift register 13, and a transmission pin 14, and a reception buffer 1.
6. A data receiving section 19 comprising a receiving shift register 17 and a receiving pin 18, a loop switch 31 (switch means) for switching transmission data to loop back to the receiving side, and a waveform shaping and high-speed retransmission of the receiving data. And a control register 33 (control means) for controlling the loop switch 31.

From the reception (RXD) pin 18 through the waveform shaping circuit 32 and the loop switch 31, the transmission (TX)
D) The path to the pin 14 constitutes a loop path for constructing a loop system as a whole.

The control register 33 includes a CPU
And the like, and controls the loop switch 31 corresponding to the reception operation, the transmission operation, the loop operation, and the like. The control of the loop switch 31 will be described later in detail.

The waveform shaping circuit 32 corrects the received distorted data. Generally, a serial signal passes over a system connected by a wire, an optical cable, or the like, and at this time, distortion occurs. Further, retransmission in multiple stages on the loop system may increase the distortion and cause a data error. The waveform shaping circuit 32 performs a waveform shaping and a noise cut. In other words, in order to cut small noise of high frequency superimposed on the serial signal on the cable, the conventional U
The waveform shaping circuit 32 has a function of a high-speed retransmission that can retransmit an input and an output with a delay of 1 + 1/2 bits as a function similar to the start bit detection function. Having. These functions will be described later with reference to FIG.

As described above, the UART3 for the loop system
0 indicates that the loop switch 31 and the waveform shaping circuit 32 are arranged on the loop. Waveform shaping circuit 32
Is a major feature for constructing a loop system as described above, and has functions of waveform shaping, noise cutting, and high-speed retransmission.

FIG. 2 is a block diagram showing a detailed configuration of the loop switch 31.

In FIG. 2, reference numeral 41 denotes a loop switch,
2 is a reception input (RXD), 43 is a data active detection circuit, 44 is a switch control circuit for controlling the loop switch 41, 45 is a transmission output (TXD), and an output request is issued in accordance with an output permission request from the switch control circuit 44. A control unit 46 for issuing and controlling the switch control circuit 44;
47 is a reception clock supplied to the data active detection circuit 43, 15 is a data transmission unit, 19 is a data reception unit,
32 is a waveform shaping circuit.

FIG. 3 is a block diagram showing a detailed configuration of the waveform shaping circuit 32.

In FIG. 3, reference numeral 51 denotes a noise detection circuit;
2 is a shift register capable of outputting input data at the minimum clock timing, 53 is a control register, 54 is a basic clock, 41 is a loop switch, and 42 is a reception input (RX
D) and 45 are transmission outputs (TXD).

The output of the control register 53 and the basic clock 54 are input to the noise detection circuit 51 and the shift register 52, respectively.

The waveform shaping circuit 32 performs a waveform shaping operation on the received data, and performs a shift register operation at the time of looping.
And retransmits the received data to the transmitting side at high speed.

Hereinafter, the operation of the loop system UART 30 configured as described above will be described. First, the overall operation of the loop system UART 30 will be described.

In the loop system UART 30, a loop switch 31 and a waveform shaping circuit 32 are arranged on a loop. The loop switch 31 is set by a control register 33 and performs the following operation.

[When the Loop Switch 31 is Set to Enable Looping] The loop switch 31 is basically set to the B side by the control register 33. And
The reception data input from the reception pin 18 is input to the reception shift register 17 and is fetched through the reception buffer 16 to become reception data. The reception data is passed through the waveform shaping circuit 32 and the waveform distorted by the waveform shaping circuit 32 is corrected. Then, it is transmitted again from the transmission pin 14.

However, when the loop system UART 30 attempts to transmit data, when the data of the waveform shaping circuit 32 is not active (ie, when there is no received data and the idle state), the loop switch 31 automatically switches to A. The transmission data written in the transmission buffer 12 is output to the transmission pin 14 through the transmission shift register 13 as a serial signal.

This type of usage can be applied to many slave units in the loop system shown in FIG. That is, it is suitable for application when a command or the like is sent from the master unit to each slave unit.

[When the Loop Switch 31 is Set to Disable Looping] The loop switch 31 is set to the A side by the control register 33. At this time, the reception data of the serial signal input from the reception pin 18 is
The data is serial-parallel converted by the reception shift register 17 and stored in the reception buffer 16. And CP
U reads it as received data. Also, CPU
The transmission data written in the transmission buffer 12 is converted from parallel to serial by the transmission shift register 13 and becomes a serial signal, which is output from the transmission pin 14.

This type of usage is applied to the parent machine in the loop system shown in FIG. In this case, this is to prevent a permanent loop of the transmission data transmitted on the loop system, and it is only necessary that the transmitted transmission data loop and reach the parent device. It is adapted to a multi-interactive loop system.

Next, the operations of the loop switch 31 and the waveform shaping circuit 32 will be described in more detail with reference to FIGS.

As described above, the loop switch 31 sets whether the basic operation is loopable or not, by setting the control register 33. In FIG. 2, the control units are collectively shown on the left side of the figure, and the control by the control register 33 is executed by the control register unit 48.

(1) When Looping is Disabled When the loop control bit of the control register section 48 is set as looping disabled, the switch control circuit 44 detects that the data active detection circuit 43 is not receiving data but is idling. Then, the loop switch 41 is set to the A side. This is an operation for preventing a line error due to switching during reception data loop.
Uses the data reception clock 47 to check whether the system is idling or receiving data.

The idling is detected by setting the start bit to L in the serial asynchronous transfer format.
Since there is the timing of the low level, if the High level of one character or more continues from the timing of the low level, it is determined that the vehicle is idling.

When the loop is disabled, the data transmission unit 15 and the transmission output 45 are fixed and connected, and there is no data loop.

This type is an example of a loop system:
Used by the parent machine, the received data is only received by the data receiving section 19, thereby preventing the loop from being permanently looped.

(2) When loop is enabled When the loop control bit of the control register section 48 is set to enable loop, when the data receiving section 19 of the loop system UART 30 is not trying to output data, the switch control circuit 44 sets the data. When the active detection circuit 43 detects that the reception input 42 is idling, the loop switch 41 is set to the B side. As a result, the serial data input to the reception input 42 is
, And re-output to the transmission output 42 through the waveform shaping circuit 32.

This is the data loop state.

In this state, the loop system U
When the data transmission unit 15 of the ART 30 attempts to output data, the control unit 46 outputs an output request to the switch control circuit 44. The switch control circuit 44 switches the loop switch 41 to the A side when the data active detection circuit 43 detects idling. Then, an output permission signal is output to the data transmission unit 15.

This type is, in the example of a loop system,
The data used by a number of slaves and input to the reception input 42 is received by the data reception unit 19, passes through the waveform shaping circuit 32, and is retransmitted to the transmission output 45.

As described above, the slave unit can be made to respond to the request of the master unit, and is suitable for a one-to-one response between the request of the master unit and a number of slave units.

Next, the operation of the waveform shaping circuit 32 will be described.

The operation of the waveform shaping circuit 32 corrects the distortion of the waveform when retransmitting the received data when constructing the loop system as described above, and removes the high-frequency noise that has entered the line. Another object of the present invention is to increase the line efficiency of the loop system by retransmitting the received data with a small time delay while performing these operations.

As shown in FIG. 3, the waveform shaping circuit 32
It comprises a noise detection circuit 51 and a shift register 52.

The noise detection circuit 51 is a general UART
In the same manner as the receiving unit, the falling of the input data of the receiving input 42 is checked. When the falling edge of the input data is detected, it is determined whether or not it is at the Low level after half the time of one character clock. If there is the Low level, the data is sent to the shift register 52. The detection clock is generated according to the frequency division value set by the control register 53 based on the basic clock. The basic clock is a clock of about 1/16 of one bit of serial data, and performs central sampling to determine whether or not the signal is at the low level at the eighth clock from the detection of falling.

Once the noise detection circuit 51 detects a low signal, the noise detection circuit 51 detects the signal with the same phase until the next fall, and performs detection so that central sampling is performed. That is, in a loop line to which many loop system UARTs 30 are applied, even if data is transmitted with the same pulse width,
Since the phases of many UARTs 30 are different, the phases of the input data are also different. Therefore, the above-described detection method is performed.

The shift register 52 includes a noise detection circuit 5
This is a buffer for re-outputting data from 1 with a pulse width of 1 bit. This pulse is output to the noise detection circuit 5
The phase is variable so as to match the phase of one signal. The pulse width divides the basic clock 54 by the value set by the control register 53. As described above, when the basic clock is 1/16, the value to be set is 16.

Further, looking at the time delay, it is found that 1
The data is output from the noise detection circuit 51 with a delay of 1/2 clock and output from the shift register 52 with a delay of 1 clock. That is, the data of the loop output is outputted only by delay of 1 + 1/2 clock from the input.

As described above, the loop system UART 30 according to this embodiment includes the data bus 11, the transmission buffer 12, the transmission shift register 13, and the transmission pin 14; Buffer 16, receiving shift register 17, and receiving pin 18
A data receiving unit 19, a loop switch 31 for switching transmission data to loop back to the receiving side,
Since it is provided with the waveform shaping circuit 32 for shaping the received data and performing high-speed retransmission, and the control register 33 for controlling the loop switch 31, the control of the software is easy and the start-up is inexpensive in hardware. UA for loop system using synchronous serial transfer method
RT can be realized.

Therefore, the UART for this loop system
Is connected on the loop line as a master unit and a number of slave units, a loop system having a very simple configuration and a high degree of freedom can be constructed.

By the way, in the UART for the loop system, in order to control operation such as reception, transmission or a loop, and to further improve the efficiency of the loop line, additional functions may be provided in the following points.

(1) In order to automate the judgment of reception, this loop system UART has the same ID as the LAN-IC.
Add features.

(2) To facilitate CPU control when the transfer rate is increased, a transmission buffer and a reception buffer of about several tens to several hundreds of bytes are provided.

(3) An interrupt signal is generated when transmission is completed or reception is completed, so that the CPU can quickly detect each state.

If the functions described above are added to increase the line efficiency and each control is automated, a more user-friendly system can be realized.

In this embodiment, an example is described in which the present invention is applied to a UART using a start-stop synchronous serial transfer method. However, the present invention is not limited to this, and any device having data transfer means for performing bit-serial data transfer can be used. It can be applied to any device.

Further, various circuits constituting the URAT,
It goes without saying that the types, numbers, connection methods, and the like of the loop switches, buffers, registers, and the like are not limited to the above-described embodiment.

[0072]

The data transfer apparatus according to the present invention has a loop path for receiving received data and looping the transmission data as a transmission data to the transmitting side, and is provided on the loop path to shape the waveform of the received data. A shaping unit, a switch unit that is provided on a loop path and switches whether or not a loop is possible, and a control unit that enables the received data to be looped to the transmission side through the waveform shaping unit by switching the switch unit. As a result, a UART for a loop system using a start-stop synchronous serial transfer method that can easily control software and is low cost in hardware can be realized, and a one-to-many interactive communication system of a master unit and a slave unit can be implemented in hardware. It can be built easily and at low cost in both hardware and software.

Therefore, the present invention is very effective when applied to a one-to-many interactive communication system that hardly requires communication between slave units.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data transfer device according to an embodiment to which the present invention has been applied.

FIG. 2 is a block diagram showing a detailed configuration of a loop switch of the data transfer device.

FIG. 3 is a block diagram showing a detailed configuration of a waveform shaping circuit of the data transfer device.

FIG. 4 is a block diagram of a conventional UART.

FIG. 5 is a block diagram of a conventional UART with a test loop switch.

FIG. 6 is a diagram for explaining a loop system.

[Explanation of symbols]

Reference Signs List 11 data bus, 12 transmission buffer, 13 transmission shift register, 14 transmission pin, 15 data transmission section, 16 reception buffer, 17 reception shift register, 18 reception pin, 19 data reception section, 30
UART for loop system (data transfer device), 31,
41 loop switch (switch means), 32 waveform shaping circuit (waveform shaping means), 33 control register (control means), 42 reception input (RXD), 43 data active detection circuit, 44 switch control circuit, 45
Transmission output (TXD), 46 control unit, 47 reception clock, 51 noise detection circuit, 52 shift register, 53 control register, 54 basic clock

Claims (4)

[Claims] 1. A data transfer device comprising a data transfer means for performing bit-serial data transfer by a start-stop synchronization method, comprising: a loop path for receiving received data and looping as transmission data to a transmission side; A waveform shaping unit provided on the loop path for shaping a waveform of received data; a switch unit provided on the loop path for switching whether or not looping is possible; by switching the switch unit, the received data is subjected to the waveform shaping. Control means for enabling a loop to the transmitting side through the means. 2. The apparatus according to claim 1, wherein said waveform shaping means includes a register capable of outputting input data at a minimum clock timing, and retransmits received data to said transmitting side at a high speed via said register during a loop. 2. The data transfer device according to 1. 3. The data transfer means according to claim 1, wherein the data transfer means uses a UART (univer
2. The data transfer device according to claim 1, wherein the data transfer device is a sal asynchronous receiver transmitter. 4. The data transfer device according to claim 1, further comprising an identification code (ID number) for identifying itself, an identification unit that reads the identification code and processes only the corresponding data, And a data holding means for temporarily storing data.