JPH11112486A - Synchronization recovery system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronization recovery system in which a probability of causing false synchronization is reduced with respect to serial data arranged by adding respective synchronizing signals to plural packets. SOLUTION: A transmitter side adds a specific synchronization pattern to the head of each packet of serial data while inverting the pattern in each packet. A synchronization pattern comparison means 15c in a synchronization recovery device 15 is at a receiver side compares the synchronization pattern of the serial data with the synchronization pattern stored in advance in a synchronization pattern storage means 15a and allows a pulse signal generating means 15f to generate a pulse signal equivalent to a period up to a time corresponding to a packet length from a coincident timing when they are coincident. The pulse signal is compared with a coincident signal from the synchronization pattern comparison means 15c, and when they are coincident, coincident information is outputted as a synchronizing signal and the synchronization pattern read from the synchronization pattern storage means 15a is inverted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous reproduction system for performing synchronous reproduction of serial data having a plurality of packets on the receiving side based on a synchronization pattern added to the head of the packet.

[0002]

2. Description of the Related Art Generally, in a synchronous reproduction system,
When the receiving side detects and reproduces a synchronization signal from the packetized serial data, the pattern comparison circuit detects the synchronization pattern superimposed on the first two bytes of the packet, and then determines the period in which the next synchronization pattern exists. The counter is counted, and a false detection with data other than the synchronization pattern is avoided by comparing and detecting.

In the above-described synchronization detection method, if the same value as the synchronization pattern exists other than at the beginning of the packet of the serial data, false synchronization will occur. Therefore, as a countermeasure to suppress the false synchronization, the comparison detection result is input to the backward synchronization protection circuit to count the number of matches, and further input to the forward synchronization protection circuit to count the number of mismatches. Based on the result, it is determined whether or not synchronization is established. However, by taking this measure, the probability of causing false synchronization is somewhat reduced, but there is a demand for a synchronous reproduction system capable of further reducing the probability of causing false synchronization.

[0004]

As described above, in the above-mentioned synchronous reproduction system, as a method of reducing false synchronization, the number of bits corresponding to the packet length counted by the counter in the backward synchronization protection circuit, The number of matches with the signal is counted, and if the count result has reached a predetermined number, it is determined that synchronization has been established, the number of mismatches is counted by the forward synchronization protection circuit, and the count result reaches the predetermined number. In such a case, the probability of occurrence of false synchronization is reduced by judging that synchronization is lost. However, a system that further reduces the probability of occurrence of false synchronization is demanded.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous reproduction system which can reduce the probability of causing false synchronization and improve the reliability of synchronous reproduction for serial data arranged by adding a synchronization signal to each of a plurality of packets. Is to do.

[0006]

A synchronous reproduction system according to the present invention transmits serial data arranged by adding a synchronization signal to each of a plurality of packets on a transmitting side, and transmits the serial data on a receiving side when receiving the serial data. A synchronous reproduction system for detecting a synchronization signal in units of packets by a synchronous reproduction device and reproducing data, wherein a transmitting side inverts a specific synchronization pattern value at the beginning of a packet with respect to serial data for each packet. It is characterized in that it is added.

According to this configuration, a specific synchronization pattern value is added to the beginning of a packet of serial data in which a plurality of packets are arrayed on the transmitting side, inverted for each packet, and added on the receiving side. The synchronous playback device recognizes the synchronous pattern value added to the head of the serial data packet and its inverted value, and compares the synchronous pattern value and the inverted value in the serial data with a timing corresponding to a unit packet length. Detection is performed and synchronous reproduction is performed.

As a result, even when the same value as the synchronization pattern value exists at a position other than the beginning of the packet of the serial data, the probability of causing false synchronization can be reduced, and the synchronization pattern value is inverted for each packet. The detection probability of synchronization in the forward synchronization protection circuit and the backward synchronization protection circuit is improved, and the reliability in synchronous reproduction can be improved.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a DVC (Digital Video Cas) to which an embodiment of the present invention is applied.
sette Recorder) shows the receiving part of the system.

In FIG. 1, transmitted DVC serial data (DVCS) is RECEIVER + RECLO.
It is supplied to the CK unit 11. This RECEIVER + RE
The output of the CLOCK unit 11 is NRZI (Noise Reduction).
Zero Inverter 12 performs NRZI conversion processing such as noise reduction, and 16B (Bit) 1C (Complementary) deletion unit 13 deletes 1-bit complementary data added every 16 bits. Then, the serial data from which the complementary data has been deleted is decrypted by the descrambler 14 and synchronously reproduced by the synchronous reproducer 15. The output of the synchronous playback unit 15 is
The serial / parallel (S / P) converter 16 converts the serial data into parallel bus data. The transmission synchronization deleter 17 deletes two transmission synchronization words, and the error corrector 18 corrects the error. Done. After that, DVC
In the S depacket unit 19, the output of the error correction unit 18 is depacketized and output to the DVC BUS.

FIG. 2 shows the structure of DVC serial data transmitted from the transmission section of the DVC system.
That is, the DVC serial data is packetized every 184 words, for example. Then, a specific synchronization pattern value 135Eh is added to the first two bytes of this packet, and an inverted synchronization pattern value ECA1h is added to the head of the next packet. Note that this DVC
The serial data will be transmitted at 36 Mbps.

FIG. 3 shows a detailed block configuration of the synchronous reproduction section 15 according to an embodiment of the present invention.
That is, the synchronous reproduction section 15 includes a synchronous pattern value storage section 15a for storing a synchronous pattern value previously added to the head of a packet of input data which is DVC serial data and its inverted value. The synchronization pattern value storage unit 15a includes storage means 15a1 for storing the synchronization pattern value 135Eh, storage means 15a2 for storing the synchronization pattern value ECA1h, and storage means 15a1,1.
A switch 15a3 for switching 5a2 is provided.

The input data is input to a 16-bit shift register 15b. The 16-bit shift register 15b stores the input data in the converter 1 every 16 bits.
5c. The converter 15c compares the input data with the synchronization pattern value read from the synchronization pattern value storage unit 15a, and outputs a match signal only when they match.

The coincidence signal output from the converter 15c is first input to an RS-FF (Flip Flop) circuit 15d to activate a packet cycle counter 15f via an AND circuit 15e. The packet cycle counter 15f counts the number of bits (1472 bits) for the unit packet length, and supplies a pulse signal corresponding to the counted packet length cycle to one input terminal of the AND circuits 15g and 15h. A match signal output from the converter 15d is supplied to the other input terminal of the AND circuit 15g.
The pulse signal output from the signal f is compared with the pulse signal, and the coincidence information is output only when the pulse signal coincides with the pulse signal. Also, the AND circuit 15h
A signal obtained by inverting the synchronization signal output from the converter 15d by the inverting circuit 15i is supplied to the other input terminal, and this signal is compared with the pulse signal output from the packet period counter 15f, and the signals are matched. Outputs mismatch information in case.

The coincidence information output from the AND circuit 15g is supplied to a T-FF serving as a synchronous pattern value switching control means.
It is supplied to the circuit 15j. This T-FF circuit 15j
By inputting the matching information from the AND circuit 15g,
The switch 15a3 of the synchronization pattern value storage unit 15a is switched to the inverted value 15a2.

The output of the converter 15c is OR
The packet period counter 15f is reset by being input to the clear terminal of the packet period counter 15f via the circuit 15k and the AND circuit 151.

The output of the AND circuit 15g is supplied to a backward synchronization protection circuit 15m. Back synchronization protection circuit 15
m counts the number of matches between the output of the converter 15c and the output of the packet cycle counter 15f based on the output of the AND circuit 15g, and when the count result becomes four or more, a reproduction request is issued by the converter 15n. Output a signal. Then, the reproduction request signal is RS-FF
When input to the set terminal of the circuit 15o, the D-FF circuit 15q is set via the AND circuit 15p.
Thereafter, the D-FF circuit 15q outputs the output of the packet cycle counter 15f and the RS-FF circuit 1 by the AND circuit 15p.
A signal whose output coincides with the output of 5o is output at the timing of the clock signal, and synchronous reproduction is performed.

Further, the output of the AND circuit 15h is supplied to a forward synchronization protection circuit 15r. Forward synchronization protection circuit 1
5r counts the number of mismatches between the output of the converter 15c and the output of the packet period counter 15f based on the output of the AND circuit 15h, and this count result is 4
When the number of times becomes equal to or more than the number of times, the converter 15s outputs a signal indicating the loss of synchronization, and the packet period counter 15
Reset f.

The backward synchronization protection circuit 15m has an AND
At the time of output from the circuit 15h, a reset is applied by the AND circuit 15t, and the forward synchronization protection circuit 15r
At the time of output of 5g, the AND circuit 15u is reset.

Further, at the time of power ON reset, T-
The switch 15a3 is switched to the storage means 15a1 side so that the synchronization pattern value storage section 15a is set to the initial synchronization pattern value by the FF circuit 15j, and the converter 15c, the packet cycle counter 15f, the backward synchronization protection circuit 15m, and the forward synchronization protection. Circuit 15r and RS-FF
The circuit 15o is reset.

Next, the synchronous reproducing section 15 performs an operation of synchronous detection as shown in the flowchart of FIG. First, when the power is turned on (step S11), the synchronization pattern value storage unit 15a is set to an initial synchronization pattern value (step S12). Then, the T-FF circuit 15j
Switches the synchronization pattern value read from the synchronization pattern value storage unit 15a to the inverted value at the synchronization timing of the next packet (step S13).

Next, in step S14, in an indeterminate synchronization state (NG), the converter 15c compares the input data with the synchronization pattern value read from the synchronization pattern value storage unit 15a (step S15). If (YES), the packet period counter 15f is initialized and the counting operation is started (step S1).
6). Then, the packet period counter 15f counts the number of bits until a time corresponding to the packet length (step S17), and the AND circuit 15g converts the converter 15 to the number of bits.
The output of c is compared with the pulse signal output from the packet cycle counter 15f (step S18). Here, if they do not match (NO), the above step S15
If the values match (YES), the matching information is input to the backward synchronization protection circuit 15m (step S19), and the number of matches is counted (step S2).
0). Here, when the number of matches reaches four (N =
4) It is determined that synchronization is confirmed (step S2)
1) Thereafter, the process returns to the process of step S14.

In step S14, in the synchronization determined state (OK), the converter 15c compares the input data with the synchronization pattern value read from the synchronization pattern value storage 15a (step S22). Note that the processing in steps S22 to S24 is performed in the above steps S15 to S15.
Since the processing is the same as that in S17, the description is omitted.

The AND circuit 15h includes a converter 15c
Is compared with the pulse signal generated by the packet period counter 15f (step S25). If they match (NO), the mismatch information is input to the forward synchronization protection circuit 15r. (Step S26). Then, the number of mismatches is counted (step S27), and when the number of times has reached four (M = 4), it is determined that synchronization has been lost (step S28), and the process returns to step S14.

Therefore, according to the above-described embodiment, a specific synchronization pattern value is added to the beginning of a packet of serial data in which a plurality of packets are arranged on the transmitting side, inverting each packet. ing. Then, the serial data is compared with the synchronization pattern value stored in the synchronization pattern value storage unit 15a in advance by the converter 15c of the synchronization reproduction unit 15, and when they match, the counting operation of the packet period counter 15f is performed at this matching timing. To start counting up to the number of bits corresponding to the packet length.
5c is compared with the coincidence signal, and when they coincide with each other, this coincidence information is output as a synchronization signal.
In the T-FF circuit 15j, the synchronous pattern value read from the synchronous pattern value storage section 15a is switched to an inverted value, and the read state of the synchronous pattern value is maintained in the case of a mismatch.

For this reason, the synchronization pattern value added to the serial data and its inverted value are detected at the timing corresponding to the packet length, so that the detection probability of the synchronization in the backward synchronization protection circuit 15m and the forward synchronization protection circuit 15r is reduced. improves.

In the backward synchronization protection circuit 15m,
The number of matches between the pulse signal output from the packet period counter 15f and the match signal output from the converter 15c is counted based on the match information output from the AND circuit 15g serving as the synchronization determination means. When the number of times reaches four, the synchronous reproduction processing is performed. In the forward synchronization protection circuit 15r, based on the mismatch information output from the AND circuit 15h as the synchronization determination means, the packet cycle counter 15
The number of coincidences between the pulse signal output from f and the non-coincidence signal obtained by inverting the output of the converter 15c by the inverting circuit 15i is counted, and when the counted result reaches a predetermined number of four, the synchronous reproduction processing is performed. , The probability of causing false synchronization is reduced.

It should be noted that the present invention is not necessarily limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the scope of the present invention.

[0029]

As described in detail above, according to the present invention,
It is possible to provide a synchronous reproduction system that can reduce the probability of causing false synchronization with serial data in which a synchronization signal is added to each of a plurality of packets and that can improve reliability in synchronous reproduction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a receiving section of a DVC system to which an embodiment of a synchronous reproducing apparatus of a synchronous reproducing system according to the present invention is applied.

FIG. 2 is a diagram showing an example of serial data transmitted by a transmission unit of the DVC system.

FIG. 3 is a block diagram showing an embodiment of a synchronous reproducing apparatus of the synchronous reproducing system according to the present invention.

FIG. 4 is a flowchart shown to explain the operation of synchronization detection in the embodiment.

[Explanation of symbols]

15: Synchronous reproduction unit, 15a: Synchronous pattern value storage unit, 15a1, 15a2: Storage unit, 15a3: Switch, 15b: 16-bit shift register, 15c, 15n, 15s: Converter, 15f: Packet cycle counter, 15e, 15g, 15h , 15l, 15p: AND circuit, 15j: T-FF circuit, 15m: backward synchronization protection circuit, 15q: D-FF circuit, 15r: forward synchronization protection circuit.

Claims (5)

[Claims] 1. A transmission side transmits serial data in which a synchronization signal is added to each of a plurality of packets and arranged, and a reception side detects a synchronization signal in packet units by a synchronous reproduction device when receiving the serial data. A synchronous reproduction system for performing data reproduction by adding a specific synchronization pattern value to the serial data at the beginning of a packet by inverting the packet for each packet on the transmission side. Reproduction system. 2. The synchronous reproduction device, comprising: a synchronous pattern value storage means for storing a synchronous pattern value previously added to the head of the packet of the serial data and an inverted value thereof; A synchronization pattern value comparison unit that detects whether the added synchronization pattern value matches the synchronization pattern value read from the synchronization pattern value storage unit, and outputs a match signal when the detection is made; At the timing of the coincidence signal output from the pattern value comparison means, a pulse signal generation means for generating a pulse signal having a cycle up to a time corresponding to the packet length, and a coincidence signal output from the synchronization pattern value comparison means The pulse signal generated by the pulse signal generating means is compared with a pulse signal. And a control processing means for switching the synchronization pattern value read from the synchronization pattern value storage means to an inverted value and maintaining a read state of the synchronization pattern value in the case of a mismatch. 2. The synchronous reproduction system according to claim 1, wherein: 3. A pulse generating means of the synchronous reproducing apparatus,
A packet counting unit that counts the number of bits corresponding to the packet length, based on an output of the synchronization signal generation unit, wherein the control processing unit counts a result of the packet counting unit; Synchronization determining means for detecting whether or not the output coincides, outputting the coincidence information when they coincide with each other, and outputting the non-coincidence information when they do not coincide, and inputting the coincidence information output from the synchronous determination means. 3. The synchronous reproduction system according to claim 2, further comprising: a synchronous pattern value switching control unit that switches the synchronous pattern value read from the synchronous pattern value storage unit to an inverted value. 4. A method for counting the number of matches between the output of the packet counting means and the output of the synchronization pattern value comparing means based on the matching information output from the synchronization determining means. 4. The synchronous reproduction system according to claim 3, further comprising a synchronous protection means for performing synchronous reproduction processing when the number of times exceeds the limit. 5. A method for counting the number of mismatches between the output of the packet counting means and the output of the synchronization pattern value comparing means based on the mismatch information output from the synchronization determining means. 4. The synchronous reproduction system according to claim 3, further comprising an asynchronous protection unit for judging that the synchronization is out of synchronization and resetting the packet counting unit when the number exceeds the threshold value.