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JPH1074776A - Manufacture of field effect transistor - Google Patents

Manufacture of field effect transistor

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Publication number
JPH1074776A
JPH1074776A JP8247208A JP24720896A JPH1074776A JP H1074776 A JPH1074776 A JP H1074776A JP 8247208 A JP8247208 A JP 8247208A JP 24720896 A JP24720896 A JP 24720896A JP H1074776 A JPH1074776 A JP H1074776A
Authority
JP
Japan
Prior art keywords
effect transistor
field effect
insulating film
current
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8247208A
Other languages
Japanese (ja)
Inventor
Shigeki Yamaga
重來 山賀
Hiroyuki Fukuda
裕行 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP8247208A priority Critical patent/JPH1074776A/en
Publication of JPH1074776A publication Critical patent/JPH1074776A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing field effect transistor by which the service life of a field effect transistor can be prolonged by relieving the characteristic variation of the transistor, such as the decrease of the current between the source and drain of the transistor, etc., without changing the gate metal of the transistor. SOLUTION: In a method for manufacturing a field effect transistor provided with source and drain electrodes 5 and 6 formed apart from each other on the surface of a gallium arsenide substrate l, a gate electrode 7 which controls the value of the current flowing through the current passage between the electrodes 5 and 6, and an insulating film 8 coating the surface, the characteristic variation of the transistor is relieved by giving a compressive or tensile stress to the semiconductor substrate l in the current passage by forming the insulating film 8 on the current passage.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ショットキー接合
電界効果トランジスタの製造方法に関し、特に長時間の
動作に伴い、トランジスタ特性が変動するとき、この変
動を緩和し、トランジスタの長寿命化を図る電界効果ト
ランジスタの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a Schottky junction field-effect transistor, and more particularly, when transistor characteristics fluctuate with long-term operation, the fluctuations are alleviated and the life of the transistor is extended. The present invention relates to a method for manufacturing a field effect transistor.

【0002】[0002]

【従来の技術】シリコン基板あるいはガリウム砒素等の
化合物半導体基板に形成された半導体装置の信頼性を向
上させるためには、故障メカニズムを解明し、効果的な
対策を立てることが重要となる。
2. Description of the Related Art In order to improve the reliability of a semiconductor device formed on a silicon substrate or a compound semiconductor substrate such as gallium arsenide, it is important to clarify a failure mechanism and take an effective countermeasure.

【0003】例えば、ガリウム砒素MESFET(金属
−半導体電界効果トランジスタ)を例に取り説明する。
図1にMESFETの断面形状を示す。ガリウム砒素基
板1にイオン注入法によりチャネル領域2、ソース領域
3及びドレイン領域4を形成する。次に、ソース領域3
及びドレイン領域4にオーミック接触したソース電極5
及びドレイン電極6と、このソース領域3、ドレイン領
域4間に形成された電流経路となるチャネル領域2上
に、チャネル領域2を流れる電流値を制御する制御電極
として、ガリウム砒素基板1にショットキー接触したゲ
ート電極7が形成されている。更に表面を保護するた
め、プラズマCVD法により形成した窒化膜からなる絶
縁膜8で被覆した構造となっている。
[0003] For example, a gallium arsenide MESFET (metal-semiconductor field effect transistor) will be described as an example.
FIG. 1 shows a cross-sectional shape of the MESFET. A channel region 2, a source region 3, and a drain region 4 are formed in a gallium arsenide substrate 1 by an ion implantation method. Next, the source region 3
And source electrode 5 in ohmic contact with drain region 4
A gallium arsenide substrate 1 on the gallium arsenide substrate 1 as a control electrode for controlling a current value flowing through the channel region 2 on the channel region 2 serving as a current path formed between the source region 3 and the drain region 4 and the drain region 6. The contacting gate electrode 7 is formed. In order to further protect the surface, the structure is covered with an insulating film 8 made of a nitride film formed by a plasma CVD method.

【0004】絶縁膜8は、一例として、基板温度200
℃、アルゴンで体積比10%に希釈したモノシラン、ア
ンモニア、アルゴンをそれぞれ32sccm、51sc
cm、110sccmの割合で混合したガスを使用し、
圧力1Torr、13.56MHz、180Wの高周波
電力を印加し、1900オングストローム形成した。こ
の窒化膜は、ガリウム砒素基板に対する応力は、ほとん
ど無い。また、この窒化膜の屈折率が1.82であっ
た。
The insulating film 8 is formed, for example, at a substrate temperature of 200.
Monosilane, ammonia and argon diluted to 10% by volume with argon at 32 sccm and 51 sc, respectively.
cm, using a gas mixed at a rate of 110 sccm,
A high-frequency power of 1 Torr, 13.56 MHz, and 180 W was applied to form 1900 angstroms. This nitride film has almost no stress on the gallium arsenide substrate. The refractive index of this nitride film was 1.82.

【0005】このような構造のMESFETは、動作時
にチャネル層の温度が上昇し、ゲート金属がチャネル領
域中に拡散し、実質的なチャネル面積が減少し、ピンチ
オフ電圧の低下、ソース、ドレイン間電流の減少という
FET特性の変動が発生する。
In the MESFET having such a structure, the temperature of the channel layer rises during operation, the gate metal diffuses into the channel region, the actual channel area decreases, the pinch-off voltage decreases, and the source-drain current decreases. Fluctuates in the FET characteristics.

【0006】図3にFET特性の変動の一例を示す。こ
れは、MESFETを300℃、窒素雰囲気で所定時間
放置した後、室温で測定したゲート電圧0Vのときのソ
ース、ドレイン間の飽和電流値(Idss)の変化率を示
している。図に示すように、初期値の10%を超える変
動が発生した場合を故障とみなすと、この条件のMES
FETの寿命は、5時間であった。ソース、ドレイン間
の飽和電流値が減少するに伴い、ピンチオフ電圧、相互
コンダクタンス等のFET特性も同様に変動する。
FIG. 3 shows an example of a change in FET characteristics. This shows the rate of change of the saturation current value (Idss) between the source and the drain when the gate voltage is 0 V measured at room temperature after leaving the MESFET at 300 ° C. in a nitrogen atmosphere for a predetermined time. As shown in the figure, when a case where a fluctuation exceeding 10% of the initial value occurs is regarded as a failure, the MES under this condition is considered.
The life of the FET was 5 hours. As the saturation current value between the source and drain decreases, FET characteristics such as pinch-off voltage and transconductance also change.

【0007】このような変動を防止するため、耐熱性の
あるゲート金属を用いる方法が提案されているが、ガリ
ウム砒素に対して高いバリアハイトが得られる材料は限
られており、ゲート金属を多層に形成するなど、製造工
程が非常に複雑になるという欠点があった。
In order to prevent such fluctuations, a method using a heat-resistant gate metal has been proposed. However, materials capable of obtaining a high barrier height with respect to gallium arsenide are limited. There is a disadvantage that the manufacturing process becomes very complicated, such as formation.

【0008】[0008]

【発明が解決しようとする課題】本発明は上記欠点を解
消し、ゲート金属を変更することなしに、ソース、ドレ
イン間電流が減少する等のFET特性の変動を緩和し、
長寿命化を図った電界効果トランジスタの製造方法を提
供することを目的とする。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks and alleviates variations in FET characteristics such as a decrease in current between a source and a drain without changing a gate metal.
It is an object of the present invention to provide a method for manufacturing a field effect transistor having a long life.

【0009】[0009]

【課題を解決するための手段】本発明は上記目的を達成
するため、半導体基板表面に離間して形成された2つの
オーム性電極と、該オーム性電極間の電流経路と、該電
流経路を流れる電流値を制御する制御電極と、前記電流
経路を被覆する絶縁膜とを備えた電界効果トランジスタ
の製造方法において、電界効果トランジスタ動作時の特
性変動を緩和する特性変動を発生させる絶縁膜で、前記
電流経路を被覆することを特徴とするものである。特
に、前記電流経路を流れる電流値の変動を緩和する電流
値変動を発生させる応力を前記半導体基板に与える絶縁
膜で、前記電流経路を被覆することを特徴とするもので
ある。
In order to achieve the above object, the present invention provides two ohmic electrodes formed on a surface of a semiconductor substrate at a distance from each other, a current path between the ohmic electrodes, and a current path between the ohmic electrodes. In a method for manufacturing a field-effect transistor including a control electrode that controls a value of a flowing current and an insulating film that covers the current path, an insulating film that generates a characteristic change to reduce a characteristic change during operation of the field-effect transistor, The present invention is characterized in that the current path is covered. In particular, the present invention is characterized in that the current path is covered with an insulating film for applying a stress to the semiconductor substrate to generate a current value variation that alleviates a variation in a current value flowing through the current path.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施の形態につい
て説明する。図1に示す従来構造のFET同様、ガリウ
ム砒素基板1にイオン注入法によりチャネル領域2、ソ
ース領域3及びドレイン領域4を形成する。次に、ソー
ス領域3及びドレイン領域4にオーミック接触したソー
ス電極5及びドレイン電極6と、このソース領域3、ド
レイン領域4間に形成された電流経路となるチャネル領
域2上に、チャネル領域2を流れる電流値を制御する制
御電極として、ガリウム砒素基板1にショットキー接触
したゲート電極7が形成されている。更に、全面をプラ
ズマCVD法により形成した窒化膜からなる絶縁膜8で
被覆する。
Embodiments of the present invention will be described below. 1, a channel region 2, a source region 3, and a drain region 4 are formed in a gallium arsenide substrate 1 by ion implantation. Next, the channel region 2 is formed on the source electrode 5 and the drain electrode 6 in ohmic contact with the source region 3 and the drain region 4 and on the channel region 2 serving as a current path formed between the source region 3 and the drain region 4. A gate electrode 7 in Schottky contact with the gallium arsenide substrate 1 is formed as a control electrode for controlling a flowing current value. Further, the entire surface is covered with an insulating film 8 made of a nitride film formed by a plasma CVD method.

【0011】ここで絶縁膜8は、基板温度300℃、窒
素で体積比20%に希釈したモノシラン、アンモニア、
窒素をそれぞれ40sccm、9sccm、360sc
cmの割合で混合したガスを使用し、圧力0.7Tor
r、13.56MHz、100Wの高周波電力を印加
し、厚さ2000オングストローム形成した。この窒化
膜は、屈折率が2.03であり、従来の窒化膜の性質と
は異なる。このような条件でチャネル領域2上に形成さ
れた絶縁膜8は、ガリウム砒素との熱膨張率の違いか
ら、伸張応力が発生する。この応力により、ガリウム砒
素中に、圧電効果により電荷が発生し、更に、FET表
面がプラズマにさらされることにより、FET特性が変
化する。
The insulating film 8 is made of monosilane, ammonia diluted to a volume ratio of 20% with nitrogen at a substrate temperature of 300.degree.
Nitrogen at 40 sccm, 9 sccm and 360 sc respectively
using a mixed gas at a pressure of 0.7 Torr
A high-frequency power of 13.56 MHz and 100 W was applied to form a film having a thickness of 2000 Å. This nitride film has a refractive index of 2.03, which is different from the properties of a conventional nitride film. Under such conditions, the insulating film 8 formed on the channel region 2 generates a tensile stress due to a difference in thermal expansion coefficient from that of gallium arsenide. Due to this stress, electric charges are generated in the gallium arsenide by a piezoelectric effect, and furthermore, the FET surface is exposed to plasma, thereby changing the FET characteristics.

【0012】主表面の結晶面が(100)のガリウム砒
素基板に、ゲート電極を<110>方向に延出するよう
に形成し、チャネル領域上にプラズマCVD法により窒
化膜を形成すると、チャネル領域を流れる電流値が減少
することが知られている。さらに一旦、減少した電流値
は、時間の経過とともに、その電流減少を緩和する方向
に特性が変動する。即ち、絶縁膜を被覆することによ
り、時間の経過とともに、チャネル領域を流れる電流値
が増加する方向に特性変動することになる。
When a gate electrode is formed on a gallium arsenide substrate whose main surface has a (100) crystal plane and extends in the <110> direction, and a nitride film is formed on the channel region by a plasma CVD method, It is known that the value of the current flowing through is reduced. Further, the characteristics of the once reduced current value fluctuate in a direction to alleviate the current decrease with time. That is, by coating the insulating film, the characteristics change in a direction in which the value of the current flowing through the channel region increases with time.

【0013】一方FETのゲート電極は、上述のよう
に、チャネル領域中に拡散し、チャネル領域を流れる電
流値が減少する方向に特性変動する。
On the other hand, as described above, the gate electrode of the FET diffuses into the channel region and changes its characteristics in the direction in which the value of the current flowing through the channel region decreases.

【0014】このような相反する特性変動を組み合わせ
ることによって、結果的にチャネル領域を流れる電流値
の変動を緩和し、FETの長寿命化を図ることが可能と
なる。図1に本発明のFETの特性変動を示す図を示
す。ここで、上述の条件同様、300℃、窒素雰囲気で
所定時間放置した後、室温で測定したゲート電圧0Vの
ときのソース、ドレイン間の飽和電流値(Idss)の変
化率を示している。図に示すように、初期値の10%を
超える変動が発生した場合を故障とみなすと、このME
SFETの寿命は、80時間の寿命となり、従来構造の
FETの16倍の寿命となる。
By combining such contradictory characteristic fluctuations, the fluctuation of the current flowing through the channel region can be reduced as a result, and the life of the FET can be extended. FIG. 1 is a diagram showing the characteristic fluctuation of the FET of the present invention. Here, the rate of change of the saturation current value (Idss) between the source and the drain at a gate voltage of 0 V measured at room temperature after being left for a predetermined time in a nitrogen atmosphere at 300 ° C. is shown in the same manner as described above. As shown in the figure, when a case where a fluctuation exceeding 10% of the initial value occurs is regarded as a failure, this ME
The lifetime of the SFET is 80 hours, which is 16 times that of the conventional FET.

【0015】以上、FETの動作に伴い、ゲート電極に
起因する電流値の変動が減少方向に変動し、絶縁膜の応
力の緩和に起因する電流値の変動が増加方向に変動する
場合について説明を行ったが、FETを形成するガリウ
ム砒素の結晶面とゲート電極の形成方向によっては、電
流値の変動が増加方向となる場合もある。その場合は、
絶縁膜の応力の緩和に起因する電流値の変動が減少方向
となるように構成すればよい。
The case where the fluctuation of the current value caused by the gate electrode fluctuates in the decreasing direction with the operation of the FET and the fluctuation of the current value fluctuates in the increasing direction due to the relaxation of the stress of the insulating film will be described. However, depending on the crystal plane of gallium arsenide forming the FET and the direction in which the gate electrode is formed, the fluctuation of the current value may increase in some cases. In that case,
What is necessary is just to comprise so that the fluctuation | variation of the current value resulting from the relaxation of the stress of an insulating film may become the decreasing direction.

【0016】絶縁膜の応力の緩和に起因する電流値の変
動を、増加方向あるいは減少方向のいずれかにするため
には、絶縁膜の形成条件を変えることで制御が可能であ
る。例えば、絶縁膜としてプラズマCVD法で形成した
窒化膜の場合を例にとる。基板温度300℃、窒素で体
積比20%に希釈したモノシラン、アンモニア、窒素を
それぞれ40sccm、9sccm、360sccmの
割合で混合したガスを使用し、圧力0.7Torr、1
00Wの高周波電力を印加し、厚さ2000オングスト
ロームの窒化膜を形成した。前述の形成条件と異なり、
印加する高周波電力の周波数を400KHzとする。生
成する窒化膜はガリウム砒素に対して圧縮の応力を発生
し、この応力の緩和に起因する電流値の変動は、減少方
向となる。また上述のように、上記印加する周波数を1
3.56MHzに変えると、生成する窒化膜はガリウム
砒素に対し伸張の応力を発生し、この応力の緩和に起因
する電流値の変動は、増加方向となる。このように、変
動の方向は、任意に制御することが可能である。また、
形成する膜厚、ガス組成、生成温度等を変えることで、
変動の時定数も変えることができる。これらは、FET
の特性変動の時定数の応じて、最適な条件を適宜選択す
ればよい。
In order to change the current value due to the relaxation of the stress of the insulating film in either the increasing direction or the decreasing direction, it is possible to control by changing the conditions for forming the insulating film. For example, a case of a nitride film formed by a plasma CVD method as an insulating film is taken as an example. At a substrate temperature of 300 ° C., a gas obtained by mixing monosilane, ammonia, and nitrogen diluted with nitrogen at a volume ratio of 20% at a ratio of 40 sccm, 9 sccm, and 360 sccm, respectively, was used at a pressure of 0.7 Torr and a pressure of 0.7 Torr.
A high-frequency power of 00 W was applied to form a 2000-Å-thick nitride film. Unlike the formation conditions described above,
The frequency of the applied high frequency power is 400 KHz. The generated nitride film generates a compressive stress on gallium arsenide, and the fluctuation of the current value caused by the relaxation of the stress is in a decreasing direction. As described above, the frequency to be applied is set to 1
When the frequency is changed to 3.56 MHz, the generated nitride film generates a tensile stress for gallium arsenide, and the fluctuation of the current value caused by the relaxation of the stress increases. Thus, the direction of the fluctuation can be arbitrarily controlled. Also,
By changing the film thickness to be formed, gas composition, generation temperature, etc.,
The time constant of the fluctuation can also be changed. These are FET
The optimum condition may be appropriately selected according to the time constant of the characteristic variation.

【0017】また、絶縁膜の形成方法は、プラズマCV
D法に限定されず、熱CVD法やスパッタ法であっても
良い。更に、絶縁膜も単層に限定されることなく、窒化
膜、酸化膜、窒化珪素酸膜のうち2種、あるいは3種類
を選択し、多層構造としても良い。
The insulating film is formed by a plasma CV
The method is not limited to the method D, and may be a thermal CVD method or a sputtering method. Further, the insulating film is not limited to a single layer, and two or three types of a nitride film, an oxide film, and a silicon nitride film may be selected to form a multilayer structure.

【0018】[0018]

【発明の効果】以上説明したように本発明によれば、F
ETの動作に伴い特性が変動する場合、その変動を緩和
するため、相反する変動を生じさせるような応力を半導
体基板に加えることにより、FET特性の変動を、実質
的に小さくすることができ、FETの寿命を大幅に長く
することができた。この半導体基板に与える応力は、通
常の半導体装置の製造工程に使用する絶縁膜の形成工程
を採用することができ、簡便な方法で実現することが可
能である。
As described above, according to the present invention, F
When the characteristics fluctuate with the operation of the ET, in order to alleviate the fluctuation, by applying a stress that causes a contradictory fluctuation to the semiconductor substrate, the fluctuation of the FET characteristics can be substantially reduced, The life of the FET was greatly extended. The stress applied to the semiconductor substrate can be realized by a simple method by using an insulating film forming process used in a normal semiconductor device manufacturing process.

【図面の簡単な説明】[Brief description of the drawings]

【図1】MESFETの構造を説明する断面図である。FIG. 1 is a cross-sectional view illustrating a structure of a MESFET.

【図2】本発明のMESFETの特性変動を示すグラフ
である。
FIG. 2 is a graph showing a characteristic variation of the MESFET of the present invention.

【図3】従来のMESFETの特性変動を示すグラフで
ある。
FIG. 3 is a graph showing a characteristic variation of a conventional MESFET.

【符号の説明】[Explanation of symbols]

1 ガリウム砒素基板 2 チャネル領域 3 ソース領域 4 ドレイン領域 5 ソース電極 6 ドレイン領域 7 ゲート電極 8 絶縁膜 Reference Signs List 1 gallium arsenide substrate 2 channel region 3 source region 4 drain region 5 source electrode 6 drain region 7 gate electrode 8 insulating film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板表面に離間して形成された2
つのオーム性電極と、該オーム性電極間の電流経路と、
該電流経路を流れる電流値を制御する制御電極と、前記
電流経路を被覆する絶縁膜とを備えた電界効果トランジ
スタの製造方法において、 電界効果トランジスタ動作時の特性変動を緩和する特性
変動を発生させる絶縁膜で、前記電流経路を被覆するこ
とを特徴とする電界効果トランジスタの製造方法。
1. A semiconductor device, comprising: a semiconductor substrate;
Two ohmic electrodes, a current path between the ohmic electrodes,
In a method for manufacturing a field effect transistor including a control electrode for controlling a current value flowing through the current path and an insulating film covering the current path, a characteristic variation that alleviates a characteristic variation during operation of the field effect transistor is generated. A method for manufacturing a field effect transistor, wherein the current path is covered with an insulating film.
【請求項2】 請求項1記載の電界効果トランジスタの
製造方法において、電界効果トランジスタ動作時の電流
値の変動を緩和する電流値変動を発生させる応力を前記
半導体基板に与える絶縁膜で、前記電流経路を被覆する
ことを特徴とする電界効果トランジスタの製造方法。
2. The method for manufacturing a field effect transistor according to claim 1, wherein the insulating film for applying a stress to the semiconductor substrate to generate a current value variation that alleviates a variation in a current value during operation of the field effect transistor, A method for manufacturing a field effect transistor, comprising covering a path.
JP8247208A 1996-08-29 1996-08-29 Manufacture of field effect transistor Pending JPH1074776A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8247208A JPH1074776A (en) 1996-08-29 1996-08-29 Manufacture of field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8247208A JPH1074776A (en) 1996-08-29 1996-08-29 Manufacture of field effect transistor

Publications (1)

Publication Number Publication Date
JPH1074776A true JPH1074776A (en) 1998-03-17

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP8247208A Pending JPH1074776A (en) 1996-08-29 1996-08-29 Manufacture of field effect transistor

Country Status (1)

Country Link
JP (1) JPH1074776A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007073555A (en) * 2005-09-02 2007-03-22 Furukawa Electric Co Ltd:The Semiconductor element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007073555A (en) * 2005-09-02 2007-03-22 Furukawa Electric Co Ltd:The Semiconductor element
US8525225B2 (en) 2005-09-02 2013-09-03 The Furukawa Electric Co., Ltd. Semiconductor device

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