JPH1069459A - Serial interface controller and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce processing time required for transmission and reception by the control of a serial interface. SOLUTION: A transmission buffer circuit 140 comprises separately in a transmission control information memory 141 for storing control information and a transmission data buffer 142 for storing data transferred from an input/ output bus and further, a frame synthesis circuit 131 for generating a frame from the control information for the transmission and the data is provided on the poststage of the transmission buffer circuit 140. The transmission control information memory 141 is divided into a plurality of areas and the control information estimated at the initialization is stored in the respective areas in the transmission control information memory 141 beforehand. At the transmission, only a field requiring change for the respective frames is updated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transfer control between nodes connected via a serial interface, and more particularly to a serial interface control device for connecting a serial interface to another input / output bus and a control method therefor. About.

[0002]

2. Description of the Related Art When data is transferred between nodes, an electric cable or a serial interface using an optical fiber may be used as a transmission medium. Such interfaces include ESCON and Fiber Channel. . In serial interface, usually
The data is transferred in a frame structure. The frame is
It consists of control information used for controlling data transfer and data to be actually transferred. At the beginning, a frame start code (hereinafter, SOF) indicating the start of a frame, and at the end, a frame end code (hereinafter, EOF) indicating the end of the frame. Is added. The control information stores a source address, a destination address, a frame identification number, and the like.

[0003] The length of one frame is defined by each interface standard. For example, in the case of Fiber Channel, the length of the control information is a fixed length of 24 bytes, the data is a variable length with a maximum length restricted, and the data length is a maximum of 21 bytes.
12 bytes. Therefore, when the transfer data length is larger than the maximum data length of the frame, the data is divided into a plurality of frames and transferred. FIG. 3 shows an example of a frame structure of a fiber channel.

In each node using a serial interface, a data transfer is often realized by connecting a serial interface controller to an input / output bus. Standard input / output buses include, for example, a PCI bus and Micro Channel.

[0005] In recent years, the data transfer speed of the serial interface has been improved. For example, in a fiber channel, a data transfer rate of a transmission medium can be 1 Gigabit / second or more. However, if the processing involved in controlling the data transfer between the serial interface and the I / O bus and the overhead time caused by the protocol processing in the serial interface account for a large proportion of the total transfer time, the effective data transfer time will decrease, There is a problem that the high data transfer speed of the medium cannot be utilized.

FIG. 13 shows a conventional example of a serial interface control device. Serial interface controller 10
Reference numeral 0 denotes a serial interface 110 for transmitting / receiving to / from the optical fiber cable 101, a parallel-to-serial conversion circuit 121 for converting parallel data to serial data, a serial-to-parallel conversion circuit 122 for converting serial data to parallel data, and operates on the CPU. A data transfer control unit 170 that is a microprogram; and a local memory 1 that temporarily stores the microprogram and frames to be transmitted and received.
80, and an input / output bus control unit 190.

When data is transferred from the input / output bus 103 to the serial interface 110 for data transmission to another node, the data is transferred from the memory 105 in the personal computer 104 via the input / output bus control unit 190.
The data is transferred to the local memory 180. The data transfer control unit 170 generates control information and stores the control information in the local memory 18.
After completing the frame on the parallel-serial conversion circuit 12
1 to the serial interface 110
Start sending to.

As described above, in the case of the data transfer method which is widely used in the past using the local memory 180 connected to the processor bus 160 as a buffer, the data to be transmitted is input / output bus 103 → processor bus 160 →
Since data must be transferred in the order of local memory 180 → processor bus 160 → serial interface 110, the same data is
Transfer twice, which increases the overhead. Further, as a result, the utilization rate of the processor bus 160 or the local memory 180 increases, and the processor bus 160 or the local memory 180 becomes a bottleneck part of the data transfer performance, which causes performance degradation.

When data is transferred from the serial interface 110 to the input / output bus 103, a frame received from the serial interface 110 is temporarily
After storing in the local memory 103, the input / output bus 190
Through the memory 1 in the personal computer 104
Transfer to 05. After analyzing the control information, the data transfer control unit 170 transfers the data to the input / output bus 103. The received data is stored in the serial interface 110
Since it is necessary to transfer data in the order of → the processor bus 160 → the local memory 180 → the processor bus 160 → the input / output bus 103, the same data is transferred twice on the processor bus 160, thereby increasing the overhead.

In order to solve this problem, a control information buffer for storing control information and a data buffer for storing data are provided, and a received frame is separated into control information and data. Could be sent to Also, at the time of transmission, it is conceivable to reduce the processing time for transmitting control information by transmitting the received control information as it is. Such a conventional example is disclosed in JP-A-6-124258.

[0011]

A main object of the present invention is to reduce processing time required for transmission and reception in controlling a serial interface.

In the conventional example, when transmission is performed using the received control information as it is, there is a problem that the control information cannot be changed. In the serial interface,
In many cases, the transmission destination responds to the frame transmitted by the transmission source with an acknowledgment frame (ACK) to confirm reception. In this case, since the control information in the frame differs between the received frame and the ACK frame, the control information has to be generated again in the conventional method.

Further, when data of variable length is separated from the control information, when data is transferred to the input / output bus, particularly when data is transferred using DMA, the number of data to be transferred when the DMA is started is increased. Need to be set. For this purpose, a means for measuring the number of data must be provided in the frame separating means. Further, the management means for managing the DMA setting, the number of received data, and the number of transfers to the input / output bus needs to recognize the number of received data.
The management means is often a microprogram. If the data of a plurality of received frames are transferred to the input / output bus at a time, the processing time required for the transfer can be reduced. In this case, however, the microprogram as the management means recognizes the number of received data. There is a need to. For this purpose, a means must be provided for the microprogram to recognize the number of received data. However, JP-A-6-12425
No. 8 does not disclose a method for separating control information and data.

In the serial interface protocol, it is necessary to transmit and receive a control frame such as the ACK frame described above. Protocols using control frames are often performed sequentially. For example, a data source cannot transmit a new frame until it receives an ACK. In the control frame, the control information occupies most of the frame, and the data length is often shorter than the control information length. Therefore, the generation time of the control information is exposed as the protocol processing overhead time, and the transfer efficiency is
There is a problem of drastic reduction. Therefore, the control information generation time of the control frame must be reduced as much as possible.

[0015]

A transmission buffer circuit is divided into a transmission control information memory for storing control information and a transmission data buffer for storing data transferred from an input / output bus. A frame synthesizing circuit for generating a frame from transmission control information and data is provided, and expected control information is stored in a transmission control information memory in advance. Update only the fields that need to be changed.

In a preferred embodiment of the present invention, the transmission control information memory is a dual port memory, and the transmission data memory is a FIFO memory.

The transmission control information memory is divided into a plurality of areas and stores control information for each frame type in each area.

Further, in the case where data larger than the maximum data length of one frame is divided into a plurality of frames and transferred, the data of a plurality of frames received sequentially and successively is stored in a reception data buffer memory. Then, the data is continuously transferred to the input / output bus by a single DMA transfer instruction.

The reception buffer circuit for storing frames received from the serial interface is divided into a reception control information buffer for storing control information and a reception data buffer for storing data to be transferred to the input / output bus. A frame separation circuit for separating a received frame into control information and data is provided at a stage preceding the buffer.

If the received data has a variable length, the frame separation circuit is provided with a counter for counting the number of received data.

Further, the frame separation circuit is provided with a selector for selecting and outputting a reception buffer output and a counter value. Further, the number of received data is added to the reception control information and stored in the reception control information memory.

In a preferred embodiment of the present invention, the reception control information memory and the transmission control information memory include S in the control information.
The OF and EOF are added and stored.

In a preferred embodiment of the present invention, the reception control information memory and the reception data memory are FIFO memories.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. Although the present embodiment is described using a fiber channel as a serial interface, the present invention is not limited to this.

FIG. 1 is a block diagram of a serial interface control device showing an example of a serial interface control method according to the present invention. In this embodiment, a memory for reception and a memory for transmission are prepared, and the memory for reception is composed of a reception control information memory for reception control information and a reception data memory for reception data. It is characterized by comprising a transmission control information memory for transmission control information and a transmission data memory for transmission data.

As shown in FIG. 1, the serial interface control device 100 is connected to another node 102 via an optical fiber cable 101 and to a personal computer 104 via an input / output bus 103.

First, the main configuration and data structure of the serial interface control device 100 will be described, and then the data flow will be described.

Serial interface control device 100
Is roughly composed of a serial interface 110, a parallel-serial conversion unit 121, a serial-parallel conversion unit 122, a frame synthesis circuit 131, a frame separation circuit 132, a transmission buffer circuit 140, and a reception buffer circuit 150. The serial interface 110 performs transmission / reception of light and conversion between light and electricity, and a CRC for error detection at the time of transmission.
When an error is detected and generated, the CRC is deleted from the frame. Parallel-to-parallel converter 121 and serial-to-parallel converter 1
Reference numeral 22 performs conversion between serial data and parallel data. The transmission buffer circuit 140 includes a transmission control information memory 141 for storing transmission control information and a transmission data FIFO 142 for transmission data. In the present embodiment, the transmission control information memory 141 is a dual port memory that can be simultaneously accessed from the frame synthesis circuit 131 and the processor bus 160. The reception buffer circuit 150 includes a reception control information FIFO 151 for storing reception control information and a reception data FIFO 152 for storing reception data.

Next, the structure of data flowing through the serial interface will be described.

FIG. 2 shows a data frame structure according to the present invention. Frame 201 flowing over serial interface
Starts with SOF, which is a control code indicating the start of a frame, and ends with EOF, which is a control code indicating the end of a frame. Subsequent to the SOF, a frame header as frame control information, actual data, and a CRC for error detection follow. SOF, CRC and EOF are 4 bytes, and
The frame header has a fixed length of 24 bytes. The data is variable length up to 2112B. When transmitting data of 2112 bytes or more, the data is divided into a plurality of frames and transmitted.

Next, the structure of the frame header will be described in detail with reference to FIG. The frame header 301 mainly includes D_ID indicating a destination address of the frame, S_ID indicating a source address, and R indicating a type of the frame.
_CTL and TYPE, F_CT indicating flow control information
L, SEQ_ID and OX_ID indicating the frame identification number
And RX_ID, and control information such as SEQ_CNT for identifying frames having the same frame identification number. When communicating with a certain node, D_ID,
Most of the control information such as S_ID can be set in advance and can be a fixed value. On the other hand, F_CTL
Since it contains flow control information, it needs to be set for each frame transmission.

Next, the frame separation circuit 13 shown in FIG.
2 will be described in detail. FIG. 4 shows a frame separation circuit 132.
1 is an example of a block diagram showing a detailed structure of FIG. The frame separation circuit 132 separates the received data into a header and data, and stores each frame header in the reception control information FIFO 151,
Further, control signals WT0 and WT1 for storing data in the reception data FIFO 152 are generated. The frame separation circuit 132 includes a control code detection unit 410, a reception state machine 420, a data number measurement unit 430 for measuring the number of received data, a multi-stage buffer 440 for temporarily storing received data, and a selector 450. . The control code detection unit 410 includes an SOF decoder 411 and an EOF decoder 412 for detecting SOF and EOF. The reception state machine 420
For 0, an enable signal of the data number counter 431 is generated. In addition, according to the control signal from the data measurement unit 430, the control signal WT0 stores the received data in the reception control information FIFO 151 when the number of received data is 28 or less, and stores the received data in the received data FIFO 152 when the number of received data is larger than 28. , WT
1 is generated. Further, the selector 450 generates a select signal for selecting data to be output to the reception buffer circuit 150 from the multi-stage buffer 440 or the data number counter 431.

The data number measuring section 430 includes a data number counter 431 and a comparator 432. Data counter 4
31 measures the number of bytes of the received data. Comparator
432 compares whether the counter value is less than 28 or greater than 28, and notifies the reception state machine 420 of the result.

As described above, the frame separation circuit 1
In the present embodiment of 32, when separating a received frame into a header and data, a data number counter for measuring the number of received data
431, multi-stage buffer 440 and data number counter 431
Is characterized in that a data count number can be added to a frame.

FIG. 5 is a state transition diagram of the reception state machine 420. If no data has been received, the idle state 501 is set. Upon receiving the SOF, the state transits to the frame header receiving state 502. When the frame header is received after receiving the SOF 4 bytes and the number of reception counters reaches 24, the data reception state 503 is set. Upon receiving the EOF, the state returns to the idle state 501 again.

Next, the transmission control information memory 601 will be described with reference to FIGS. FIG. 6 shows an address space of the transmission control information memory 601. The transmission control information memory 601 is divided into a plurality of areas for storing the SOF, the frame header, and the EOF. FIG. 7 shows the format of each area.

In this embodiment, an area for a frequently used frame and an area for general use are provided. Specifically, areas 0 to 6 include a data frame for each class.
A field that can be set as an area for an ACK frame before transmission is set in advance. In this embodiment, as described later, the setting is performed at the time of initialization of the adapter board. As a result, for example, when transmitting class 1 data,
It can be transmitted by updating only F_CTL, which is the flow control information of the class 1 data frame in area 0. Regions 7 to n are regions that can be used for general purposes, and control information for control frames that are used less frequently is generated as needed.

Next, the serial interface controller 10
The operation of the data transfer control unit 171 at the time of initialization of 0 is shown in FIG.
This will be described with reference to the flowchart shown in FIG. After the power-on reset, initial data is set in each area of the transmission control information memory (801). It waits until a device driver notifies the transfer destination address when transferring received data from another node to the input / output bus (802). After notification,
The transmission / reception is started by starting the operation of each hardware of the adapter board (803). By initialization, when a frame is transmitted, a header that has already been set is used, so that the header can be created only in fields that need to be changed for each frame, such as flow control information.
As a result, since the frame can be transmitted without newly generating all the headers, the processing time can be reduced. In addition, by recognizing the transfer destination address of the received data in advance for data reception, it becomes possible to transfer data to the input / output bus immediately after data reception.

Next, the data transfer control unit 17 at the time of data reception
Operation 1 will be described with reference to the flowchart shown in FIG. In the present embodiment, the reception of the class 1 data frame
The case where ACK_1 which is a response frame is transmitted is shown. When detecting the reception of the frame, the data transfer control unit 171 transfers the received control information to the memory (901) and performs analysis (902). SOF and TYPE
(903), it is recognized that the received frame is a class 1 data frame. Class 1 ACK_1 of the transmission control memory set when the adapter board was initialized
Only the fields that need to be changed, such as F_CTL, are updated in the area of the data transmission frame header (904). Further, transmission of an ACK_1 frame has started (907).
Thereafter, it waits for transmission completion (906). Transfer of the received data to the input / output bus is started (907), and after the transfer is completed (908), the device driver is notified of data reception (909).

In this embodiment, the case where the transmission of the ACK_1 frame and the transfer of the received data to the input / output bus are performed sequentially is described. However, when the transmission is performed in parallel, the processing time can be further reduced.

FIG. 10 shows an EOF structure 1001 when the reception count is added to the EOF. In Fiber Channel, EOF is represented by 4 bytes. this is,
This is for encoding as a special serial data sequence. However, after the parallel conversion, it can be represented by one byte. On the other hand, since the number of received data is about 2 kilobytes at the maximum, it can be represented by 3 bytes. Therefore, as shown in FIG. 10, the EOF code is written in the first byte of the 4 bytes, and the SOF to EOF is written in the remaining 3 bytes.
It is possible to add a reception count number. By using the selector 450 in the frame separation circuit 132 described with reference to FIG. 4, the reception count can be added to the EOF structure. As a result, it is possible to add the number of received data in the frame without changing the number of data in the frame.

Next, data transmission will be described with reference to FIGS. FIG. 11 is a block diagram showing a detailed configuration of the frame synthesis circuit 131 shown in FIG. The frame synthesizing circuit 131 includes a register 1100, a data number measuring unit 1110, a transmission state machine 1120,
It comprises a selector 1130 and a multi-stage buffer 1140.

A register 1100 is a header start address register 1101 for designating a header storage start address.
And a header end address register 1101 for specifying the end address of the header storage and a data length register 1103 for specifying the number of transmission data. The writing to the data length register 1103 is set to start the transmission, and when the writing to the data length register 1103 occurs, the transmission state machine 1120 is notified. Register 1100
Is set by the data transfer control unit 170 via the processor bus 160.

The data number measuring unit 1110 compares the counter value of the header number counter 1111 for counting the number of transmitted headers with the counter value of the header number counter 1111 and the value of the header end address 1102, and is transmitting the header to the transmission state machine 1120. A comparator 1112 for notifying that
Data number counter 11 for counting the number of transmitted data
13 is compared with the counter value of the data number counter 1113 and the value of the data length 1103, and the transmission state machine 1120
And a comparator 1114 for notifying that the data is being transmitted.

The selector 1130 responds to a selection control signal from the transmission state machine 1120 by
The data source to be output to the transmission control information memory 14
1 and the transmission data FIFO 142 are switched. As described above, the header and data can be combined and transmitted.

Next, the data transfer control unit 17 during data transmission
Operation 1 will be described with reference to the flowchart shown in FIG. To specify the area to be used in the transmission control information memory 141, the head address of the area is written into the header start address register 1101 (1201). The end address of the area is written into the header end address register 1102 (1202). Transmission is started by writing the number of data to be transmitted to the data length register 1103 (1203) (1204).

As described above, at the time of transmission, a frame can be transmitted using the header information stored in advance in the transmission control memory, so that the processing time can be reduced.

[0048]

The transmission buffer circuit is divided into a transmission control information memory for storing control information and a transmission data buffer for storing data transferred from the input / output bus. A frame synthesizing circuit for generating a frame from control information and data is provided, and expected control information is stored in advance in a transmission control information memory. Since only the fields that need to be changed are updated, the time for generating the control information of the frame can be reduced.

Further, since the dual-port memory is used as the transmission control information memory, the control information of the next transmission frame can be simultaneously generated during the frame transmission, and the generation time of the control information of the apparent frame can be reduced. Can be reduced. When data is received, transmission of an ACK frame for the received data and transfer of the received data to the input / output bus can be performed simultaneously.

The transmission control information memory is divided into a plurality of areas, and at the time of initialization after power-on, expected control information is stored in advance in the transmission control information memory. Since only the fields that need to be changed for each frame, such as the flow control information of the area, are updated, the time for generating the control information of the frame can be reduced.

Further, when data larger than the maximum data length of one frame is divided into a plurality of frames and transferred, the data of a plurality of frames received sequentially and sequentially is stored in the reception data buffer memory. However, since the data is successively transferred to the input / output bus by a single DMA transfer instruction, there is no need to issue a transfer instruction for each frame, and the processing amount and processing time can be reduced.

The receiving buffer for storing frames received from the serial interface is divided into a receiving control information buffer for storing control information and a receiving data buffer for storing data to be transferred to the input / output bus.
A frame separation circuit is provided in front of the receive buffer to separate the received frame into control information and data, so that control information analysis and data transfer to the input / output bus can be performed simultaneously. The processing time can be reduced.

Further, the frame separation circuit is provided with a counter for counting the number of received data, a selector for selecting and outputting a received buffer output and a counter value, and further adding the number of received data to the reception control information to control the reception. Since the data is stored in the information memory, even when a plurality of frames are received continuously, the data transfer control unit can recognize the number of received data by analyzing the reception control information.

When a FIFO memory is used as the transmission control information memory, the reception control information memory, and the reception data memory, the address generation becomes easy, so that the amount of hardware can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a data transfer control unit according to the present invention.

FIG. 2 is an explanatory diagram showing an example of a data frame structure according to the present invention.

FIG. 3 is an explanatory view showing an example of the structure of a frame header according to the present invention.

FIG. 4 is a block diagram illustrating a configuration example of a frame separation circuit according to the present invention.

FIG. 5 is an explanatory diagram of state transition showing an example of a reception state machine of the present invention.

FIG. 6 is an explanatory diagram showing an example of an address space of a transmission control information memory according to the present invention.

FIG. 7 is an explanatory diagram showing an example of control information stored in a transmission control information memory according to the present invention.

FIG. 8 is a flowchart showing an example of the operation of the data transfer control unit of the present invention.

FIG. 9 is a flowchart showing an example of the operation of the data transfer control unit of the present invention.

FIG. 10 is an explanatory view showing an example of the structure of an EOF of the present invention.

FIG. 11 is a block diagram illustrating an example of a frame synthesis circuit according to the present invention.

FIG. 12 is a flowchart showing an example of the operation of the data transfer control unit of the present invention.

FIG. 13 is a block diagram showing a conventional example of the operation of the data transfer control unit of the present invention.

[Explanation of symbols]

100: serial interface control device, 101: optical fiber cable, 102: other node, 103: input / output bus, 104: personal computer, 105: memory, 110: serial interface, 121: parallel-serial conversion circuit, 122: serial-parallel conversion circuit, 131: frame synthesis circuit, 132: frame separation circuit, 140: transmission buffer circuit, 141: transmission control information memory, 142
... Transmission data FIFO, 150 ... Reception buffer circuit, 1
51: reception control information FIFO, 152: reception data FI
FO.

Claims (10)

[Claims] 1. A serial interface controller for connecting a serial interface to an input / output bus and controlling data transfer, the serial interface controller comprising: a serial interface, a parallel-to-serial conversion circuit, a serial-to-parallel conversion circuit; A frame synthesizing circuit for synthesizing information and data; a transmission control information memory for storing frame control information to be transmitted; a transmission data memory for storing data to be transmitted; and the transmission control information memory and transmission used for controlling the transmission data memory A transmission buffer circuit having a control register; a frame separation circuit for separating a received frame into frame control information and data; a reception control information memory for storing received frame control information; and a reception for storing received data. Data memory and the above reception control information A reception buffer circuit having a memory and a reception control register used for controlling the reception data memory, a processor bus, a memory, an input / output bus control unit, and a CPU, and the transmission control information memory includes: A serial interface control device, wherein frame control information is stored in advance. 2. The frame separating circuit according to claim 1, wherein the frame separating circuit includes a multi-stage buffer for temporarily storing a received frame, an SOF as a control code indicating the start of the frame, and a control code indicating the end of the frame. A control code detector having a decoder for detecting EOF, a data number counter having a data number counter for measuring the number of received data, and a comparator for comparing the number of received data with the number of control information;
A selector for switching output to the reception buffer and a reception state machine are provided, and upon receiving control information after detecting SOF reception, generate a control signal for storing control information in a reception control information memory. A serial interface control device that generates a control signal for storing data in a reception data memory when receiving data, and stores a data counter number in a reception control information memory when receiving EOF. 3. The method of claim 2, wherein when the data number counter value is stored in the reception control information FIFO memory, an EOF identification code is stored in one byte of the received 4-byte length EOF, and the EOF identification code is stored in three bytes. Is a serial interface controller that stores the number of data counters. 4. The frame synthesizing circuit according to claim 1, wherein the frame synthesizing circuit includes a multi-stage buffer for temporarily storing a frame to be transmitted, and an address at which storage of a header as control information is started. A register group having a header start address register for storing, a header end address register for storing an address at which the header has been stored, a data length register for storing the number of data stored in the transmission data memory, and measurement of the number of transmitted headers. A comparator for comparing the value of the header number counter and the header end address with the header end address, a data number counter for measuring the number of transmitted data, and a comparator for comparing the value of the data number counter with the data length. A data number measurement unit having
A selector for switching the input from the transmission buffer circuit and a transmission state machine are provided, and the number of headers and the number of data counters start to be measured by writing the data length register, and the header ends from the header start address of the transmission control information memory first. Generate a control signal of the transmission control information memory for reading the frame start code and control information stored up to the address, and then generate a control signal of the transmission data memory for reading the data stored in the transmission data memory, Finally, a serial interface control device for generating a control signal for a transmission control information memory for reading a frame end code stored at an address subsequent to a header end address of the transmission control information memory. 5. The transmission control information memory according to claim 1, wherein said transmission control information memory is divided into a plurality of areas, and each area stores a frame start code, control information, and a frame end code together. Interface control method. 6. The setting of the frame start code, the control information, and the frame end code in the divided areas of the transmission control information memory is performed at the time of initialization, and at the time of frame transmission, only the portions that need to be corrected are reset. 6. The serial interface control method according to claim 5, wherein transmission is performed afterwards. 7. The data transfer control unit according to claim 1, wherein said data transfer control unit transmits data of a plurality of frames to be transmitted or received to / from an input / output bus. Serial interface control method to transfer data in batch. 8. The serial interface control device according to claim 1, wherein said transmission data memory, reception control information memory and reception data memory are FIFO memories. 9. The serial interface control device according to claim 1, wherein the transmission control information memory is a dual port memory. 10. The method of claim 1, 2, 3, 4, 5, 6, 7, 8
In 9 or 9, a serial interface control device, wherein the serial interface is a fiber channel.