JPH1049448A - Error correction mechanism for redundant memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a redundant memory of higher reliability by preventing the development to an unrecoverable error due to the accumulation of soft errors of a memory. SOLUTION: If a correctable error is detected while a memory 2 is read, a correction address/data buffer 6 holds the relevant address and data. The memory data on the address stored in the buffer 6 may possibly be developed into an uncorrectable error as long as the memory error is not corrected. Thereafter, if an uncorrectable error is detected out of the memory 2 in its read mode, it's checked whether the data that caused the uncorrectable error are stored in the buffer 6. If such data are stored in the buffer 6, the data are replied from the buffer 6. Thus, even the uncorrectable error can be recovered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a redundant memory as a fault-tolerant computer, and more particularly to a memory provided with an error correction mechanism.

[0002]

2. Description of the Related Art Conventionally, a fault-tolerant computer having a memory having such an error correction mechanism and having a redundant memory prevents an uncorrectable error from developing due to accumulation of soft errors in the memory beforehand and provides a more reliable system. There is a demand for realizing a highly reliable memory. It has been proposed that such a request be realized by a memory error check function started by a timer set at a predetermined time interval, as shown in, for example, JP-A-5-88990.

FIG. 6 is a block diagram showing an example of a conventional error correction mechanism of a redundant memory. This error correction mechanism receives a bus switch 130, a timer 150 in which a predetermined time interval is set, and a check request output from the timer 150 at predetermined time intervals.
A bus arbiter 160 that prohibits access to the duplicated first memory (RAM) 121 and second memory (RAM) 122, and is activated based on a check request from the timer 150. 2nd memory 122
, An address generator 170 for generating an address for sweeping the entire area, a parity check means 180 for performing a parity check on data read from the corresponding address in the first memory 121 and the second memory 122, and a parity check means If an error is detected at 180, the error correction means 190 writes correct data to the error area of the memory where the error has occurred. The parity check means 180 includes first and second memories 121, 1
The error correction means 190 comprises parity checkers 181 and 182 corresponding to the access CTL 14.
0, data retainer 191 and read modify CTL1
92.

Next, the operation will be described. The timer 150 outputs a request for checking data held in each memory at every set time. When this check request is output, the bus arbiter 160 prohibits the CPU unit 110 from accessing the memory. Further, the address generator 170 outputs an address for sweeping the entire area to each memory, and reads data held in the first memory 121 and the second memory 122. The read data are all checked by the parity check unit 180, and if an error is detected here, the error correction unit 190 writes correct data into the error area. Thereby, the first memory 121
And the data held in the second memory 122 are always maintained in a state corrected to correct data.

[0005]

However, the above mechanism has the following problems. That is, in the related art, since the contents of the memory are checked at each time interval set in the timer and the error is corrected, the accumulation of soft errors within the set time may cause an unrecoverable error. is there. In addition, as shown in FIG. 2 and FIG. 3, in a general fault-tolerant system, main functional units are duplicated for each replacement module in order to continue to operate even when a failed module is replaced. . In this memory, as shown in FIG. 6, when the memory is duplicated, the memory is logically quadrupled for one memory, and the memory inside the module is reduced due to the price problem. It often has an error correction function by ECC (Error Check & Correction) instead of duplexing. At this time, similarly to the conventional example, the error in the memory is periodically corrected by the timer, or the error is corrected during the refresh operation (rewrite after reading). However, in this case as well, there is a possibility that the error will develop into an unrecoverable error before correction.

The reason is that in the mechanism for correcting the memory error periodically by the timer 150 in FIG. 6, a 2-bit error or an error occurs at the same address of the duplicated memory within the time interval set by the timer. Because there is no mechanism to recover it.

On the other hand, it is conceivable to reduce the probability by shortening the set time of the timer. However, if the time interval set by the timer is too short, the performance is greatly reduced. Can not.

In the case where the memory is provided with an error correction function in the configuration shown in FIGS. 2 and 3, an error detected at the time of normal reading occurs only in one of the duplicated memories. Only one of the memories performs the error correction operation, so that the duplicated memories are out of synchronization.

Therefore, it is not possible to perform error correction writing when an error is detected during normal reading. Generally, an error is corrected by a refresh operation in which a rewrite operation is performed after reading. At the time of refresh operation, it is performed in synchronization with the duplicated memory,
When an error is detected by reading, after correcting the error, writing may be performed as a series of refresh operations. However, in the case of error correction at the time of such a refresh, there is a problem that an error that cannot be recovered may occur between refresh operations as in the case of the error correction by the timer.

SUMMARY OF THE INVENTION It is an object of the present invention to prevent a redundant memory from developing into an unrecoverable error due to accumulation of soft errors in the memory and to realize a more reliable redundant memory. is there.

[0011]

SUMMARY OF THE INVENTION An error correction mechanism according to the present invention, when a correctable error occurs in a redundant memory, corrects the uncorrectable error before the error is corrected in the memory. Prevent progress. More specifically, an error detection circuit (3 in FIG. 1) for detecting whether there is a correctable error and an uncorrectable error in the data read from the RAM (2 in FIG. 1) on the memory, When an error is detected by the error detection circuit, an error correction circuit (4 in FIG. 1) that corrects the error, an address register (5 in FIG. 1) that holds a read address of the RAM, and an error detection circuit can correct the error. When it is notified that an error has been detected, a corrected address / data buffer (6 in FIG. 1) for holding the error correction data from the error correction circuit and the RAM read address from the address register, An address comparison circuit (7 in FIG. 1) for comparing the current address with all the addresses held in the corrected address / data buffer; If there is a matching address in the path, even if an uncorrectable error is detected from the error detection circuit, a NOR circuit (8 in FIG. 1) and an uncorrectable error notification suppression circuit (8 in FIG. 11) and if there is an error in which the reply to the read cannot be corrected, the address comparison circuit selects the corrected address / data buffer data whose address matches, and if there is no uncorrectable error, the output of the error correction circuit is output. Correction data selection circuit (Figure 1
9 and 10).

[0012]

When an error that can be corrected is detected, the error corrected data and the read address of the data are held, so that the error correction error cannot be immediately written due to the synchronization problem of the redundant memory. Even if the error progresses to an uncorrectable error due to the progress of soft errors, etc., it is possible to recover by using the stored data, and it is possible to continue operating without causing a memory failure .

With this function, it is possible to prevent a memory failure due to the progress of a soft error or the like, and to continue to operate as a fault tolerant system with a redundant memory configuration. In a fault-tolerant system, reliability is important, and a memory failure in a state where a memory has failed and is not redundant causes an immediate system down, causing a serious problem. Therefore, it is possible to construct a more reliable fault-tolerant system by preventing a memory failure due to progress of a soft error or the like.

[0014]

Next, a preferred embodiment of the present invention will be described in detail with reference to FIGS. 1, 2 and 3. FIG. FIG.
2 or 3 shows a typical configuration of a fault-tolerant system including the CPU 1 and the memory 16 shown in FIG.
FIG. 2 shows another module in which CPUs 21a and 21b, memories 22a and 22b, and IOPs 21a and 23b are connected via buses 24a and 24b.
It is heavy. On the other hand, as shown in FIG. 3, the CPU and the memory are one module 31a, 31b and the buses 33a, 3b.
There is also a configuration in which IOPs 32a and 32b are connected via 3b.

The CPU 1 is a functional unit for performing arithmetic processing.
The memory 16 is a functional unit that stores program data. The memory 16 replies read data requested by the CPU 1 and stores data written by the CPU 1 in the RAM 2. The RAM 2 is a functional unit that actually stores program data in the memory 16. The error detection circuit 3 is R
This is a circuit for detecting whether there is a correctable error and an uncorrectable error in the data read from AM2. The error correction circuit 4 is a circuit for correcting an error when the error is detected by the error detection circuit 3.

The address register 5 stores the RAM in the CPU 1
2 is held when the address is read. The corrected address / data buffer 6 informs the correctable error notification line 13 that the correctable error has been detected by the error detection circuit 3.
, The data from the error correction circuit 4 and the address from the address register 5 are held. The address comparison circuit 7 is a circuit that compares the address held in the address register 5 with all the addresses held in the corrected address / data buffer 6. N
The OR circuit 8 is a circuit that issues an instruction to suppress notification of the detection of an uncorrectable error to the CPU 1 to the uncorrectable error suppression line 14 based on the comparison result of the address comparison circuit 7.

The correction data selection circuit 10 selects the data of the corrected address / data buffer 6 whose address matches in the address comparison circuit 7. The correction data selection circuit 9
When the error detection circuit 3 notifies that an uncorrectable error has been detected via the uncorrectable error notification line 12, the data from the correction data selection circuit 10 is selected, and the data from the error correction circuit 4 is otherwise selected. This is the circuit to be selected.

The uncorrectable error notification suppression circuit 11 detects an uncorrectable error from the uncorrectable error notification line 12 to the CPU 1 through the uncorrectable error notification line 15 when an instruction is given through the uncorrectable error suppression line 14. This is a circuit for suppressing a notification indicating that the notification has been made.

Next, the operation of the circuit of FIG. 1 will be described. The CPU 1 performs arithmetic processing and executes reading and writing with respect to the memory 16. Data to be read and written by the CPU 1 is stored in the RAM 2. The data read from the RAM 2 is checked by the error detection circuit 3 to determine whether there is a correctable error or an uncorrectable error. When an uncorrectable error is detected,
The uncorrectable error notification suppression circuit 11 and the correction data selection circuit 9 are notified via the uncorrectable error notification line 12.
Originally, when an uncorrectable error was detected, the memory in which the uncorrectable error was detected was disconnected from the service and caused to fail, and the other duplexed module was processed as shown in FIGS. To continue. The correctable error detected by the error detection circuit 3 is notified to the corrected address / data buffer 6 via a correctable error notification line 13.

The error correction circuit 4 corrects an error in the data read from the RAM 2 when the error detection circuit 3 detects a correctable error. The address register 5 stores an address when the CPU 1 reads the RAM 2. When the correction address / data buffer 6 is notified from the error detection circuit 3 that a correctable error has been detected via the correctable error notification line 13, the corrected address / data buffer 6 stores the address of the data having an error stored in the address register 5. , And the data in which the error is corrected by the error correction circuit 4 are stored in pairs.

The address comparison circuit 7 stores all the addresses of the data having a correctable error stored in the corrected address / data buffer 6 and the CPU 1
Is compared with the address of the address register 5 which holds the address from which is read. When the address is matched by the address comparison circuit 7, a correctable error is detected at that address in the RAM 2 during the previous read, indicating that the data at that address stored in the RAM 2 has a correctable error. .

In the data in which a previously correctable error has been detected, the error may further develop and become an uncorrectable error. When an uncorrectable error is detected, the memory 16 is originally disconnected from the service as a failure. However, in the system of FIG. 1, it is possible to recover since the correct data remains in the corrected address / data buffer 6. .

When the addresses are matched by the address comparing circuit 7, even if an uncorrectable error is detected, the correct data is stored in the corrected address / data buffer 6 and the error can be recovered. 8
Has been instructed to notify the uncorrectable error notification suppression circuit 11 through the uncorrectable error suppression line 14 to notify the CPU 1 from the error detection circuit 3 through the uncorrectable error notification line 12 that an uncorrectable error has been detected. Also issues an instruction not to notify the CPU 1 via the uncorrectable error notification line 15 that an uncorrectable error has been detected.

The correction data selection circuit 10 uses the data in the corrected address / data buffer 6 to generate an address comparison circuit 7
Select the data of the address that matches. This is because even if the error detection circuit 3 detects an uncorrectable error, the corrected address / data buffer 6 has correct data, and the error can be recovered by replying the data to the CPU 1. Means.

The correction data selection circuit 9 determines whether an uncorrectable error has been detected or not.
The output of the error correction circuit 4 is selected as usual if there is no uncorrectable error, and if an uncorrectable error has been detected, the corrected address /
In order to select correct data without errors stored in the data buffer 6, the output of the correction data selection circuit 10 is selected.

As described above, the RAM 2 of the memory 16
A correctable error occurs in the data stored in
Even if an uncorrectable error evolves before a timer or error correction during refresh as shown in the conventional example, an uncorrectable error can be maintained by retaining the address and data at which the correctable error occurred. It is possible to recover the data of the RAM 2 that has been developed.

Next, an embodiment of the present invention will be described with reference to FIGS. 1, 4 and 5. FIG. FIG. 4 shows a first embodiment of the error detection circuit 3 and the error correction circuit 4 in the memory 16 having the functions of error detection and error correction by ECC.

FIG. 5 shows a RAM as in the conventional example of FIG.
This is a second embodiment of the error detection circuit 3 and the error correction circuit 4 when 2 is duplicated.

The CPU 1 performs arithmetic processing and executes reading and writing with respect to the memory 16. Data to be read and written by the CPU 1 is stored in the RAM 2 in the memory 16. An embodiment of the error detection circuit 3 and the error correction circuit 4 which are different between a case where the RAM 2 is duplicated and a case where the RAM 2 is not duplicated will be described.

FIG. 4 shows an embodiment in which the RAM 2 is not duplicated and error detection and correction are performed by adding an ECC code.
As the ECC code, a code that can correct a 1-bit error and can detect a 2-bit error is used.
When constructed as a fault-tolerant system, memory modules are duplicated as shown in FIGS.

The read data output from the RAM 2 is input, and the error detector 41 checks whether there is a correctable error. The error detection unit 41 detects whether there is an error that can be corrected by taking the exclusive OR of all data bits and all ECC codes. Error detector 4
The result of 1 is output to the correctable error notification line 13 and notified to the corrected address / data buffer 6. The syndrome generation circuit 43 reads the read data from the RAM 2 and the EC according to a predetermined syndrome generation pattern.
Generate a syndrome from the C code. The syndrome when there is no error is usually all 0s.

The generated syndrome is decoded by the syndrome decoder 44, and a decoding result having the same number of bits as the read data in which only the bit corresponding to the data in which the error has occurred becomes 1 is obtained. As in the case of the syndrome, the result is all 0 when there is no error. An error correction unit 45 that takes an exclusive OR of the result of the syndrome decoder 44 and each bit of the read data from the RAM 2
As a result, a correctable 1-bit error is corrected. The data whose error has been corrected is output to the corrected address / data buffer 6 and the corrected data selection circuit 9.

The uncorrectable error detection circuit 42 detects whether there is an uncorrectable error of two or more bits.
When the result of the syndrome generation circuit 43 is not all 0 even though no error is detected by the error detection unit 41, and when the result of the syndrome generation circuit 43 is an unspecified pattern, an uncorrectable error It is judged as. The detected uncorrectable error is output to the correction data selection circuit 9 and the uncorrectable error notification suppression circuit 11 through the uncorrectable error notification line 12.

The RAM 2 is duplicated, and the duplicated R
FIG. 5 shows an embodiment in which error detection and correction are performed based on data from AMa and RAMb. When constructed as a fault-tolerant system, as shown in FIGS. 2 and 3,
The modules of the memory are further duplicated.

The parity checkers 51 and 53 receive the read data from one of each of the duplicated RAMa and RAMb and receive a parity error, that is, 1
Check for bit errors. The parity checkers 51 and 53 alone cannot detect that even-numbered bits cause an error.
The two input data from AMa and RAMb are compared. Here, when a mismatch occurs, an error occurs.

The correctable error detection circuit 54 performs an exclusive OR operation on the results of the parity checkers 51 and 53, and detects a correctable error when one of the parity checkers detects an error. The detection of the correctable error is notified to the corrected address / data buffer 6 through the correctable error notification line 13. If an error is detected by both parity checkers, it is a non-recoverable double error and an uncorrectable error.

The uncorrectable error detection circuit 55 receives the results of the parity checkers 51 and 53 and the comparison circuit 52. If the comparison circuit 52 detects a mismatch even though no error has been detected by both parity checkers. If an error is detected by one or both of the parity checkers, an uncorrectable error is detected. When an uncorrectable error is detected, the error is notified to the corrected data selection circuit 9 and the uncorrectable error notification suppression circuit 11 through the uncorrectable error notification line 12. The error correction circuit 4 is composed of a selection circuit 56. The selection circuit 56 uses the results of the parity checkers 51 and 53 to determine whether the RAM has detected no error.
2 is selected.

When an uncorrectable error is detected by the error detection circuit 3, recovery cannot be normally performed.
The memory 16 in which the uncorrectable error is detected is disconnected from the service. However, in a fault-tolerant system as shown in FIGS. 2 and 3, the other memory module that has been duplicated continues processing. However, if only one of the memory modules is operating, the system immediately shuts down when the operating memory module fails, which is a fatal problem as a fault-tolerant system with the proposition of reliability.

When an error that can be corrected is detected by the error detection circuit 3, it is desirable to correct the error immediately. However, when writing the data with the error corrected to the RAM 2, the RAM 2 is duplicated. 2 corrects an error between the duplicated RAMa and RAMb and the synchronization between the duplicated memory modules as shown in FIGS. 2 and 3 even when the RAM 2 is not duplicated. Cannot be performed on the RAM2.

Therefore, in order not to shift the synchronization, error correction writing is periodically performed by a timer, or correction writing is performed during a refresh operation in which writing is performed periodically in synchronization. However, even in this case, since the error correction is not performed immediately, there is a possibility that the correctable error may progress to an uncorrectable error. A method for avoiding the fear is the following mechanism.

Returning to FIG. 1, the address register 5
The address when U1 reads RAM2 is stored.
The correction address / data buffer 6 is provided in the error detection circuit 3
Is notified via the correctable error notification line 13 that a correctable error has been detected, the address register 5
The address of the data in which the error has occurred and the data whose error has been corrected by the error correction circuit 4 are stored in pairs. As a result, even if the data at that address evolves into an uncorrectable error before the error correction write to the RAM 2 is executed, the correct data is stored in the correction address / data buffer 6 and recovery is possible. become.

The address comparing circuit 7 stores all the addresses of the data in which the correctable error is stored in the corrected address / data buffer 6 and the CPU 1
Is compared with the address of the address register 5 which holds the address from which is read. When the address is matched by the address comparison circuit 7, a correctable error is detected at that address in the RAM 2 during the previous read, indicating that the data at that address stored in the RAM 2 has a correctable error. .

If the address comparison circuit 7 matches the address, correct data is stored in the corrected address / data buffer 6 even if an uncorrectable error is detected in the read data from the RAM 2 at that address. Since the error can be recovered, the NOR circuit 8 detects an uncorrectable error to the uncorrectable error notification suppression circuit 11 via the uncorrectable error suppression line 14 and the error correction circuit 3 to the CPU 1 via the uncorrectable error notification line 12. Even if there is an instruction to notify that the error has been detected, an instruction is issued via the uncorrectable error notification line 15 so that the CPU 1 is not notified that an uncorrectable error has been detected.

The correction data selection circuit 10 uses the data in the corrected address / data buffer 6 to generate an address comparison circuit 7
Select the data of the address that matches. This is because even if the error detection circuit 3 detects an uncorrectable error, the correct address / data buffer 6 has the correct data, and the data can be replied to the CPU 1 to enable the error recovery. . This CPU
The reply operation to 1 is performed by selecting the output of the correction data selection circuit 10 when the error detection circuit 3 notifies the correction data selection circuit 9 of an uncorrectable error via the non-correctable error notification line 12. Be executed. Therefore,
The correction data selection circuit 9 selects the output of the error correction circuit 4 as usual if there is no uncorrectable error, and if the uncorrectable error is detected, the error stored in the corrected address / data buffer 6 In order to select correct data without the error, the output of the correction data selection circuit 10 is selected.

As described above, the RAM 2 of the memory 16
A correctable error occurs in the data stored in
Even if an uncorrectable error has progressed before the error correction performed during a timer or refresh as shown in the conventional example, an uncorrectable error can be maintained by retaining the address and data where the correctable error occurred. It is possible to recover the data of the RAM 2 that has been developed.

[0046]

According to the present invention, it is possible to prevent the occurrence of an unrecoverable error due to accumulation of soft errors in a redundant memory, thereby realizing a more reliable redundant memory. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a redundant memory to which an error correction mechanism of the present invention is applied.

FIG. 2 is a diagram illustrating an example of a fault-tolerant system of a redundant memory.

FIG. 3 is a diagram showing another example of a fault-tolerant system of a redundant memory.

FIG. 4 is a diagram illustrating a first example of the error detection circuit and the error correction circuit of FIG. 1;
It is a figure which shows the Example of.

FIG. 5 shows a second example of the error detection circuit and the error correction circuit of FIG.
It is a figure which shows the Example of.

FIG. 6 is a block diagram showing an example of a redundant memory to which a conventional error correction mechanism is applied.

[Explanation of symbols]

 Reference Signs List 1 CPU 2 RAM 3 Error detection circuit 4 Error correction circuit 5 Address register 6 Corrected address / data buffer 7 Address comparison circuit 8 NOR circuit 9, 10 Correction data selection circuit 11 Uncorrectable error notification suppression circuit 12 Uncorrectable error notification line 13 Correctable error notification line 14 Uncorrectable error suppression line 15 Uncorrectable error notification line 16 Memory

Claims (4)

[Claims] In a system provided with a redundant storage unit that operates in synchronization to improve fault tolerance, a correctable error and an uncorrectable error occur in data read from the storage unit. An error detection circuit that detects whether or not there is an error, an error correction circuit that corrects an error that can be corrected when the error detection circuit detects the error, an address register that holds a read address for the storage unit, A correction address / data buffer for holding error correction data from the error correction circuit and a read address of the storage unit from the address register when notified that a correctable error has been detected by the error detection circuit; The address held in the address register and all the addresses held in the corrected address / data buffer An address comparing circuit for comparing the addresses, and an uncorrectable error notification suppressing means for suppressing a notification even if an uncorrectable error is detected from the error detecting circuit when there is a matching address in the address comparing circuit. When the error detection circuit detects an uncorrectable error, the address comparison circuit selects the corrected address / data buffer data whose address matches, and when there is no uncorrectable error, the error correction is performed. An error correction mechanism for a redundant memory, comprising: a correction data selecting means for selecting an output of the circuit. 2. The error correction mechanism of a redundant memory according to claim 1, wherein said uncorrectable error notification suppressing means notifies that an uncorrectable error has been detected from a comparison result of said address comparison circuit. A NOR circuit for issuing an instruction to suppress the error, and an instruction from the NOR circuit detects an uncorrectable error even when a signal indicating that an uncorrectable error is detected is received from the error detection circuit. An error correction mechanism for a redundant memory, comprising: an uncorrectable error notification suppression circuit for suppressing a notification indicating that the error has occurred. 3. The error correction mechanism for a redundant memory according to claim 1, wherein said error detection circuit is a circuit for performing an error detection by adding an ECC code, and wherein said error correction circuit has a predetermined syndrome. A syndrome generation circuit that generates a syndrome from the read data from the storage unit and the ECC code according to the generation pattern of: a syndrome decoder that decodes the generated syndrome; a result of the syndrome decoder and read data from the storage unit And an error correction unit that corrects a correctable error by taking an exclusive OR of each bit of the error correction circuit. The error detection circuit performs an exclusive OR of all data bits and all ECC codes to perform correction. An error detector for detecting whether there is a possible error, and an output of the error detector. The error correction mechanism of the redundant memory, characterized in that it consists of a uncorrectable error detection circuit for detecting whether the uncorrectable error from said generated syndrome. 4. The error correction mechanism for a redundant memory according to claim 1, wherein said storage unit is duplicated, and said error detection circuit is provided from each of said duplicated storage units. Two parity checkers for inputting read data and checking for a parity error; a comparison circuit for comparing two input data from the storage unit which is duplicated; and a result of the two parity checkers Is exclusive ORed, and a correctable error is detected if an error is detected by one of the parity checkers, and an uncorrectable error is detected if an error is detected by both parity checkers A correctable error detection circuit, receiving the results of the two parity checkers and the comparison circuit, and detecting an error in both parity checkers; An uncorrectable error detection circuit that detects an uncorrectable error when a mismatch is detected in the comparison circuit despite the absence of the error or when an error is detected in both parity checkers. The error correction mechanism for a redundant memory, wherein the correction circuit includes a selection circuit that selects read data of the storage unit on the side where no error is detected, based on the results of the two parity checkers.