JPH10340953A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, wherein tolerance to position deviation in contact hole formation is high and connection between diffusion layers or wiring layers is enabled with high reliability. SOLUTION: This device has a first wiring layer 5 formed on a semiconductor substrate 1 via a first interlayer insulating film 2, and a second wiring layer 8 which is formed on the first wiring layer 5 via a second interlayer insulating film 4 and connected with the first wiring layer 5, via a contact hole 7 formed in a specified region of the second interlayer insulating film 4. In this case, an etching stopper layer is formed on a lower layer of the first wiring layer 5 and immediately below the forming region of the contact hole 7, interposing an insulating layer. The etching stopper layer is constituted of a conductor film formed in a specified pattern shape.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a structure of a wiring layer and a structure of a contact hole for connecting the wiring layers.

[0002]

2. Description of the Related Art The miniaturization and higher density of the structure of semiconductor devices are still being vigorously pursued. For miniaturization, a semiconductor element formed with a size of 0.18 μm is currently used, and a semiconductor device such as a 1-bit DRAM using this size as a design standard has been developed.

[0003] Regarding the high density, a method of three-dimensional semiconductor elements as well as a two-dimensional high density by miniaturization has been studied, and some of them have already been put to practical use. In fact, along with the multi-layered structure of the electrode wiring or the multi-layered structure of the diffusion layer, it is now practically used as a passive element such as a capacitor among semiconductor elements, and is embodied in a semiconductor device at a product level. At present, this three-dimensional structure is being studied at the development level for active elements such as transistors.

As described above, miniaturization and three-dimensionalization are the most effective methods for achieving high performance or multi-functionality by increasing the integration and operating speed of semiconductor devices, and are essential for the future manufacture of semiconductor devices. Has become.

On the other hand, with such miniaturization and three-dimensionalization, it is essential to improve mask alignment accuracy in a photolithography process. However, a reduction projection exposure apparatus (hereinafter, referred to as a stepper) currently used in a photolithography process has a limitation in improving the mask alignment accuracy. In order to make such a semiconductor device three-dimensional,
Particularly, the flatness of the interlayer insulating film between the diffusion layer and the wiring or between the multilayer wirings is deteriorated. This deterioration in flatness is also a factor that hinders an improvement in the alignment accuracy between the wiring layer and the contact hole.

A conventional method for forming this contact hole will be described with reference to FIG. FIG. 4 is a schematic cross-sectional view illustrating a conventional method for forming such a contact hole.

[0007] As shown in FIG.
For example, a first interlayer insulating film 102 is formed on the substrate 01.
Then, a first wiring layer 103 is formed in a predetermined region of the first interlayer insulating film 102. Here, such a first wiring layer 103 is formed by processing a metal thin film for wiring such as an aluminum metal film by a photolithography technique and a dry etching technique. Next, the first wiring layer 103 is covered with a second interlayer insulating film 104. Then, a contact hole 105 reaching a first wiring layer in a predetermined region of the second interlayer insulating film 104 is provided by a photolithography technique and a dry etching technique.
Note that the first wiring layer 103 and the contact holes 1 are
05 is aligned.

Then, a second wiring layer 106 is formed in the same manner as the formation of the first wiring layer 103. The second wiring layer 106 is connected to the first wiring layer 103 through the contact hole 105.

However, when the above wiring layer is miniaturized,
4B tends to occur. That is, if the alignment accuracy is not good in the mask alignment by the stepper in the photolithography process described with reference to FIG. 4A, the mask pattern of the contact hole 105 shifts with respect to the pattern of the first wiring layer 103. And
In a dry etching step for forming the contact hole 105, after the dry etching of the second interlayer insulating film 104, the first portion is shifted from the portion shifted from the first wiring layer.
Is dry-etched. In the worst case, a contact hole 105a reaching the surface of the silicon substrate 101 is formed. Therefore, the second wiring layer 106 is connected to the silicon substrate 101 together with the first wiring layer 103 and short-circuited (short-circuited). And the semiconductor device formed in this way becomes a defective product.

Japanese Patent Laid-Open No. Hei 4-26 discloses a method for preventing a short circuit in a wiring layer due to such a positional displacement of a contact hole.
No. 0328. Therefore, this conventional technique will be described with reference to FIG. FIG. 5 is a sectional view showing the manufacturing method in the order of steps.

As shown in FIG. 5A, a diffusion layer 202 is formed on a silicon wafer 201. Then, a gate SiO ₂ film 203 and a patterned poly-Si gate electrode 204 are formed close to the gate SiO ₂ film 203. Further, an SiO ₂ film 205 is formed on the poly-Si gate electrode 204, and a first interlayer insulating film 206 is deposited on the entire surface.
Then, a poly-Si film 208 having a hole 207 for a contact hole is provided on the first interlayer insulating film 206.

Next, as shown in FIG.
A second interlayer insulating film 209 is deposited to cover the film 208. Then, as shown in FIG. 5C, dry etching is performed using the photoresist film 210 as a mask. Here, a second contact hole 211 is formed in the second interlayer insulating film 209 on the poly-Si film 208, and the first contact hole 211 reaches the diffusion layer 202 through the hole 207 in the first interlayer insulating film 206.
Contact hole 212 is formed.

Next, as shown in FIG. 5D, a first contact hole 212 and a second contact hole 211 are formed.
Then, an Al film is embedded as an electrode film, and an Al electrode 213 connected to the diffusion layer 202 is formed.

In this conventional technique, the poly-Si film 208 becomes an etching stopper layer in forming a contact hole. For this reason, even if misalignment occurs in the process of forming the photoresist film 210, the poly-Si film 208 serves as an etching mask, and no contact hole deviating from the pattern of the diffusion layer 202 is formed.

[0015]

However, the technique described in Japanese Patent Application Laid-Open No. 4-260328 has the following three problems. That is, the first problem is that it is impossible to form a contact hole in a predetermined region when a positional shift occurs during the formation of the poly-Si film 208 as described above. That is, the diffusion layer 2
If there is a misalignment between the mask 02 and the hole 207, a misalignment occurs between the diffusion layer 202 and the first contact hole 212. The second problem is that the presence of the poly-Si film 208 and the second interlayer insulating film makes the contact hole deeper than necessary. A third problem is that the number of manufacturing steps is greatly increased. In this case, two photolithography steps are required to form one contact hole. Further, the formation of the poly-Si film 208, the dry etching, and the formation of the second interlayer insulating film 209 are additionally required.

An object of the present invention is to provide a semiconductor device which is resistant to positional deviation in the formation of a contact hole and can perform connection between a diffusion layer or a wiring layer with high reliability.

[0017]

For this purpose, in the semiconductor device of the present invention, a first wiring layer provided on a semiconductor substrate via a first interlayer insulating film, and a first wiring layer provided on the first wiring layer are provided. Second
A second wiring layer provided through a first insulating layer and connected to the first wiring layer through a contact hole provided in a predetermined region of the second interlayer insulating film. An etching stopper layer is formed directly below the contact hole formation region and below the first wiring layer via an insulating layer.

Here, the etching stopper layer is formed of a conductive film formed in a predetermined pattern. Alternatively, the etching stopper layer is formed of a dummy wiring layer. Further, the etching stopper layer and the first wiring layer are electrically connected through a contact hole different from the contact hole formed in the insulating layer.

Here, when the contact hole is displaced during the formation of the contact hole and deviates from the pattern of the first wiring layer, the formation of the contact hole is stopped by the etching stopper layer provided below the first wiring layer. I will be. For this reason, there is no problem as described in the prior art.

[0020]

Next, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional view of a multilayer wiring portion of a semiconductor device according to the present invention. As shown in FIG. 1, a first interlayer insulating film 2 is formed on a silicon substrate 1.
Here, the first interlayer insulating film 2 is formed by chemical vapor deposition (CV).
This is a silicon oxide film having a thickness of about 300 nm deposited by the method D). Then, a polycrystalline silicon film 3 is formed on the first interlayer insulating film 2 as an etching stopper layer. Here, the polycrystalline silicon film 3 is formed as a thin film having a thickness of about 100 nm deposited by the CVD method, and its pattern is formed in a strip shape.

Then, a second interlayer insulating film 4 is formed so as to cover the polycrystalline silicon film 3. Here, the second
Is 200 nm in thickness deposited by the CVD method.
About a silicon oxide film. This second interlayer insulating film 4
A WSi wiring 5 is formed thereon as a first wiring layer. Here, the WSi wiring 5 is formed of a tungsten silicide thin film having a thickness of 100 nm.

Then, the WSi wiring 5 is covered with a film thickness of 300.
A third interlayer insulating film 6 of about nm is formed, and a contact hole 7 is formed in the third interlayer insulating film 6. Here, even if a misalignment of the mask occurs in the photolithography process for forming the contact hole 7, the strip-shaped polycrystalline silicon film 3 serves as an etching stopper and the contact hole is formed in the first interlayer insulating film. There is no.
However, a contact hole is formed in the second interlayer insulating film 4.

Further, an Al wiring 8 is formed as a second wiring layer. Here, the Al wiring 8 has a thickness of 700 nm.
It is a thin aluminum thin film. Then, the Al wiring 8 is connected to the WSi wiring 5 through the contact hole 7. When the mask is misaligned as described above, the Al wiring 8 is connected to the polycrystalline silicon film 3 but is not connected to the silicon substrate 1. Here, since the polycrystalline silicon film 3 is not connected at all, no inconvenience occurs.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a sectional view of a multilayer wiring portion of the semiconductor device of the present invention. As shown in FIG. 2, a first interlayer insulating film 2 is formed on a silicon substrate 1 as in the first embodiment. Here, the first interlayer insulating film 2 is made of C
This is a silicon oxide film having a thickness of about 500 nm deposited by the VD method. Then, a polycrystalline silicon film 3 a is formed on first interlayer insulating film 2. Here, the polycrystalline silicon film 3a is formed as a thin film having a thickness of about 200 nm deposited by the CVD method, and its pattern is formed in a strip shape. The polycrystalline silicon film 3a is doped with high-concentration phosphorus impurities to form a conductor film.

Then, a second interlayer insulating film 4 is formed to cover the polycrystalline silicon film 3a. Here, the second interlayer insulating film 4 has a thickness of 50 nm deposited by the CVD method.
About a silicon oxide film. Further, a preliminary contact hole 9 is formed in the second interlayer insulating film 4. On the second interlayer insulating film 4, a WSi wiring 5 is formed as a first wiring layer so as to be connected to the polycrystalline silicon film 3a. In the same layer, WSi
The wiring 5a is formed. Here, the WSi wiring 5 or 5a is formed of a tungsten silicide thin film having a thickness of 100 nm.

Then, a third interlayer insulating film 6 is formed to cover WSi wirings 5 and 5a, and contact holes 7 are formed in third interlayer insulating film 6. Here, as in the first embodiment, even if a mask alignment shift occurs in the photolithography process for forming the contact hole 7, the strip-shaped polycrystalline silicon film 3a serves as an etching stopper, No contact hole is formed in the interlayer insulating film 2. However, the second interlayer insulating film 4
Is formed with a contact hole.

Further, an Al wiring 8 is formed as a second wiring layer. Here, the Al wiring 8 has a thickness of 700 nm.
It is a thin aluminum thin film. Then, the Al wiring 8 is connected to the WSi wiring 5 through the contact hole 7. In addition, when there is such a positional deviation, the Al wiring 8 is connected to the polycrystalline silicon film 3a, but is not connected to the silicon substrate 1.

Here, the polycrystalline silicon film 3a is connected to a WSi wiring 5, which is a first wiring layer. Moreover, the polycrystalline silicon film 3a is a conductor film. As shown in FIG. 2, the position of the contact hole is shifted and Al
Even if the contact area between the wiring 8 and the WSi wiring 5 through the contact hole 7 is reduced, the Al wiring 8 is connected to the WSi wiring 5 through the polycrystalline silicon film 3a.
The connection resistance between the l wiring 8 and the WSi wiring 5 does not increase.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view of a multilayer wiring portion of the semiconductor device of the present invention. As shown in FIG. 3, an element isolation insulating film 10 is selectively formed on a silicon substrate 1.
Then, the gate insulating film 1 is formed in another region on the silicon substrate 1.
1 is formed, and a gate electrode 1 is formed on the gate insulating film 11.
2 are formed. A dummy gate electrode 12a is formed as an etching stopper layer on the element isolation insulating film 10 and in the same layer as the gate electrode 12. Further, a diffusion layer 13 serving as a source / drain region of the MOS transistor is formed. Here, the gate electrode 1
2 and the dummy gate electrode 12a are formed of a low-resistance conductive film such as a tungsten polycide film.

The layers above this are the same as those described in the first embodiment. That is, the second interlayer insulating film 4 is formed to cover the gate electrode 12 and the dummy gate electrode 12a. Here, the second interlayer insulating film 4 is C
This is a silicon oxide film having a thickness of about 500 nm deposited by the VD method. On the second interlayer insulating film 4, a WSi wiring 5 is formed as a first wiring layer. Here, the WSi wiring 5 is formed of a tungsten silicide thin film having a thickness of 100 nm.

Then, the WSi wiring 5 is covered with a film thickness of 500
A third interlayer insulating film 6 of about nm is formed, and a contact hole 7 is formed in the third interlayer insulating film 6. Here, even if a mask misalignment occurs in a photolithography process for forming the contact hole 7, the dummy gate electrode 12a serves as an etching stopper and a contact hole is not formed in the element isolation insulating film 10.

Further, an Al wiring 8 is formed as a second wiring layer. Here, the Al wiring 8 has a thickness of 1000 n.
m aluminum thin film. Then, the Al wiring 8 is connected to the WSi wiring 5 through the contact hole 7. In addition, if there is the above-mentioned misalignment, the Al wiring 8 is connected to the dummy gate electrode 12a, but is not connected to the silicon substrate 1. Here, the dummy gate electrode 12a
Since there is no other connection at all, there is no inconvenience.

[0033]

According to the semiconductor device of the present invention, a first wiring layer provided on a semiconductor substrate via a first interlayer insulating film, and a second interlayer insulating film provided on the first wiring layer. And a second wiring layer connected to the first wiring layer through a contact hole provided in a predetermined region of the second interlayer insulating film. An etching stopper layer is formed immediately below the formation region and below the first wiring layer via an insulating layer. Here, the etching stopper layer is formed of a conductor film formed in a predetermined pattern shape.

As described above, even if a mask is misaligned between the contact hole and the first wiring layer in the mask alignment in the photolithography process, the lower interlayer insulating film is formed in the dry etching process for forming the contact hole. Is not etched. This is because the etching stopper layer prevents the progress of the etching.

In the present invention, the thickness of the insulating layer between the etching stopper layer and the first wiring layer can be reduced. Therefore, the contact hole does not become deeper than necessary.

In the present invention, the etching stopper layer can be constituted by a dummy wiring layer formed below the first wiring layer like a dummy gate electrode. For this reason, the manufacturing process of the semiconductor device does not increase as in the related art.

As described above, according to the present invention, the positional deviation from the wiring layer in the formation of the contact hole becomes very strong,
The connection between the diffusion layer or the wiring layer can be performed with high reliability by a simple method.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a multilayer wiring section for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a multilayer wiring section for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a multilayer wiring section for explaining a third embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view for explaining a conventional technique.

FIG. 5 is a cross-sectional view illustrating a related art in the order of manufacturing steps.

[Explanation of symbols]

1,101 silicon substrate 2,102,206 first interlayer insulating film 3,3a polycrystalline silicon film 4,104,209 second interlayer insulating film 5,5a WSi wiring 6 third interlayer insulating film 7,105, 105a Contact hole 8 Al wiring 9 Preliminary contact hole 10 Element isolation insulating film 11 Gate insulating film 12 Gate electrode 12a Dummy gate electrode 13,202 Diffusion layer 103 First wiring layer 106 Second wiring layer 201 Silicon wafer 203 Gate SiO ₂ Film 204 poly-Si gate electrode 205 SiO ₂ film 207 hole 208 poly-Si film 210 photoresist film 211 second contact hole 212 first contact hole 213 Al electrode

Claims (4)

[Claims] A first wiring layer provided on a semiconductor substrate via a first interlayer insulating film; a first wiring layer provided on the first wiring layer via a second interlayer insulating film; A semiconductor device having a second wiring layer connected to the first wiring layer through a contact hole provided in a predetermined region of the second interlayer insulating film; A semiconductor device, wherein an etching stopper layer is formed below the first wiring layer via an insulating layer. 2. The semiconductor device according to claim 1, wherein said etching stopper layer is formed of a conductive film formed in a predetermined pattern. 3. The semiconductor device according to claim 2, wherein said etching stopper layer is formed of a dummy wiring layer. 4. The semiconductor device according to claim 2, wherein the etching stopper layer and the first wiring layer are electrically connected through a contact hole different from the contact hole formed in the insulating layer. Alternatively, the semiconductor device according to claim 3.