JPH10321866A - Thin film transistor and its manufacture - Google Patents
Thin film transistor and its manufactureInfo
- Publication number
- JPH10321866A JPH10321866A JP10008732A JP873298A JPH10321866A JP H10321866 A JPH10321866 A JP H10321866A JP 10008732 A JP10008732 A JP 10008732A JP 873298 A JP873298 A JP 873298A JP H10321866 A JPH10321866 A JP H10321866A
- Authority
- JP
- Japan
- Prior art keywords
- active layer
- area
- gate electrode
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000010409 thin film Substances 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000010408 film Substances 0.000 claims description 27
- 238000005468 ion implantation Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 22
- 229920005591 polysilicon Polymers 0.000 abstract description 16
- 150000002500 ions Chemical class 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、薄膜トランジスタ
及びその製造方法に係るもので、詳しくは、オン／オフ
電流比が増加するように改善された薄膜トランジスタ及
びその製造方法に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly, to a thin film transistor improved so as to increase an on / off current ratio and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】通常、トップゲート（top gate）型多結
晶シリコン（polycrystalline- silicon）薄膜トランジ
スタの製造方法においては、図１１に示すように、基板
１１上に絶縁層の第１酸化膜１２を形成し、該第１酸化
膜１２上に化学的気相蒸着法を用いてポリシリコン層１
３を形成した後、該ポリシリコン層１３上に再び絶縁層
の第２酸化膜１４を形成する。2. Description of the Related Art Generally, in a method of manufacturing a top gate type polycrystalline silicon thin film transistor, a first oxide film 12 as an insulating layer is formed on a substrate 11 as shown in FIG. Then, the polysilicon layer 1 is formed on the first oxide film 12 by using a chemical vapor deposition method.
After the formation of No. 3, a second oxide film 14 of an insulating layer is formed on the polysilicon layer 13 again.
【０００３】次いで、マスク（図示されず）を用いてソ
ース／ドレインを形成すべき部分の前記ポリシリコン層
１３の表面が露出されるように前記第２酸化膜１４を選
択的に食刻し、該第２酸化膜１４上にゲート電極１５を
形成した後、前記表面の露出されたポリシリコン層１３
内にホウ素Ｂ又はＰイオンの不純物を注入してソース／
ドレイン領域１６、１７を形成する。次いで、該ソース
／ドレイン領域１６、１７に夫々電気的にコンタクトさ
れるソース／ドレイン電極１８、１９を形成して、トッ
プゲート型多結晶シリコン薄膜トランジスタの製造工程
を終了していた。Then, the second oxide film 14 is selectively etched by using a mask (not shown) so that the surface of the polysilicon layer 13 where the source / drain is to be formed is exposed, After a gate electrode 15 is formed on the second oxide film 14, the exposed polysilicon layer 13 is exposed.
Implanted with boron B or P ion impurities into the source /
Drain regions 16 and 17 are formed. Next, source / drain electrodes 18 and 19 electrically connected to the source / drain regions 16 and 17, respectively, were formed, and the manufacturing process of the top gate type polycrystalline silicon thin film transistor was completed.
【０００４】このようなトップゲート型多結晶シリコン
薄膜トランジスタは、前記ゲート電極１５にしきい電圧
よりも高い電圧が印加された状態で、ドレイン電極１７
の電圧をソース電極１６の電圧よりも高く印加すると、
電子がソース１６からチャンネル領域を経てドレイン１
７に流れ込んで駆動電流が流れる。しかし、上記トップ
ゲート型多結晶シリコン薄膜トランジスタは、ゲートに
電圧を印加してチャンネルを形成するとき、ポリシリコ
ン内の結晶粒界（grainboundry ）に形成される電位障
壁によりキャリヤの移動度が低下するため、ターンオン
時に前記電位障壁により駆動電流が大いに減少し、ドレ
イン電流のオン／オフ電流比が減少されて変則的な漏洩
電流が発生するという欠点があった。In such a top-gate type polycrystalline silicon thin film transistor, a drain electrode 17 is applied while a voltage higher than a threshold voltage is applied to the gate electrode 15.
Is applied higher than the voltage of the source electrode 16,
Electrons flow from the source 16 through the channel region to the drain 1
7, and a drive current flows. However, in the top gate type polycrystalline silicon thin film transistor, when a voltage is applied to the gate to form a channel, the mobility of carriers is reduced due to a potential barrier formed at a grain boundary in polysilicon. At the time of turn-on, the driving current is greatly reduced due to the potential barrier, and the on / off current ratio of the drain current is reduced, thereby causing an irregular leakage current.
【０００５】このような問題点を解決するため、オフセ
ット領域を形成して変則的な漏洩電流を減少させてオン
／オフ電流比を増大し得る薄膜トランジスタが文献（IE
EEElectron Device Letters VOL 9. No1. January 1988
（名称：Characteristicof effect structure polycuy
stalline silicon... ）に記載されている。即ち、従来
オフセット領域を有した薄膜トランジスタの製造方法に
おいては、図１２に示すように、基板２１上にＬＰＣＶ
Ｄ（lower pressure chemicalvapor deposition ）
法によりポリシリコン膜２２を蒸着し、形成されたオフ
セット領域２３ａ，２３ｂ内に低濃度の燐イオンを注入
した後、形成されたソース／ドレイン領域２４ａ．２４
ｂ内に高濃度の燐イオンを注入する。In order to solve such a problem, a thin film transistor capable of forming an offset region to reduce an irregular leakage current and increase an on / off current ratio has been disclosed in the literature (IE).
EEElectron Device Letters VOL 9. No1. January 1988
(Name: Characteristicof effect structure polycuy
stalline silicon ...). That is, in the conventional method of manufacturing a thin film transistor having an offset region, as shown in FIG.
D (lower pressure chemical vapor deposition)
After a polysilicon film 22 is deposited by a method and low concentration phosphorus ions are implanted into the formed offset regions 23a and 23b, the formed source / drain regions 24a. 24
A high concentration of phosphorus ions is implanted in b.
【０００６】次いで、該注入された不純物の活性化のた
め約９００℃で熱処理を行って前記ポリシリコン層２２
上にＳｉＮのようなゲート絶縁膜２５を蒸着し、該ゲー
ト絶縁膜２５にコンタクトホールを形成した後、その上
にアルミニウム層を蒸着し食刻してゲート電極２６、ソ
ース電極２７、及びドレイン電極２８を夫々形成する。
ここで、前記オフセットの長さＬｓは３μｍ〜７μｍに
形成していた。Then, a heat treatment is performed at about 900 ° C. for activating the implanted impurities, thereby forming the polysilicon layer 22.
A gate insulating film 25 such as SiN is deposited thereon, and a contact hole is formed in the gate insulating film 25. Then, an aluminum layer is deposited thereon and etched to form a gate electrode 26, a source electrode 27, and a drain electrode. 28 are formed respectively.
Here, the length Ls of the offset is formed in the range of 3 μm to 7 μm.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、このよ
うな従来のオフセット領域を有した薄膜トランジスタに
おいては、オフセット領域２３ａ，２３ｂによりオン／
オフ電流比が図11に示したトップゲート型多結晶シリコ
ン薄膜トランジスタよりも増加するが、ソース領域２４
ａ側のオフセット領域２３ａによりオンの時に電流比が
減少するという問題点があった。However, in such a conventional thin film transistor having an offset region, the thin film transistor is turned on / off by the offset regions 23a and 23b.
Although the off-state current ratio is larger than that of the top gate type polycrystalline silicon thin film transistor shown in FIG.
There is a problem that the current ratio decreases when the transistor is turned on due to the offset region 23a on the a side.
【０００８】図12に示された従来の技術においては、ソ
ース及びドレイン領域側にオフセット領域を形成するた
めに絶縁側壁を形成し、ドレイン側にのみオフセット領
域を形成するためには、高濃度イオンを注入する以前に
ソース側の絶縁側壁を除去する必要があり、このため、
感光膜のマスクを形成すべきであるという不都合な点が
あった。In the prior art shown in FIG. 12, in order to form an insulating side wall on the source and drain region side to form an offset region and to form an offset region only on the drain side, a high concentration ion The source side insulation sidewalls must be removed before implanting
There is an inconvenience that a mask for the photosensitive film should be formed.
【０００９】このような問題点を解決するため本発明の
目的は、オン／オフ電流比を増加させ、オフセット領域
を形成するためのマスクを省いて製造工程の単純化を図
り得る薄膜トランジスタ及びその製造方法を提供しよう
とするものである。SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to increase the on / off current ratio and to omit a mask for forming an offset region, thereby simplifying a manufacturing process and a thin film transistor. It seeks to provide a way.
【００１０】[0010]
【課題を解決するための手段】このような目的を達成す
るため、本発明に係る薄膜トランジスタは、基板（３
１）と、該基板（３１）上に形成された活性層（３２）
と、該活性層（３２）の両端部を除く部分及び基板（３
１）上に形成され、前記活性層の一端部側から内方向に
凹む開口部（３４ｂ）を有したゲート電極（３４）と、
前記開口部（３４ｂ）下方の前記活性層（３２）内に形
成されたオフセット領域（３２ｄ）と、前記活性層（３
２）の両端部内に形成された不純物領域（３２ａ，３２
ｂ）と、を備えて構成されたことを特徴とする。In order to achieve such an object, a thin film transistor according to the present invention comprises a substrate (3).
1) and an active layer (32) formed on the substrate (31)
And a portion excluding both ends of the active layer (32) and the substrate (3).
1) a gate electrode (34) formed thereon and having an opening (34b) recessed inward from one end of the active layer;
An offset region (32d) formed in the active layer (32) below the opening (34b);
2) Impurity regions (32a, 32
b).
【００１１】前記本発明に係る薄膜トランジスタによれ
ば、ドレイン側にのみ形成されたオフセット領域により
オフの電流を減少させるようになっているため、オン／
オフ電流比を増加させることができる。また、前記本発
明に係る薄膜トランジスタにおいて、前記ゲート電極
（３４）の側面には、前記開口部（３４ｂ）を充填して
前記オフセット領域（３２ｄ）の上部が覆われるように
絶縁側壁（３５）が形成された構成としてもよい。According to the thin film transistor of the present invention, the off current is reduced by the offset region formed only on the drain side.
The off-state current ratio can be increased. In the thin film transistor according to the present invention, an insulating side wall (35) may be formed on a side surface of the gate electrode (34) so as to fill the opening (34b) and cover an upper portion of the offset region (32d). The formed structure may be used.
【００１２】また、本発明に係る薄膜トランジスタの製
造方法は、基板（３１）上に活性層（３２）を形成する
工程と、該活性層（３２）上の両端部を除く部分にゲー
ト絶縁膜（３３）を形成し、該ゲート絶縁膜（３３）上
に前記活性層の一端部側から内方向に凹む開口部（３４
ｂ）を有するゲート電極（３４）を形成する工程と、該
ゲート電極（３４）の両側面に絶縁側壁（３５）を形成
する工程と、前記活性層（３２）の両端部内に不純物領
域（３２ａ、３２ｂ）を形成する工程と、を順次行うこ
とを特徴とする。Further, in the method of manufacturing a thin film transistor according to the present invention, a step of forming an active layer (32) on a substrate (31) and a step of forming a gate insulating film ( An opening (34) is formed on the gate insulating film (33) inwardly inward from one end of the active layer.
b), forming insulating sidewalls (35) on both side surfaces of the gate electrode (34), and forming impurity regions (32a) in both ends of the active layer (32). , 32b) are sequentially performed.
【００１３】前記本発明に係る薄膜トランジスタ及びそ
の製造方法においては、オフセットを形成するため別の
マスクを省いて製造工程の単純化を図ることができる。
また、前記本発明に係る薄膜トランジスタの製造方法に
おいて、前記不純物領域（３２ａ，３２ｂ）は、傾斜イ
オン注入法により形成するようにしてもよい。このよう
にすれば、前記開口部３４ｂに充填された側壁３５の長
さが使用者の所望する適切なオフセット領域３２ｄの長
さよりも長くなる場合は、傾斜イオン注入により前記開
口部３４ｂに充填された絶縁側壁３５直下の活性層３２
まで所定の長さだけにイオンを浸透させ、以て、オフセ
ット領域を所望の長さに設定することができる。In the thin film transistor and the method of manufacturing the same according to the present invention, another mask can be omitted to form an offset, and the manufacturing process can be simplified.
In the method for manufacturing a thin film transistor according to the present invention, the impurity regions (32a, 32b) may be formed by a gradient ion implantation method. In this manner, when the length of the side wall 35 filled in the opening 34b is longer than the length of the appropriate offset region 32d desired by the user, the opening 34b is filled by inclined ion implantation. Active layer 32 immediately below the insulating sidewall 35
The ions can be permeated only to a predetermined length until the offset region can be set to a desired length.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態につい
て説明する。本発明に係る薄膜トランジスタにおいて
は、図１乃至図３に示すように、基板３１と、該基板３
１上に形成されたポリシリコンの活性層３２と、該活性
層３２内の両端部に夫々形成されたソース領域３２ａ及
びドレイン領域３２ｂを有する不純物領域と、該ソース
領域３２ａとドレイン領域３２ｂ間に形成されたチャン
ネル領域３２ｃと、該チャンネル領域３２ｃ内に前記ド
レイン領域３２ｂに隣接して所定長さＬを有して形成さ
れたオフセット領域３２ｄと、前記チャンネル領域３２
ｃ及び基板３１上に形成された酸化物のゲート絶縁膜３
３と、該ゲート絶縁膜３３上に前記オフセット領域３２
ｄの上部が開放されるように前記活性層の一端部側から
内方向に凹む開口部３４ｂを有して形成されたゲート電
極３４と、該ゲート電極３４の両側面に少なくとも前記
開口部３４ｂを充填させて前記オフセット領域３２ｄの
上部を覆うように形成された酸化物又は窒化物の絶縁側
壁35と、から構成されている。Embodiments of the present invention will be described below. In the thin film transistor according to the present invention, as shown in FIGS.
1, an active layer 32 of polysilicon, an impurity region having a source region 32a and a drain region 32b respectively formed at both ends in the active layer 32, and a region between the source region 32a and the drain region 32b. A channel region 32c formed therein; an offset region 32d having a predetermined length L adjacent to the drain region 32b in the channel region 32c;
c and oxide gate insulating film 3 formed on substrate 31
3 and the offset region 32 on the gate insulating film 33.
A gate electrode 34 having an opening 34b recessed inward from one end of the active layer so that an upper portion of the active layer d is opened, and at least the opening 34b on both side surfaces of the gate electrode 34. And an oxide or nitride insulating sidewall 35 formed so as to cover the upper portion of the offset region 32d.
【００１５】次に、このように構成された薄膜トランジ
スタの製造方法に対し説明する。まず、図４に示すよう
に、基板３１上にポリシリコンの活性層３２を化学気相
蒸着（ＣＶＤ）法によりパターニングして形成するが、
このとき、前記基板３１は絶縁基板と半導体上に絶縁物
質が形成された基板の中いずれか一つを選択して使用す
る。Next, a method of manufacturing the thin film transistor having the above-described structure will be described. First, as shown in FIG. 4, an active layer 32 of polysilicon is formed on a substrate 31 by patterning by a chemical vapor deposition (CVD) method.
At this time, as the substrate 31, one of an insulating substrate and a substrate having an insulating material formed on a semiconductor is selected and used.
【００１６】次いで、図５に示すように、前記活性層３
２を包含した基板３１上にゲート絶縁膜３３を形成する
ための酸化膜３３ａを形成し、該酸化膜３３ａ上にゲー
ト電極３４を形成するためのポリシリコン層３４ａを形
成する。この場合、前記酸化膜３３ａは化学気相蒸着法
により形成するか又は前記ポリシリコンの活性層３２を
熱酸化して形成する。このように熱酸化により酸化膜３
３ａを形成すると、該酸化膜３３ａが活性層３２上のみ
に形成される。その後、前記ポリシリコン層３４ａ内に
イオン注入を施して不純物をドーピングさせ、該ポリシ
リコン層３４ａの伝導度を向上させるが、前記不純物と
してはホウ素（Ｂ）、砒素（Ａｓ）、燐（Ｐ）を用い
る。Next, as shown in FIG.
An oxide film 33a for forming a gate insulating film 33 is formed on the substrate 31 including the semiconductor substrate 2, and a polysilicon layer 34a for forming a gate electrode 34 is formed on the oxide film 33a. In this case, the oxide film 33a is formed by a chemical vapor deposition method or by thermally oxidizing the polysilicon active layer 32. Thus, the oxide film 3 is formed by thermal oxidation.
When 3a is formed, oxide film 33a is formed only on active layer 32. Thereafter, impurities are doped by implanting ions into the polysilicon layer 34a to improve the conductivity of the polysilicon layer 34a. The impurities include boron (B), arsenic (As), and phosphorus (P). Is used.
【００１７】次いで、図６に示すように、前記酸化膜３
３ａ及びポリシリコン層３４ａをパターニングして前記
酸化膜３３ａからなるゲート絶縁膜３３及び前記ポリシ
リコン層３４ａからなるゲート電極３４を形成し、該ゲ
ート電極３４は、図５に示すように、前記活性層３２の
両端部が露出され、該ゲート電極３４の一方の側から内
方向に凹む開口部３４ｂを形成する。該開口部３４ｂは
前記活性層３２の上に形成され、該開口部３４ｂの形成
された活性層３２の一端部が他端部よりも多く露出され
る。また、前記開口部３４ｂを有するゲート電極３４は
ゲート用マスクを用いたフォトリソグラフィ工程により
形成され、該ゲート用マスクのパターンは、図９に示し
たように開口部３４ｂを有するゲート電極３４の形状と
同様に形成されたマスクを用いる。Next, as shown in FIG.
3a and the polysilicon layer 34a are patterned to form a gate insulating film 33 composed of the oxide film 33a and a gate electrode 34 composed of the polysilicon layer 34a. The gate electrode 34 is formed as shown in FIG. Both ends of the layer 32 are exposed to form an opening 34 b that is recessed inward from one side of the gate electrode 34. The opening 34b is formed on the active layer 32, and one end of the active layer 32 where the opening 34b is formed is more exposed than the other end. Further, the gate electrode 34 having the opening 34b is formed by a photolithography process using a gate mask, and the pattern of the gate mask has the shape of the gate electrode 34 having the opening 34b as shown in FIG. A mask formed in the same manner as described above is used.
【００１８】次いで、図７及び図１０に示すように、図
６に示した全ての構造物上に絶縁膜を形成し、該絶縁膜
を異方性食刻して前記ゲート電極３４の側面に絶縁側壁
３５を形成する。該絶縁側壁３５は前記開口部３４ｂを
充分に充填するように形成され、該開口部３４ｂに充填
された一方側の絶縁側壁３５の長さＬ１が他方側の絶縁
側壁３５の長さＬ２よりも長く形成する。この場合、前
記絶縁膜は酸化膜と窒化膜の中いずれか一つを選択して
使用する。Next, as shown in FIG. 7 and FIG. 10, an insulating film is formed on all the structures shown in FIG. An insulating side wall 35 is formed. The insulating sidewall 35 is formed so as to sufficiently fill the opening 34b, and the length L1 of one insulating sidewall 35 filled in the opening 34b is longer than the length L2 of the other insulating sidewall 35. Form long. In this case, one of the oxide film and the nitride film is selected and used as the insulating film.
【００１９】次いで、図８に示すように、前記ゲート電
極３４及び絶縁側壁３５をマスクとし前記活性層３２内
にイオンを注入し熱処理を施してソース領域３２ａ及び
ドレイン領域３２ｂとしての不純物領域を形成するが、
前記イオン注入時に用いる不純物はホウ素（Ｂ）、砒素
（Ａｓ）、及び燐（Ｐ）の中いずれか一つを用いること
もできるし、相互に組み合わせて使用することもでき
る。また、前記イオン注入の方向は通常基板３１に対し
垂直方向に行うが、前記開口部３４ｂに充填された側壁
３５の長さＬ１が使用者の所望する適切なオフセット領
域３２ｄの長さＬ４よりも長くなる場合は、傾斜イオン
注入により前記開口部３４ｂに充填された絶縁側壁３５
直下の活性層３２まで前記長さＬ１からＬ４を引いたＬ
３の長さだけにイオンが浸透（Drive-in）するようにす
る。このようにすると、前記傾斜イオン注入方法により
垂直イオン注入方法よりも前記オフセット領域３２ｄの
長さを減らすことができる。又、前記傾斜イオン注入又
は熱処理工程時、不純物の浸透長さＬ３はＬ２≦Ｌ３≦
Ｌ１になるようにする。従って、前記開口部３４ｂに充
填された絶縁側壁３５の長さＬ１から不純物の浸透長さ
Ｌ３を引いた長さをＬ４とすると、該Ｌ４の長さだけ前
記ドレイン領域３２ｂとチャンネル領域３２ｃ間にオフ
セット領域３２ｄが形成される。Next, as shown in FIG. 8, ions are implanted into the active layer 32 using the gate electrode 34 and the insulating side wall 35 as a mask and heat treatment is performed to form impurity regions as the source region 32a and the drain region 32b. But
As the impurity used for the ion implantation, any one of boron (B), arsenic (As), and phosphorus (P) can be used, or can be used in combination with each other. The direction of the ion implantation is usually perpendicular to the substrate 31, but the length L1 of the side wall 35 filled in the opening 34b is longer than the length L4 of the appropriate offset region 32d desired by the user. If it becomes longer, the insulating side wall 35 filled in the opening 34b by inclined ion implantation is used.
L obtained by subtracting L4 from the length L1 up to the immediately lower active layer 32
Drive-in the ions for only 3 lengths. In this case, the length of the offset region 32d can be reduced by the inclined ion implantation method as compared with the vertical ion implantation method. Further, at the time of the inclined ion implantation or the heat treatment step, the permeation length L3 of the impurity is L2 ≦ L3 ≦
L1. Accordingly, if the length obtained by subtracting the permeation length L3 of the impurity from the length L1 of the insulating side wall 35 filled in the opening 34b is L4, the length between the drain region 32b and the channel region 32c is the length of L4. An offset region 32d is formed.
【００２０】[0020]
【発明の効果】以上説明したように本発明に係る薄膜ト
ランジスタ及びその製造方法においては、ドレイン側に
形成されたオフセット領域によりオフの電流を減少させ
るようになっているため、オン／オフ電流比を増加さ
せ、オフセットを形成するため別のマスクを省いて製造
工程の単純化を図り得るという効果がある。As described above, in the thin film transistor and the method of manufacturing the same according to the present invention, since the off current is reduced by the offset region formed on the drain side, the on / off current ratio is reduced. There is an effect that the manufacturing process can be simplified by omitting another mask for forming the offset and forming the offset.
【図１】本発明に係る薄膜トランジスタの平面図。FIG. 1 is a plan view of a thin film transistor according to the present invention.
【図２】図１のａ−ａ線に従う縦断面図。FIG. 2 is a longitudinal sectional view taken along line aa of FIG.
【図３】図１のｂ−ｂ線に従う縦断面図。FIG. 3 is a vertical sectional view taken along line bb of FIG. 1;
【図４】本発明に係る薄膜トランジスタの製造方法の第
１の工程を示した縦縦断面図。FIG. 4 is a vertical longitudinal sectional view showing a first step of the method for manufacturing a thin film transistor according to the present invention.
【図５】同じく第２の工程を示した縦断面図。FIG. 5 is a longitudinal sectional view showing a second step in the same manner.
【図６】同じく第３の工程を示した縦断面図。FIG. 6 is a longitudinal sectional view showing a third step.
【図７】同じく第４の工程を示した縦断面図。FIG. 7 is a longitudinal sectional view showing a fourth step in the same manner.
【図８】同じく第５の工程を示した縦断面図。FIG. 8 is a longitudinal sectional view showing a fifth step.
【図９】図７の平面図。FIG. 9 is a plan view of FIG. 7;
【図10】図８の平面図。FIG. 10 is a plan view of FIG. 8;
【図11】一般のトップゲート型多結晶シリコン薄膜トラ
ンジスタを示した縦断面図。FIG. 11 is a longitudinal sectional view showing a general top gate type polycrystalline silicon thin film transistor.
【図12】従来オフセット領域を有する薄膜トランジスタ
を示した縦断面図。FIG. 12 is a longitudinal sectional view showing a conventional thin film transistor having an offset region.
３１ 基板 ３２ 活性層 ３２ａ ソース領域 ３２ｂ ドレイン領域 ３２ｃ チャンネル領域 ３２ｄ オフセット領域 ３３ ゲート絶縁膜 ３４ ゲート電極 ３４ｂ 開口部 ３５ 絶縁側壁 DESCRIPTION OF SYMBOLS 31 Substrate 32 Active layer 32a Source region 32b Drain region 32c Channel region 32d Offset region 33 Gate insulating film 34 Gate electrode 34b Opening 35 Insulating side wall
Claims (4)
された活性層（３２）と、該活性層（３２）の両端部を
除く部分及び基板（３１）上に形成され、前記活性層の
一端部側から内方向に凹む開口部（３４ｂ）を有したゲ
ート電極（３４）と、前記開口部（３４ｂ）下方の前記
活性層（３２）内に形成されたオフセット領域（３２
ｄ）と、前記活性層（３２）の両端部内に形成された不
純物領域（３２ａ，３２ｂ）と、を備えて構成されたこ
とを特徴とする薄膜トランジスタ。1. A substrate (31), an active layer (32) formed on the substrate (31), a portion excluding both ends of the active layer (32) and the substrate (31), A gate electrode (34) having an opening (34b) recessed inward from one end of the active layer; and an offset region (32) formed in the active layer (32) below the opening (34b).
d) and impurity regions (32a, 32b) formed in both ends of the active layer (32).
開口部（３４ｂ）を充填して前記オフセット領域（３２
ｄ）の上部が覆われるように絶縁側壁（３５）が形成さ
れたことを特徴とする請求項１に記載の薄膜トランジス
タ。2. The offset region (32) is filled in the side surface of the gate electrode (34) by filling the opening (34b).
2. The thin film transistor according to claim 1, wherein an insulating side wall is formed so as to cover an upper part of d).
る工程と、該活性層（３２）上の両端部を除く部分にゲ
ート絶縁膜（３３）を形成し、該ゲート絶縁膜（３３）
上に前記活性層の一端部側から内方向に凹む開口部（３
４ｂ）を有するゲート電極（３４）を形成する工程と、
該ゲート電極（３４）の両側面に絶縁側壁（３５）を形
成する工程と、前記活性層（３２）の両端部内に不純物
領域（３２ａ、３２ｂ）を形成する工程と、を順次行う
ことを特徴とする薄膜トランジスタの製造方法。3. A step of forming an active layer (32) on a substrate (31), and forming a gate insulating film (33) on a portion of the active layer (32) except for both ends. (33)
An opening (3) recessed inward from one end of the active layer
Forming a gate electrode (34) having 4b);
A step of forming insulating side walls (35) on both side surfaces of the gate electrode (34) and a step of forming impurity regions (32a, 32b) at both ends of the active layer (32) are sequentially performed. Manufacturing method of a thin film transistor.
斜イオン注入法により形成することを特徴とする請求項
３記載の薄膜トランジスタの製造方法。4. The method according to claim 3, wherein the impurity regions (32a, 32b) are formed by a gradient ion implantation method.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR17387/1997 | 1997-05-07 | ||
| KR1019970017387A KR100244467B1 (en) | 1997-05-07 | 1997-05-07 | Thin-film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10321866A true JPH10321866A (en) | 1998-12-04 |
| JP2939735B2 JP2939735B2 (en) | 1999-08-25 |
Family
ID=19504992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10008732A Expired - Fee Related JP2939735B2 (en) | 1997-05-07 | 1998-01-20 | Thin film transistor and method of manufacturing the same |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US6011276A (en) |
| JP (1) | JP2939735B2 (en) |
| KR (1) | KR100244467B1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100253261B1 (en) * | 1997-06-03 | 2000-04-15 | 김영환 | Fabrication method of thin film transistor |
| KR100590265B1 (en) * | 2001-03-12 | 2006-06-15 | 삼성에스디아이 주식회사 | Method for fabricating TFT using MILC |
| KR100426381B1 (en) * | 2001-03-30 | 2004-04-08 | 주승기 | Method for fabricating thin film transistor including a crystalline silicon active layer |
| KR100885013B1 (en) * | 2002-01-03 | 2009-02-20 | 삼성전자주식회사 | Thin film transitor and liquid crystal display |
| FR2871294A1 (en) * | 2004-06-07 | 2005-12-09 | St Microelectronics Sa | METHOD FOR PRODUCING A REDUCED SIZE DMOS TRANSISTOR, AND A RESULTING DMOS TRANSISTOR |
| JP2006339343A (en) * | 2005-06-01 | 2006-12-14 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| US8598659B2 (en) * | 2005-10-26 | 2013-12-03 | Hewlett-Packard Development Company, L.P. | Single finger gate transistor |
| KR101377596B1 (en) * | 2006-06-02 | 2014-03-26 | 삼성전자주식회사 | Thin film transistor formed on flexible substrate and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4771012A (en) * | 1986-06-13 | 1988-09-13 | Matsushita Electric Industrial Co., Ltd. | Method of making symmetrically controlled implanted regions using rotational angle of the substrate |
| US5151374A (en) * | 1991-07-24 | 1992-09-29 | Industrial Technology Research Institute | Method of forming a thin film field effect transistor having a drain channel junction that is spaced from the gate electrode |
| US5604139A (en) * | 1994-02-10 | 1997-02-18 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
| US5804837A (en) * | 1994-06-27 | 1998-09-08 | Samsung Electronics Co., Ltd. | Polysilicon thin-film transistor and method for fabricating the same |
| JP2586844B2 (en) * | 1994-12-28 | 1997-03-05 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| KR960042942A (en) * | 1995-05-04 | 1996-12-21 | 빈센트 비.인그라시아 | Semiconductor Device Forming Method |
| US5889303A (en) * | 1997-04-07 | 1999-03-30 | Motorola, Inc. | Split-Control gate electrically erasable programmable read only memory (EEPROM) cell |
-
1997
- 1997-05-07 KR KR1019970017387A patent/KR100244467B1/en not_active IP Right Cessation
- 1997-10-17 US US08/953,651 patent/US6011276A/en not_active Expired - Lifetime
-
1998
- 1998-01-20 JP JP10008732A patent/JP2939735B2/en not_active Expired - Fee Related
-
1999
- 1999-07-08 US US09/349,945 patent/US6100121A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US6011276A (en) | 2000-01-04 |
| US6100121A (en) | 2000-08-08 |
| KR19980082459A (en) | 1998-12-05 |
| KR100244467B1 (en) | 2000-02-01 |
| JP2939735B2 (en) | 1999-08-25 |
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