JPH10320933A - Circuit for processing reproduction signal of optical disk - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for processing reproduction signals of an optical disk which can shorten an error correction delay time. SOLUTION: This circuit includes a PLL circuit 2 which extracts a bit clock from a reproduction signal from an optical disk including a product code as an error-correcting code, a demodulation circuit 4 which generates a synchronous word clock in response to the reproduction signal and bit clock and outputs demodulation data; a switch 3 which outputs as a word clock either of the synchronous word clock and a fixed word clock of an oscillation circuit 1 (higher frequency than an average frequency of the synchronous word clock); an error-correcting circuit 10 which, responding to the word clock, corrects errors of the demodulation data with the use of the error-correcting code, outputs corrected demodulation data, and outputs a data output completion signal when completing the outputting of the corrected demodulation data; and a control computer 8 which outputs as the word clock the fixed word clock before receiving the data output completion signal after the reproduction signal is interrupted, and the synchronous word clock at other times than the above to the switch 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk reproduction signal processing circuit used in an optical disk recording / reproduction device or reproduction device for processing a reproduction signal including an error correction signal from the optical disk.

[0002]

2. Description of the Related Art In recent years, various types of optical disks such as a compact disk (CD) and a laser disk (LD) have been commercialized, and large-capacity optical disks such as digital video disks (DVD) have appeared. ing. A large-capacity disc such as a DVD has information recorded at a higher density than a conventional CD or the like, so that an error easily occurs in a reproduced signal. For example, narrowing the track bitch increases crosstalk between tracks, and shortening the bit length (increase linear density) increases intersymbol interference and increases the probability of erroneously reproducing signals. . Therefore, a high-density optical disk employs an error correction code having a higher performance and a higher correction capability than an error correction code used in a conventional CD or the like.

In the above-mentioned DVD, as shown in FIG.
The Reed-Solomon product code of 82 bytes × 208 columns is
A 16-row PO parity and a 10-column PI parity are generated and added to user data of a data sector (172 bytes × 192 rows). The error correction method of FIG. 3 is referred to as RSPC (Reed-Solomon Produ).
ct Code), for example, in the literature (“Oplu
s E ", 1996-6, No. 199, p93-9.
7, DVD physical format and modulation method). As described above, when a product code is used as an error correction code, it is necessary to temporarily store input data in a memory.

The reproduced signal data is stored in the memory in order from address 0 in FIG. 3 to addresses 1, 2, 3,..., N. Error correction (PI correction) in the row direction (horizontal direction in the figure)
Can be executed if data is input up to the rightmost address in FIG. 3 (182 × (n−1): n = 1 to 208), but in the column direction (vertical direction in FIG. It cannot be executed until input is completed up to the last line. Therefore, R
In the SPC method, a memory for recording input data of at least 182 × 208 bytes is required.

In the case where the reproduction signal data is input continuously, for example, a memory for 182 × 208 × 2 pages is prepared, and while the data is input to one page, the data is input to the other page. Error correction processing of stored data is performed. Data input and output in this case,
The relationship between the error correction processing times is as shown in FIG.

[0006]

As shown in FIG. 4, an error correction system using a product code such as the RSPC system requires time to store data in a memory. The delay time (correction delay) from data input to output is increased. For example, in a DVD, as shown in FIG.
Since data of * 208 bytes is stored, the delay time due to error correction is several tens of ms, and occupies a fraction of the entire access time.

In general, the correction delay time is included in the access time of data as a file device, so that an increase in the correction delay time increases (deteriorates) the access time, and thus affects the performance as a file device.

An object of the present invention is to provide an optical disk reproduction signal processing circuit capable of reducing an error correction delay time.

Another object of the present invention is to provide an optical disk reproduction signal processing circuit capable of shortening an error correction delay time and realizing a file device having a short access time.

[0010]

According to a first aspect of the present invention, there is provided an optical disk reproduction signal processing circuit for processing a reproduction signal including an error correction code from an optical disk. Bit clock extracting means for extracting the reproduced bit clock, generating a synchronous word clock word-synchronized with the reproduced signal in response to the reproduced signal and the bit clock, outputting the synchronous word clock to a synchronous word clock output terminal, A demodulating means for demodulating data based on the synchronous word clock and outputting demodulated data to a demodulated data output terminal; a fixed word clock generating means for generating a fixed word clock and outputting the same to a fixed word clock output terminal; An output terminal, and the synchronous word clock output terminal and the fixed word clock. Switching means for connecting one of the output terminals to the switching output terminal; performing error correction of the demodulated data using the error correction code in response to a word clock supplied to the switching output terminal; And error correction means for outputting a data output completion signal when the output of the corrected demodulated data is completed, and the switching means until the data output completion signal is received after the reproduction signal is interrupted. An optical disk reproduction signal processing circuit comprising: a control unit for connecting a fixed word clock output terminal to the switching output terminal; and a control unit for connecting the synchronous word clock output terminal to the switching output terminal otherwise. Is obtained.

According to a second aspect of the present invention, in an optical disk reproduction signal processing circuit for processing a reproduction signal including an error correction code from an optical disk, a bit clock bit-synchronized with the reproduction signal is extracted from the reproduction signal. PL
An L circuit, generating a synchronous word clock word-synchronized with the reproduced signal in response to the reproduced signal and the bit clock, outputting the synchronous word clock to a synchronous word clock output terminal, and generating a synchronous word clock from the reproduced signal based on the synchronous word clock. A demodulation circuit that demodulates data and outputs demodulated data to a demodulated data output terminal; an oscillation circuit that generates a fixed word clock and outputs the same to a fixed word clock output terminal; and a switching output terminal. A switch for connecting one of a terminal and the fixed word clock output terminal to the switching output terminal, and performing error correction of the demodulated data using the error correction code in response to the word clock supplied to the switching output terminal. Output the corrected demodulated data and output the data when the output of the corrected demodulated data is completed. An error correction circuit for outputting a completion signal,
Until the data output completion signal is received after the reproduction signal is interrupted, the switch connects the fixed word clock output terminal to the switch output terminal, otherwise the switch connects the synchronous word clock output terminal to the switch. An optical disk reproduction signal processing circuit having a control computer connected to the switching output terminal is obtained.

Preferably, in the optical disk reproduction signal processing circuit according to the first and second aspects, the frequency of the fixed word clock is higher than the average frequency of the synchronous word clock.

Preferably, in the optical disk reproduction signal processing circuit according to the first and second aspects, the error correction code is a product code.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an optical disk reproduction signal processing circuit according to one embodiment of the present invention.

This optical disk reproduction signal processing circuit processes a reproduction signal 101 from an optical disk (not shown). The reproduction signal 101 includes a Reed-Solomon product code as described in FIG. 3 as an error correction code, and the reproduction signal 101 includes a demodulation circuit 4 and a PLL.
(Phase locked loop) circuit 2.

The PLL circuit 2 converts the reproduced signal 101 into a bit clock 103 bit-synchronized with the reproduced signal 101.
Is output.

The demodulation circuit 4 generates a synchronous word clock 104 word-synchronized with the reproduced signal 101 in response to the reproduced signal 101 and the bit clock 103 and outputs it to a synchronous word clock output terminal. Demodulates data based on clock 104,
The demodulated data 106 is output to the demodulated data output terminal.

The oscillation circuit 1 has a fixed word clock 102
Is generated and output to the fixed word clock output terminal. The frequency of the fixed word clock 102 is set higher than the average frequency of the synchronous word clock 104.

The clock switch 3 has a switching output terminal, and connects one of the synchronous word clock output terminal of the demodulation circuit 4 and the fixed word clock output terminal of the oscillation circuit 1 to the switching output terminal.

The error correction circuit 10 performs error correction of the demodulated data 108 using the error correction code in response to the word clock 106 supplied to the switching output terminal of the clock switch 3, And outputs a data output completion signal 107 when the output of the corrected demodulated data 112 is completed.

The control computer 8 monitors the reproduction signal 101, and outputs the clock signal from the fixed word clock output terminal of the oscillation circuit 1 to the clock switch 3 until the data output completion signal 107 is received after the reproduction signal 101 is interrupted. The switching output terminal of the switching unit 3 is connected to the switching output terminal of the clock switching unit 3, and the clock switching unit 3 connects the synchronization word clock output terminal of the demodulation circuit 4 to the switching output terminal of the clock switching unit 3.

The clock switch 3 converts the synchronous word clock 104 and the fixed word clock 102 into a switching signal 10
5 to switch one of the synchronous word clock 104 and the fixed word clock 102 to the word clock 10.
Output as 6.

The error correction circuit 10 has a word clock 10
6, the demodulated data 108 is subjected to error correction using the error correction code, and the corrected demodulated data 112 is output. When the output of the corrected demodulated data 112 is completed, the data output completion signal 107 is output. Output. Therefore, the error correction circuit 10 includes an error correction circuit controller 5, an error correction memory 6, and an error correction logic circuit 7, which will be described later.
Having.

Next, the operation of the optical disk reproduction signal processing circuit of FIG. 1 will be described in detail.

The PLL circuit 2 extracts a clock from a change point of the reproduction signal 101 and outputs a bit clock 103 bit-synchronized with the reproduction signal 101.

The demodulation circuit 4 demodulates data from the reproduction signal 101 and the bit clock 103. Normally, the reproduction signal 101 includes a synchronization signal, and a synchronization word clock 104 that is word-synchronized with the reproduction signal 101 is generated based on the synchronization signal.
At 04, the signal input in serial is converted in parallel. In the DVD, 16 bits (serial) of the reproduction signal 101 are converted into 8-bit (1 byte) parallel data, and the parallel data is output as demodulated data 108.

The parallel demodulated data 108
Is input to the error correction circuit controller 5, and the synchronous word clock 104 is input to the error correction circuit controller 5 through the clock switch 3. Clock switch 3
Switches between the synchronous word clock 104 and the fixed word clock 102 from the oscillation circuit 1. At this time, the clock switch 3 is normally controlled by the switch signal 105 from the control computer 8 so as to output the synchronous word clock 104 as the word clock 106.

The error correction circuit controller 5 operates in synchronization with the word clock 106. The error correction circuit controller 5 temporarily stores the demodulated data 108 in the error correction memory 6 via the memory bus 109. Then, when the required data amount is accumulated in the error correction memory 6, it is input to the error correction logic circuit 7 as correction data 110 to be corrected. The error correction logic circuit 7 corrects the error of the correction data 110 to be corrected, and then corrects the corrected data 1.
As 11, it is output to the error correction circuit controller 5.
The error correction circuit controller 5 records the corrected data 111 in the error correction memory 6 again. At this time, the error correction circuit controller 5 operates in the horizontal direction (PI
Correction) control first, then vertical (PO correction)
Control the correction of The error correction circuit controller 5 calculates P
When both the I and PO correction processes are completed, the corrected data 111 recorded in the error correction memory 6 is output to the outside as the corrected demodulated data 112, and the error correction signal processing is completed. The error correction circuit controller 5 outputs a data output completion signal 107 to the control computer 8 when the error correction processing of the data amount set in advance from the control computer 8 is completed and the error correction circuit controller 5 outputs the corrected demodulated data 112 to the outside. .

In the optical disk reproduction signal processing circuit shown in FIG. 1, there is no problem when the reproduction signal 101 is continuously inputted without interruption, as shown in FIG. When the optical heads are not continuously arranged on the optical disk, it is necessary to perform a track jump and move the optical head to a track having data to be reproduced. However, during such an access operation,
Since the reproduction signal 101 is interrupted, the PLL circuit 2 releases the lock and outputs the free-running oscillation frequency.

Therefore, in the optical disk reproduction signal processing circuit of FIG. 1, the control computer 8 causes the clock switch 3 to set the word clock 106 at the time of the access operation to a fixed frequency higher than the synchronous word clock 104, as shown in FIG. Switching signal 105 for switching to word clock 102
To the clock switch 3 to shorten the data output time and minimize the increase in access time due to correction delay. FIG. 2 shows an output completion time in the synchronous word clock 104 for reference.

The frequency of the fixed word clock 102 is meaningless unless it is higher than the frequency of the synchronous word clock 104. However, there is an upper limit due to the access time of the error correction logic circuit 7 and the error correction memory 6, and so on. To an appropriate value for.

When the output of the demodulated data 112 after the correction is completed, the control computer 8 changes the word clock 106 to the synchronous word clock 104 by the switching signal 105 in preparation for the input of the reproduction signal 101 at the next reproduction position. Output to the clock switch 3.

By doing so, the data correction delay time can be reduced in an optical disk drive such as a DVD drive which employs a product code having a long code length. This effect becomes remarkable especially when the optical head repeatedly accesses.

[0035]

As described above, according to the present invention, an optical disk reproduction signal processing circuit capable of shortening the error correction delay time can be obtained, and a file device having a short access time can be realized by using this optical disk reproduction signal processing circuit. Becomes

[Brief description of the drawings]

FIG. 1 is a block diagram of an optical disk reproduction signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the present invention.

FIG. 3 is a diagram for explaining a format of a DVD error correction system (RSPC system).

FIG. 4 is a time chart for explaining a correction delay time of a normal DVD.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Oscillation circuit 2 PLL circuit 3 Clock switch 4 Demodulation circuit 5 Error correction circuit controller 6 Error correction memory 7 Error correction logic circuit 8 Control computer 10 Error correction circuit 101 Reproduction signal 102 Fixed word clock 103 Bit clock 104 Synchronization word clock 105 Switching signal 106 Word clock 107 Data output completion signal 108 Demodulated data 109 Memory bus 110 Corrected data 111 Corrected data 112 Corrected demodulated data

Claims (6)

[Claims] 1. An optical disk reproduction signal processing circuit for processing a reproduction signal including an error correction code from an optical disk, wherein: a bit clock extracting means for extracting a bit clock bit-synchronized with the reproduction signal from the reproduction signal; Generating a synchronous word clock word-synchronized with the reproduction signal in response to the bit clock and outputting the same to a synchronous word clock output terminal, and demodulating data from the reproduction signal based on the synchronous word clock; A demodulating means for outputting demodulated data to an output terminal; a fixed word clock generating means for generating a fixed word clock for output to a fixed word clock output terminal; and a switching output terminal, wherein the synchronous word clock output terminal and the fixed Connect one of the word clock output terminals to the switching output terminal A switching unit that performs error correction of the demodulated data using the error correction code in response to the word clock supplied to the switching output terminal, outputs corrected demodulated data, and outputs the corrected demodulated data. Error correction means for outputting a data output completion signal when the output is completed, and until the data output completion signal is received after the reproduction signal is interrupted, the switching means sets the fixed word clock output terminal to the switching output terminal. An optical disc reproduction signal processing circuit, comprising: control means for causing the switching means to connect the synchronous word clock output terminal to the switching output terminal. 2. The optical disk reproduction signal processing circuit according to claim 1, wherein a frequency of said fixed word clock is higher than an average frequency of said synchronous word clock. 3. The optical disk reproduction signal processing circuit according to claim 1, wherein the error correction code is a product code. 4. An optical disk reproduction signal processing circuit for processing a reproduction signal including an error correction code from an optical disk, wherein: a PLL circuit for extracting a bit clock bit-synchronized with the reproduction signal from the reproduction signal; A synchronous word clock word-synchronized with the reproduced signal is generated in response to the bit clock and output to a synchronous word clock output terminal, and data is demodulated from the reproduced signal based on the synchronous word clock. A demodulation circuit that outputs demodulated data to a fixed word clock output terminal; and an oscillation circuit that generates a fixed word clock and outputs the fixed word clock to a fixed word clock output terminal. A switch for connecting one to the switching output terminal, and the switching output terminal Error correction of the demodulated data is performed using the error correction code in response to the supplied word clock, and the demodulated data is output after correction. When the output of the corrected demodulated data is completed, a data output completion signal An error correction circuit that outputs the fixed word clock output terminal to the switching output terminal until the data output completion signal is received after the reproduction signal is interrupted, and otherwise the switching device An optical disk reproduction signal processing circuit, comprising: a control computer for connecting the synchronous word clock output terminal to the switching output terminal. 5. The optical disk reproduction signal processing circuit according to claim 4, wherein a frequency of said fixed word clock is higher than an average frequency of said synchronous word clock. 6. The optical disk reproduction signal processing circuit according to claim 4, wherein the error correction code is a product code.