JPH1031867A - Decoder device and decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an effect which improves the anti-rolling characteristic, to give the effect minimizing the error uncorrectable region due to influences of discontinuous points of data at linking points and to secure reliability in reproduced data. SOLUTION: Resynchronizing processing is executed at the position of 64 frames from the time point t1 where a signal FD START rises, and RAM resetting is executed at the position of 69 frames. And the processing of C2 inhibition/C1PC(pointer copy) is executed during the period of 131 frames from the starting point on the position 69 frames from the time point t1. By this, resynchronizing processing, RAM resetting and C2 inhibition/C1PC processing are executed with having no effect on the main data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a decoder and a decoding method for decoding data read from a digital signal recording medium.

[0002]

2. Description of the Related Art In recent years, various digital data recording media have been put into practical use. For example, a reproduction-only system using an optical disc such as a compact disc system, or a user recording / reproducing audio data using a magneto-optical disc as a recording medium.
2. Description of the Related Art A mini disc system capable of playing is known.

[0003] By the way, in a CD system or a mini-disc system, an error correction code is added to audio data to be recorded, and EFM modulation is performed. For this reason, the reproducing apparatus is provided with an EFM decoder, and performs EFM demodulation and error correction processing.

The EFM decoder locks a PLL circuit using an input EFM signal to generate a PLL clock. Then, EFM demodulation (14-8 conversion) is performed using the PLL system clock, and the demodulated data is written in a RAM used for error correction. In addition,
As an error correction code, for example, in the case of a CD system, C
If the IRC (Cross Interleave Reed-Solomon Code) is adopted and the mini disk system, the CIRC (Advanced Interleave + CI
RC) is used. On the other hand, a crystal-based stabilized clock is used for reading from the RAM.

The EFM decoder generates a clock for CLV (constant linear velocity) servo of a spindle motor for rotating the disk. The clock for the CLV servo for the read-only disk is generated by injecting the EFM signal into the PLL circuit. On the other hand, in the magneto-optical area of the magneto-optical disk, the absolute address information (ADIP information) detected from the wobbling pre-groove formed on the disk is used to calculate the AD.
An IP sync is obtained and CLV servo information is generated using the IP sync.

[0006]

As described above, in the RAM in the EFM decoder, the write system clock and the read system clock are different. There is also a limit to the capacity of the RAM that can be mounted. For this reason, the RAM may overflow beyond the jitter margin due to various causes such as disturbance, PLL swing, linking, scratches on the disk, CLV servo failure, track jump, and the like.

If the RAM overflows, the read data becomes unreliable. For this reason, normally, when an overflow occurs, the write pointer of the RAM is reset to the center of the jitter margin, ie, RA
Although the M reset is performed, the read data remains unreliable for a while (about 15 ms). The overflow caused by the linking during the normal operation particularly impairs the reliability of the operation stability of the mini disc reproducing apparatus.

[0008] This point will be described in detail. In the case of a mini disc system, data to be recorded is divided into units called clusters as shown in FIG. 17, and this is the minimum unit at the time of recording. One cluster is composed of 36 sectors. Of these sectors, "00" to "1" shown in FIG.
The 32 sectors up to F ″ are the main data sector, and the actual audio data and management information are recorded in this sector. The remaining four sectors “FC” to “FF” are used as linking areas by dummy data. However, at least the sector “FF” is defined so as to be usable as a sub data area. Therefore, the substantial linking areas are “FC” to “F”.
E ”.

[0010] In the EFM signal, a frame sync is obtained at a period of 7.35 KHz. However, in the linking area of “FC” to “FF”, recording data is not managed accurately, and
The frame continuity of the FM signal loses the correct continuity. Since writing to the RAM is controlled using a frame sync detected from the output of the PLL system, the frame sync is disturbed, so that the jitter margin is gradually shifted from the center, and the influence of the frame sync disturbance is accumulated and stored in the RAM. Overflow occurs.

For example, if the RAM overflows in the main data sector as shown in FIG. 18, the RAM is reset as described above. At this time, the write pointer is reset to the center of the jitter margin.
The data writing to M is not the same as the input data (EFM demodulated data), but is discontinuous, that is, the interval is increased or overlapped and shortened. Then, in the portion where the RAM reset is performed, the data of the C2 series is discontinuous, so that the C2 cannot be corrected or a C2 error occurs. Since the total number of data is incorrect at that point, the scramble in the CD-ROM format is erroneous from that point onward, resulting in erroneous data for at least one sector.

As described above, RA in the main data sector
When the M overflow occurs, that is, a main data error occurs. In this case, it is necessary to perform a retry of reading data from the disk again, and in this respect, the playability is low.

In the magneto-optical area, the CLV servo
Since this is performed using an IP sink, the EFM signal and the CLV system are irrelevant. For this reason, in the case where the RAM writing deviates from the center of the jitter margin in the linking portion, there is also a situation in which it is not possible to perform feedback control to return this to the center in the CLV system.

Further, even when overflow does not occur, deviation from the center of the jitter margin due to the influence of the linking sector leads to deterioration of functions such as so-called anti-rolling.

Further, as described above, in the mini-disk system, writing to the disk is performed in cluster units. However, among the sectors "FC" to "FE" which are actually linking areas, the center of the sector "FD" is written. At the position, two consecutive clusters are connected (the connection position of this cluster is called a linking point). That is, the linking points are the end position and the start position of the data writing in cluster units. Then, before and after this linking point, data is naturally discontinuous, but with this, continuity cannot be obtained even for the C2 sequence in error correction. In other words, before and after the linking point, the error correction processing using the C2 sequence does not make sense. In spite of this, for example, when error correction using the C2 sequence is performed, all byte data of the C2 sequence over one interleave section before and after the C1 error area which is an inevitable error generation section at the linking point. It turns out to be an error. That is, not only the C1 error area, which is the data actually damaged, but also the correct data over a wide section before and after the C1 error area is processed as an uncorrectable area. In other words, the error area of the data is unnecessarily expanded, and in some cases, the area of the main data before and after the linking area may be affected by the error correction error due to the C2 sequence. May be impaired.

In the mini disc system,
For example, in the EFM demodulation processing system, decoding processing is executed by obtaining synchronization based on a frame synchronization signal (hereinafter referred to as frame sync) of input data. However, the timing of frame sync is irrelevant before and after the linking point. Becomes discontinuous. Therefore, E
In the FM demodulation processing system, a newly input frame sync is taken in at an appropriate timing after the linking point has elapsed, and synchronization with the input data is again performed (hereinafter, this operation is also referred to as "resynchronization processing"). ), It is necessary to execute an appropriate decoding process for the current cluster.

[0016]

In view of the above problems, the present invention performs EFM demodulation on the above EFM signal using a clock synchronized with the input EFM signal, and then performs the EFM demodulation. The read data is written into the memory means and read out from the memory means using a clock generated by a stable system clock, and then the read data is subjected to error correction processing by the error correction processing means and output as reproduced data. As a decoder device, a resynchronization process for executing resynchronization by treating frame syncs of all input EFM signals as effective information for synchronization, and a write address of the memory unit so that a jitter margin of the memory unit is centered. Reset processing for executing a reset, and a predetermined data in the error correction processing means. An error correction prohibition process for preventing an error correction process using an error correction code added to a column from being executed at a predetermined timing in a linking sector area of a sector of an input EFM signal. The linking processing timing generating means is provided.

The linking processing timing generating means performs the resynchronization processing and the reset processing based on a sector position indication signal indicating a predetermined position of the linking sector area obtained based on the absolute address information read from the recording medium. , And the execution timing of the error correction prohibition processing.

After performing EFM demodulation on the EFM signal using a clock synchronized with the input EFM signal, the EFM demodulated data is written into a memory means, and a clock generated by a stable system clock is output. After the data is read out to the memory means, the read data is subjected to error correction processing by the error correction processing means, and as a decoding method for outputting as reproduced data, the frame sync of all the input EFM signals is synchronized. A re-synchronization process for performing re-synchronization by treating as effective information, a reset process for resetting a write address so that a jitter margin of the memory unit is at a center, and a predetermined process in the error correction processing unit. Using error correction code added to data sequence Ri and correction errors so as not to perform correction inhibiting process, and so as to execute at predetermined timing in a sector linking sector area of the EFM signal input.

According to the above configuration, resynchronization processing
RAM reset operation and erroneous correction prohibition processing (for example, CI
In the case where RC is used, three processes (linking process) including the error correction process in which error correction using the C2 sequence is not performed are performed at required timing in the linking area of the sector. In the configuration of the present invention, the linking process is performed automatically by the decoder device itself while performing timing control based on the absolute address information extracted from the reproduction signal, irrespective of the timing given from control means such as an external system controller. It becomes possible to execute it.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a recording apparatus according to the present invention will be described below. This embodiment is a recording / reproducing apparatus using a magneto-optical disk (mini disk) as a recording medium.
In the following description of the present embodiment, resynchronization processing executed at a timing in the linking area and RA
The M reset process and the erroneous correction prohibition process will be dealt with, and these three processes are collectively referred to as “linking process”. Further, the error correction prohibition process of the present embodiment is an error correction process in which an error result based on the C1 sequence is used without performing an error correction based on the C2 sequence, as will be described in detail later. Is referred to as “C2 prohibition / C1PC (Pointer Copy)” processing. The following description will be made in the following order. 1. 1. Configuration of recording / reproducing device 2. Configuration of encoder / decoder section Linking processing of this embodiment 3-a Resynchronization processing 3-b RAM reset 3-c C2 inhibition / C1PC processing 3-d Timing of C2 inhibition / C1PC processing in linking processing 3-e Timing control of linking processing 3-f Circuit configuration for linking processing

1. 1. Configuration of Recording / Reproducing Apparatus FIG. 1 is a block diagram of a main part of a recording / reproducing apparatus according to the present embodiment. The magneto-optical disk 1 on which audio data is recorded is driven to rotate by a spindle motor 2. The optical head 3 irradiates the magneto-optical disk 1 with laser light during recording / reproduction.

The optical head 3 performs a high-level laser output for heating a recording track to the Curie temperature during recording, and a relatively low-level laser for detecting data from reflected light by a magnetic Kerr effect during reproduction. Perform output. Therefore, the optical head 3 is equipped with a laser diode as a laser output unit, an optical system including a polarizing beam splitter and an objective lens, and a detector for detecting reflected light. The objective lens 3a is 2
It is held by a shaft mechanism 4 so as to be displaceable in the radial direction of the disk and in the direction of coming into contact with and separating from the disk.

A magnetic head 6a is disposed at a position facing the optical head 3 with the disk 1 interposed therebetween. The magnetic head 6a performs an operation of applying a magnetic field modulated by the supplied data to the magneto-optical disk 1. The entire optical head 3 and the magnetic head 6a can be moved in the disk radial direction by the thread mechanism 5.

The information detected from the disk 1 by the optical head 3 by the reproducing operation is supplied to the RF amplifier 7. The RF amplifier 7 performs an arithmetic operation on the supplied information,
A reproduction RF signal, a tracking error signal TE, a focus error signal FE, groove information (absolute position information recorded as a pre-groove (wobbling groove) on the magneto-optical disk 1) GFM, and the like are extracted. The extracted reproduced RF signal is supplied to the encoder / decoder section 8. Further, the tracking error signal TE and the focus error signal FE are supplied to the servo circuit 9, and the groove information GFM is supplied to the address decoder 10.

The servo circuit 9 is provided with the supplied tracking error signal TE and focus error signal FE, and the system controller 1 composed of a microcomputer.
Various servo drive signals are generated based on a track jump command, an access command, rotation speed detection information of the spindle motor 2 and the like from the controller 1 to control the two-axis mechanism 4 and the sled mechanism 5 to perform focus and tracking control. 2 is controlled to a constant linear velocity (CLV).

The address decoder 10 decodes the supplied groove information GFM to extract an ADIP signal which is absolute address information on the disk. This ADIP signal is supplied to the system controller 11 and used for various control operations. In the address decoder 10 of the present embodiment, a signal FD • START indicating the start timing of the sector “FD” is generated based on the ADIP signal and supplied to the encoder / decoder unit 8 as described later. . This signal FD • START is used for controlling the timing of the linking process in the encoder / decoder unit 8. The reproduced RF signal is subjected to EFM demodulation and AC
Decoding processing such as IRC is performed. At this time, addresses, subcodes, and the like included in the reproduced RF signal are also extracted as data and supplied to the system controller 11.

EFM demodulation in the encoder / decoder section 8
The decoded audio data (sector data) such as CIRC is temporarily written into the buffer memory 13 by the memory controller 12. The reading of data from the disk 1 by the optical head 3 and the transfer of reproduced data in the system from the optical head 3 to the buffer memory 13 are at 1.41 Mbit / sec, and are usually performed intermittently.

The data written in the buffer memory 13 is read out at a timing when the transfer of the reproduction data becomes 0.3 Mbit / sec, and is supplied to the encoder / decoder section 14. Then, the signal is subjected to reproduction signal processing such as decoding processing for the audio compression processing, converted into an analog signal by the D / A converter 15, supplied from the output terminal 16 to a predetermined amplification circuit section, and reproduced and output. For example, they are output as L, R analog audio signals.

When a recording operation is performed on the magneto-optical disk 1, the recording signal (analog audio signal) supplied to the input terminal 17 is converted into digital data by the A / D converter 18 and then converted to digital data. Encoder / decoder unit 1
4 and subjected to audio compression encoding processing. The recording data compressed by the encoder / decoder 14 is temporarily written to the buffer memory 13 by the memory controller 12. Then, when a predetermined amount or more of data is accumulated in the buffer memory 13, the data is read in predetermined data units and sent to the encoder / decoder unit 8. Then, the encoder / decoder unit 8 sets the CIRC
After the encoding process such as encoding and EFM modulation,
It is supplied to the magnetic head drive circuit 6.

The magnetic head drive circuit 6 supplies a magnetic head drive signal to the magnetic head 6a according to the encoded recording data. That is, the magneto-optical disk 1
Is applied by the magnetic head 6a. At this time, the system controller 11 supplies a control signal to the optical head so as to output a laser beam at a recording level. Through the buffer memory 13, the recording operation for the audio data that is continuously input is intermittently performed.

The operation unit 19 is provided with various keys used for user operations. For example, a record key, a play key, a stop key, an AMS key, a fast forward key, a fast rewind key, etc. are provided.
Supplied to The display unit 20 is configured by, for example, a liquid crystal display, and performs an operation of displaying an operation state, a track number, time information, and the like based on the control of the system controller 11.

2. Configuration of Encoder / Decoder Unit FIG. 2 is a block diagram showing a configuration of a main part as the decoder unit 8 in the encoder / decoder unit 8 of FIG. This decoder section 8 performs EFM demodulation and A
It performs CIRC decoding and outputs data. The reproduction RF signal (EFM signal) from the RF amplifier 7 is converted to a binarization circuit 5
The EFM demodulation unit 5 binarizes the signal with a 1
3 for EFM demodulation. That is, 14-8 conversion is performed. The output of the binarization circuit 51 is supplied to a PLL circuit 54, and a clock synchronized with the EFM signal is generated by the PLL circuit 54.

The sync detector 55 detects a frame sync of the EFM signal. Then, as will be described later with reference to FIG. 3, the same frame sync pattern is detected in the data due to the effect of dropout or jitter, or the original frame sync is not detected. Window protection and frame sync pattern interpolation processing. If the frame sync pattern is not properly detected for a certain period, the window protection and the interpolation process of the frame sync pattern are stopped, and a process for resynchronization is executed. The present embodiment is configured to execute resynchronization processing at a predetermined timing in a linking area based on a signal FC · GTOP output from a linking processing timing generator (hereinafter, referred to as linking processing TG) 72 described later. You. The register 52 operates according to the output of the sync detector 55.

The data demodulated by the EFM demodulation unit 53 is taken into the RAM 58 via the bus 57. The address generator 59 generates a write / read address in response to various requests output from the multiplexers 62 and 67. Write base counter 60 and read base counter 61
Are selected by the multiplexer 62 and supplied to the address generator 59. The outputs of the RAM write request generator 64, the RAM read request generator 65, and the C1 / C2 request generator 66 are selected by the multiplexer 67 and supplied to the address generator 59.

The write base counter 60 and the read base counter 61 count on a frame basis, and the write base counter 60 is used to write the EFM demodulated data into the RAM 58. The light base counter 60 counts the frame syncs detected by the sync detector 55. The RAM write request generator 64
Generates a write request in accordance with the frame sync detected by the sync detector 55. That is, the write operation to the RAM 58 is executed by the PLL clock synchronized with the EFM signal.

A read base counter 61 is a timing generator 56 for generating a stable clock of a crystal system.
Count clocks from The clock from the timing generator 56 is also supplied to the RAM read request generator 65 and the C1 / C2 request generator 66, and a request signal is generated in response thereto. Therefore, the reading operation from the RAM 58 is executed by the stabilizing clock. The clock of the PLL system synchronized with the EFM signal includes the disturbance of the disk rotation servo. By reading the data from the RAM 58 with the stabilizing clock, the RAM 58 performs the time axis correction. In the present embodiment, the linking process TG72
Control of the RAM 58
Reset control can be performed, and the RAM reset control sets the write base counter 60 to be at the center of the jitter margin.

Note that there is a limit to the time axis correction due to the capacity of the RAM 58. For example, if the difference between the write base counter 60 and the read base counter 61 exceeds ± 5 frames, other data is destroyed, and the reproduced sound is guaranteed. Can not. Therefore, the count value is monitored by the base counter monitor 63, and when the difference between the write base counter 60 and the read base counter 61 exceeds ± 4 frames, the value of the read base counter 61 is set to the write base counter 60. ing.

The ECC processing section 68 performs error correction on the EFM decoded data stored in the RAM 58. In this embodiment, ACIRC (Advanced
Interleave + CIRC), and performs error correction using the C1 sequence and the C2 sequence as described later. Further, in the present embodiment, at least the position of the linking point at which the data is
Prohibition / C1PC processing is executed. In other words, by performing only error correction using the C1 sequence and not performing error correction using the C2 sequence, a maximum of one interleave length before and after a discontinuity point of data (108 frames in the case of a mini-disc system is equivalent to 108 frames). ) Are prevented from spreading. In the present embodiment, the start / end timing of the C2 prohibition / C1PC process is also controlled by the linking process TG72.

The controller interface 69 transmits and receives control signals and the like from the system controller 11 shown in FIG. 70 is a register, 71 is an output control unit, and outputs audio data on which EFM demodulation and C1, C2 sequence error correction have been performed. This output is sent to the buffer RAM by the memory controller 12 of FIG.
13 is written.

In this embodiment, the address decoder 10 outputs a signal FD / START indicating the timing of the start position of the sector "FD". This signal FD / START is output to the address decoder 1
This is generated based on the ADIP sink obtained at 0, which will be described later with reference to FIG. Then, in the linking process TG72 in the decoder unit 8, the signal ROF corresponding to the RAM reset timing and the sync protection window are forcibly released to capture the frame sync based on the input signal FD / START. Synchronous) signal FC / GT for obtaining timing
The OP is output, which will be described later with reference to FIG.

The signal ROF is branched and supplied to the base counter monitor 63 and the ECC processing section 68 as shown in FIG. Then, the base counter monitor 63 performs an operation (RAM reset) for setting the value of the write base counter 60 to the center of the jitter margin in response to the signal ROF. Further, the ECC processing unit 68 of the present embodiment is configured to generate appropriate C2 prohibition / C1PC processing start / end timing as linking processing based on the input signal ROF (see FIG. 14). See below).

The signal FC · GTOP output from the linking process TG 72 is input to the sync detector 55, and performs resynchronization operation at a timing obtained based on the signal FC · GTOP.

3. Linking process of the present embodiment 3-a Resynchronization process Hereinafter, a linking process that is a feature of the present embodiment will be described. The linking process refers to performing the resynchronization process, the RAM reset, and the C2 inhibition / C1PC process at the timing of the linking area, as described above.
Each of the C2 prohibition / C1PC processing will be briefly described, and first, the resynchronization processing will be briefly described.

The resynchronization process is performed in the sync detector 55 as described with reference to FIG. Here, a general operation of the resynchronization processing will be described with reference to a timing chart of FIG. FIG. 3A shows data input to the decoder unit 8 together with a frame sync. The sync detector 55 detects the frame sync shown in FIG. 3A as a detection sync (FIG. 3B),
An interpolation pulse (FIG. 3) is reset by resetting an interpolation counter (not shown) at the timing of the detection sync.
(C)) is generated (interpolation processing). A window timing signal shown in FIG. 3D is generated corresponding to the timing of the interpolation pulse. FIG. 3 (f)
The window signal shown in (1) corresponds to the window timing signal in principle. When it is determined that the timing signal of the interpolation pulse is synchronized with the detection sync, the window protection signal W shown in FIG.
NDLK goes high, thereby providing window protection. In this state, only the detection sink obtained during the period (within the window) during which the window signal shown in FIG. 3F is H (in the window) is valid as the reset of the interpolation counter, and the detection sink outside the window is invalid. Handled (window protection). In this case, although a shift of the frame sync and No Sync (a state in which no frame sync is detected) have occurred in the input data, it is considered that they are synchronized because the interpolation pulse is within the window.

In this figure, the detection syncs at the positions indicated by arrows A and B are out of the window due to, for example, a track jump. When the asynchronous state is detected in this manner, the sync detection unit 55, FIG.
As shown in the period T1 of (e), the window protection signal WN
Let DLK be L. As a result, the window protection is released, and the gate is opened regardless of the window timing (FIG. 3D) as shown in a period T2 in FIG. 3F. In such a period during which the gate is opened, all the detection sinks obtained during this period are valid, and the reset of the interpolation counter is urged. In this embodiment, newly obtaining synchronization between the input signal and the decoder by releasing the window protection for detecting the frame sync and opening the gate in this manner is referred to as resynchronization processing.

As described above, the continuity of the frame sync cannot be obtained at the data discontinuity point of the linking point. Therefore, in the present embodiment, as one of the linking processes, the resynchronization process is executed at a predetermined timing after the passing of the linking point.

3-b RAM Reset Next, as linking processing in the decoder section 8 shown in FIG. 2, a reset operation (RAM reset) for the RAM 58 will be schematically described with reference to FIG. The actual RAM reset start timing will be described later with reference to FIG.

FIG. 4 shows an EFM signal input, an ADIP sync,
Output decoded signal and its main data sink,
9 shows a C2 correction NG window. In this case, the decoding delay is set to 132 EFM frames. The ADIP sync is a synchronization signal in sector units obtained based on the ADIP signal extracted by the address decoder 10.
In this embodiment, as described with reference to FIG. 17, sectors "FC", "FD", and "FE" are defined as linking areas in which dummy data is written, and "FF" is a sub-data. Defined as an area.

The RAM reset is performed at the timing of the linking point LP which is the center position of the sector of "FD". However, in practice, other linking processing (resynchronization and C2 inhibition / C1
In consideration of the balance with the operation timing with the PC, the margin of the operation timing, and the like, the program is executed with a predetermined timing delay from the position set as the linking point LP. RAM reset refers to the write base counter 60
Is forcibly reset to the center of the jitter margin, whereby the jitter margin is always set to the maximum state for each cluster.

As described above, by performing the RAM reset at the timing of the linking point LP in the linking area “FC”, the write data of the sector FD for the EFM input signal becomes discontinuous. If normal error correction processing using the C1 sequence and the C2 sequence including the discontinuity is performed,
Since two-series error correction results in an error, a C2 correction NG window stands around the sector FD for the decoded signal.

However, the range of the C2 correction NG is RA
Interleave length before and after the M reset point (108
As shown in the figure, the sector (“FC”) of the linking area where dummy data is recorded
"FE"). Therefore, the RAM reset does not affect the decoding processing of the main data sectors (00 to 1F) in which actual audio data and the like are recorded and the sub-data sector FF. As described above, by performing the RAM reset at the predetermined timing in the linking area, it is possible to prevent the RAM 58 from overflowing during the reproduction of the main data sector.

However, in the present embodiment, as described later, C2 inhibition / C1P
C processing is performed, so that an area where an error correction error occurs in the linking area is minimized.

3-c C2 Prohibition / C1PC Process Next, the C2 prohibition / C1PC process will be described with reference to FIGS.
The operation of the 2 prohibition / C1PC process will be described. As described above, the ACIRC is used as the error correction code in the mini disc system.

As data to be EFM-demodulated in the EFM demodulation circuit 53 shown in FIG. 2 and stored in the RAM 58, each byte (symbol) is represented by (mn) (m: frame number, n: byte unit in a frame). 5A), the signal is repeated in units of 32 bytes = 1 frame as shown in FIG. 5A. Then, the ECC processing unit 68 rearranges the data on a byte-by-byte basis on the RAM 58 and executes error detection and correction processing using the C1 sequence and the C2 sequence, as shown in FIG. 5B.

The C1 sequence corresponds to a 32-byte data unit for each column in the vertical direction shown in FIG. 5B. For example, in the rightmost column in the vertical direction in FIG. 5B, (1.1)
(1.2) (1.3) ... (1n) ... (1.3)
0) (1.31) (1 · 32) 32-byte data is 1
The unit is the C1 series. Of these 32 bytes, the lower 4 bytes (1 · 29) (1 · 30) (1.3)
1) (1.32) is the parity P of the C1 sequence, and the remaining 28 bytes of data are actual audio data. This C1 sequence enables error detection and correction of 2 bytes.

The C2 sequence is obtained by obliquely taking one byte (one of the data of one frame excluding the parity P) in one frame of every four frames out of the data taken in the past. . For example, FIG.
In the case of (b), (-103.1) (-99.2) (-9
5.3) ... (-107 + 4n.n) ... (-3.
27) 28 bytes of (1 · 28) form a C2 sequence of one unit. Also in this case, 4 bytes of the 28 bytes are the parity Q of the C2 sequence, and the remaining 24 bytes of data are actual audio data. And this C2
Depending on the sequence, error detection and correction of 2 bytes can be performed. When an error pointer indicating the error detection result of the C1 sequence is used, erasure correction of up to 4 bytes can be performed.

Next, as the error correction using the C1 sequence and the C1 sequence, an error correction process including a C2 prohibition / C1PC process, which is a feature of the present embodiment, will be described with reference to flowcharts of FIGS. explain. This processing operation is executed by the ECC processing unit 68 shown in FIG.

First, the ECC processing section 68 executes step S1
In 01, parity calculation is performed on the data of the C1 sequence of 32 bytes per frame (see FIG. 5), and in the following step S102, it is determined whether or not an error exists in the data of the C1 sequence. If it is determined in step S102 that there is no error, the process proceeds to step S103, and a pointer indicating the presence or absence of an error for each of the 28 data bytes is set as follows.
"OK", that is, data for which no error exists, is set, and the process proceeds to step S107.

On the other hand, if it is determined in step S102 that an error exists, the process proceeds to step S1.
Proceeding to 04, it is determined whether or not the number of errors in the C1 sequence is equal to or less than the number of errors that can be corrected. If it is determined that the number of errors is equal to or less than the number of correctable errors (that is, the number of errors is equal to or less than 2 bytes), step S105
After correcting the error, the process proceeds to step S103. If it is determined in step S104 that the number of errors in the C1 sequence is equal to or greater than the number of errors that can be corrected, the process proceeds to step S106, and “NG”, that is, “NG” for all the pointers of the 28 bytes Data indicating an error correction error is set, and the flow advances to step S107.

In step S107, C2 inhibition /
It is determined whether there is a request for the C1PC process. In the present embodiment, at least the request for the C2 inhibition / C1PC processing as the linking processing is made based on the signal ROF (RAM) input to the ECC processing unit 68 as described later.
(Corresponding to the reset timing) based on a flag FL · C1PC for C2 inhibition / C1PC request generated at a predetermined timing.

If it is determined in step S107 that there is no request for the C2 prohibition / C1PC process,
Go to step S108. In step S108, C2
A parity calculation based on the sequence is executed, and step S109 is performed.
It is determined whether or not there is an error in the C2 sequence. If it is determined in step S109 that there is no error in the C2 sequence, the process proceeds to step S110,
Data indicating OK (no error) is set as a pointer for each of the 24 data bytes in the C2 sequence. On the other hand, if it is determined in step S109 that there is an error, the process proceeds to step S111.
To determine whether the number E of errors in the C2 sequence is equal to or less than the number m of correctable errors (E ≦ m). In the case of this example, the number m of errors that can be corrected from performing erasure correction is up to 4 bytes (m = 4).

In step S111, if the number E of errors in the C2 sequence is equal to or less than the number m of correctable errors,
Proceeding from step S111 to step S112, the error result (that is, the state of the pointer) obtained by the error correction processing of the C1 sequence is compared with the calculation result (the number of errors) of the C2 sequence. Then, in the subsequent step S113, it is determined whether or not the two match (the number of errors matches) based on the result of the comparison.

Steps S112 and S11
Reference numeral 3 denotes a function for detecting an erroneous correction in a normal error correction process. For example, a process for preventing an improper operation such as erroneously detecting data having no correct error as an error and performing an erroneous correction process. It is.

Then, in step S113, C1
If it is determined that the error results (the number of errors) of the sequence and the C2 sequence match, the process proceeds to step S114 to execute an error correction process using the C2 sequence, and then proceeds to step S110. On the other hand, in step S113, C1
If it is determined that the error results of the sequence and the C2 sequence do not match, the process proceeds to step S114, and “N” is set for each pointer corresponding to the 24-byte data of the C2 sequence.
G "is set.

In step S111, the number E of errors in the C2 sequence is larger than the number m of correctable errors (E
> M), the process proceeds to step S116. In step S116, reference is made to the pointer of the error detection result of the C1 sequence for each byte in the C2 sequence. Then, the number of pointers n _NG indicating “NG” for byte data of the C1 series in the C2 series
Is determined whether the number of errors is greater than the number m of errors that can be corrected by the C2 sequence (n _NG > m). Step S11
In step 6, when it is determined that n _NG > m is not satisfied with respect to the number n _NG of C1 pointers, the number of detected errors of the C1 sequence or C
It is estimated that at least one of the two series of detection errors is incorrect. Therefore, in this case, the process proceeds from step S116 to step S115, in which data indicating "NG" is set for each pointer corresponding to 24-byte data of the C2 sequence. On the other hand, in step S116, the number of C1 pointers n _NG is n
If it is determined that _NG > m, it is considered that the number of errors detected by the calculation result of the C1 sequence matches the number of errors detected by the calculation result of the C2 sequence. In this case, the process proceeds to step S117, and data indicating “OK” or “NG” is set and output to the pointer of C2 according to the result of the pointer of C1. In the process in step S117, since the result of the pointer of the C1 series performed earlier is copied to the pointer of C2, the process of step S117 is C1 pointer copy (C1PC).
Processing.

The error correction processing described so far is an error correction processing when there is no C2 inhibition / C1PC processing request in step S107. That is, the error correction process is performed by both the normal C1 sequence and the normal C2 sequence.

On the other hand, if it is determined in step S107 that a C2 prohibition / C1PC process request has been made, the process immediately proceeds to step S117 to execute a C1 pointer copy process. That is, according to the present embodiment, for example, C2 inhibition /
When the C1PC processing request is issued, the C1 sequence error correction is performed, but the C2 sequence error correction is not performed (that is, the process started from step S108 is not performed), and the C1 pointer copy process is forcibly performed. Is to run.

For example, in a state where data becomes a discontinuous point as in the above linking point, first, FIG.
As described in (b), in a state where the data is rearranged on the RAM 58 in byte units, the rearranged data in the RAM 58 is schematically shown as in FIG. In FIG. 8A, the data after the discontinuity point is indicated by oblique lines. Then, even in such a state, it is assumed that error correction by the C1 and C2 sequences is performed as usual. That is, it is assumed that the determination processing in step S107 is omitted, and the parity calculation of the C2 sequence is always performed in step S108 following the processing in steps S103 and S107. In this case, the error detection result is as shown in FIG. For example, when an abnormal state occurs where a discontinuous point of data occurs, the clocks of the data before and after the discontinuous point become asynchronous, so that the PLL for reproduction clock synchronization is unlocked and the like. As shown in (1), a continuous error for C1 is inevitable over a section of about 5 to 10 frames from the discontinuity point. Then, assuming that the parity calculation based on the C2 sequence is performed on such a C1 sequence, a C2 sequence unit S1 (circles indicate data bytes included in the C2 sequence) shown in FIG. For the C2 sequence, there is no particular problem because the number of errors during normal operation is treated as 1 or 2. Even if there is an error that cannot be corrected, appropriate processing such as interpolation is executed.

However, C2 shown in the system S2 of FIG.
In the case of a sequence, the number of errors in the parity calculation result of C2 is 2, even if no error actually exists in a region other than the C1 error region of about 5 to 10 frames shown in FIG. According to the parity calculation result of C2, one byte data (byte data indicated by arrow B) after the discontinuous point is added to C2 in addition to the two error numbers due to the C1 sequence.
Is included as the number of errors due to the sequence, so that 3 is detected as the number of errors. In this case, the processing of steps S112 and S113 shown in FIG.
Since it is determined that the number of error detections does not match the C2 sequence of the sequence, all data (24 bytes) of the C2 sequence are regarded as errors by the processing of step S115. In other words, in an abnormal state where a discontinuity of data occurs, by executing error correction using the C2 sequence, data that should be correct other than the C1 error area is also output as an error. And
The state in which all the byte data of the C2 series as described above is regarded as an error continues up to the C2 series shown by the system S4 in FIG. 8B, and as a result, a continuous error is output over 100 frames or more. Will be done.

Therefore, as in the present embodiment, step S
107 → C2 realized by the processing of step S117
By performing the prohibition / C1PC processing, it becomes possible to eliminate the error of the C1 series in which the error correction error is inevitable at the timing of the data discontinuity point such as the linking point, and the appropriate data decoding processing can be promptly performed. It is possible to return.

Incidentally, as described so far, step S
In the case where there is a C2 prohibition / C1PC processing request described in 107, the timing of a data discontinuity point at the linking point is described.
The C1PC process is performed by, for example, a disturbance such as some disturbance.
It is as if the frame sync could not be properly and continuously obtained for some reason other than the case where the overflow or underflow of the RAM 58 occurred during the decoding of the main data, the case where the track jump was performed, and the linking point other than the linking point. In this case, it is effective because the error area for error correction can be limited to the C1 sequence. Therefore, also in the present embodiment, when the above abnormal state occurs, C2 inhibition / C1P
If the configuration is made so that the C processing request is generated, the period during which the main data is in error can be shortened, so that stable reproduction can be performed.

3-d Timing of C2 Prohibition / C1PC Process in Linking Process Next, the start / end timing of the C2 prohibition / C1PC process as the linking process which is a feature of the present embodiment will be described with reference to FIGS. To consider. Here, for the sake of convenience of explanation, it is considered based on the timing of data read from the RAM 58.

FIG. 9 schematically shows the position of the sector data (RAM data) written in the RAM 58 and the state of the data (here, DAread) read from the RAM 58 corresponding to the position. .
As the sector data, a linking area of “FC”, “FD”, and “FE” and a sub data area of “FF” are shown. The linking point LP is located at the center of the sector "FD" as described above.

As can be seen from the above description, the C2 prohibition / C1PC process is performed on data to be corrected by the C2 sequence. Therefore, for example, C2 prohibited / C1PC
Assuming that the processing is performed over the xxx frame at the timing shown in FIG. 9, the data affected by the C2 prohibition / C1PC processing includes the data for the xxx frame on which the C2 prohibition / C1PC processing is performed, and the C2 prohibition / C1PC
Xxx + 10 after adding 108 frames after processing is completed
The data becomes DA read data for eight frames. In addition,
108 frames correspond to one interleave length. In this figure, the data of the series of DA read0 is C
This is the first C1 sequence affected by the 2 prohibition / C1PC process, and all the byte data of the DA read1 sequence data is subjected to the C2 prohibition / C1PC process. The DA read2 sequence is the last C1 sequence including byte data that has been subjected to C2 inhibition / C1PC processing.

As described above with reference to FIG.
By performing C2 prohibition / C1PC processing for frames, xxx + 1 from the start position of C2 prohibition / C1PC processing
Based on the fact that DA read data over 08 frames is affected by C2 prohibition / C1PC processing,
Thereafter, C2 inhibition / C1P in the actual linking process
The setting of the start / end timing of the C processing will be described. First, the start timing of the C2 inhibition / C1PC processing will be described with reference to FIG.

FIG. 10A shows the case where the start timing is too early as the C2 prohibition / C1PC process in the linking process. In this figure, the C2 prohibition / C1PC processing is performed in the sector "F" of the linking area.
The data is started from the part after the sector “1F” of the main data before “C”. In this case, the data of the DA read series after the sector “1F” of the main data is C2 series. Will not be executed. Since this leads to a decrease in the reliability of the main data of the sector “1F”, it is understood that this is not preferable as the start timing of the C2 inhibition / C1PC process.

FIG. 10B shows the case where the start timing of the C2 inhibition / C1PC process is too late.
In this case, the error data due to the influence of the discontinuity at the linking point LP (a plurality of ×
(Indicated by a mark)), error correction by the C2 sequence is performed. That is, if the error data is C
It will be scattered by two lines.

FIG. 10C shows a case where the start timing of the C2 prohibition / C1PC process is proper. In this case, the C1 prohibition / C1PC processing is not performed on the C1 sequence of the sector "1F" of the main data, and the error data at the discontinuous point at the linking point LP is corrected by the C2 sequence. The start timing that satisfies these two conditions is an appropriate timing.

Next, the end timing of the C2 prohibition / C1PC process in the linking process will be described with reference to FIG. FIG. 11A shows a case where the end timing is too early. If the end timing of the C2 prohibition / C1PC process is too early in this way, the C2 prohibition / C1PC process process on the error data at the discontinuous point of the linking point LP indicated by the mark X does not reach, and the error correction by the C2 sequence is executed. There is data to be executed, and error data is scattered by the C2 sequence. FIG. 11B shows a case where the end timing is too late. In this state, the C2 prohibition / C1PC process is applied to the first part of the sub-data sector “FF”, and the C2 correction is not performed on the sub-data. Only the reliability of the data will be lost. FIG. 11 (c)
Indicates that the end timing is appropriate. In this state, the C2 inhibit / C1PC process is performed for all error data at discontinuous points of the linking point LP, and the C2 inhibit / C1PC process does not reach the sub data sector "FF". In this case as well, the end timing satisfying these two conditions is the appropriate end timing.

As described above, the C2 prohibition / C1PC processing as the linking processing in the present embodiment is the same as that shown in FIG.
0 and the start timing and the end timing are required to satisfy the conditions described in FIG. In addition to this,
The resynchronization and the RAM reset, which are other linking processes, may be performed at a timing after the linking point LP corresponding to the data read from the disk has passed to some extent. After EFM demodulation and reading out from the RAM 58, it is necessary to set in consideration of a time difference until the error is corrected by the C2 sequence (this is called a decoder delay).

3-e Timing Control of Linking Process Next, the linking process (re-synchronization,
Examples of execution timings of RAM reset and C2 inhibition / C1PC processing will be described with reference to the timing chart of FIG. FIG. 12A shows that the ADIP sink is assigned to a sector (“FC”, “FD”, “FE”, “F”).
F "," 00 "). In the mini disc system, one sector is formed by 98 frames. In the present embodiment, in the decoder unit 8 based on the ADIP sync,
The signal FD • START shown in FIG. As can be seen from FIG. 12B, this signal FD • START is used as the timing of the ADIP sync and the sector “F”
D "during the period" D ".

As described above, in the mini-disc system, the linking point LP is defined as an intermediate position of the sector “FD”. That is, the linking point L
As shown in FIG. 12C, the reference position of P is the position of 49 frames from the start position (time point t1) of the sector “FD”. However, the linking point LP is defined so that a margin of ± 10 frames is given to the reference position shown in FIG.

The resynchronization timing can be set as follows. As the resynchronization operation, after the data discontinuity point of the linking point LP,
Since it is necessary to obtain the frame sync as quickly as possible, the execution is started immediately after the linking point LP. However, in the case where the timing of the linking point LP is the latest, according to the description of FIG. 12C, it is sufficient to add 10 frames to the position of 49 frames from the time point t1 (the reference position of the linking point LP). That is, 49 + 1
0 = 59 (frames), which is the position of 59 frames from the start of the sector “FD”. Therefore, the actual resynchronization timing may be performed immediately after the position of 59 frames from the time point t1. In the present embodiment, in order to ensure the reliability, a margin of 5 frames is further added from here. Add. That is, as shown in FIG. 12D, resynchronization is set at a position of 59 + 5 = 64 frames from time t1. From this point,
As described above, the frame sync protection window is released in the sync detection unit 55, the gate is forcibly opened, and the operation of capturing the frame sync is started.

The RAM reset is started with a margin of 5 frames from the position of 64 frames from the time point t1, which is the timing of the resynchronization. That is, FIG.
As shown in FIG. 2 (e), the process starts from the position of 69 frames from the time point t1.

The C2 prohibition / C1PC process is performed as shown in FIG.
As shown in FIG. 2 (g), the operation is started from the position of 69 frames from the same time t1 as the above-mentioned RAM reset.

The end timing of the C2 prohibition / C1PC processing is, as can be understood from the above description with reference to FIGS. 9 and 12, D which is data read from the RAM 58.
Linking point L on Area (FIG. 12 (j))
The process may be terminated immediately after the passage of P (shown in FIG. 12 (f)). From this, a decoder delay (132 frames) was added to 59 frames from time t1, which is the latest case of the linking point LP corresponding to the ADIP sink in FIG. 12A, and a frame jitter margin of 5 frames was further added. , C2 inhibition / C at the timing of 196 frames (= 59 + 132 + 5) from time t1
In this embodiment, it is set that the C2 inhibition / C1PC process is terminated at a position of 200 frames from the time point t1 where a margin of 4 frames is given to the 196 frames (FIG. 12
(G)). Accordingly, the C2 prohibition / C1PC process is performed at the time t1.
It is set to be executed from the position of 69 frames to the period of 131 frames.

The period of the data DA read affected by the C2 prohibition / C1PC processing extends from the start of the C2 prohibition / C1PC processing to 108 frames after the end as described with reference to FIG. Therefore, in this case, as shown in FIG. 12H, the time spans from the time point t1 to (131 + 108 frames). Therefore, the end of the DA read period of the data affected by the C2 prohibition / C1PC processing is 308 frames from the time point t1.

Here, since the error correction processing is performed on the data stored in the RAM 58 as described with reference to FIG. 9, in the case of FIG. 12, R shown in FIG.
It can be seen that the read operation is performed on DA read which is read data from the AM 58. This FIG.
The DA read (sector) shown in FIG.
The data at the timing shown in FIG.
The timing is delayed by a decoder delay for 32 frames (FIG. 12 (i)).

Therefore, C2 inhibition / C shown in FIG.
A period during which the data processed by 1PC is DA read;
Comparing with the data DA read shown in FIG. 12 (j), the DA read of the data subjected to the C2 prohibition / C1PC processing is compared.
The start position of ad (69 frames from time t1) is shown in FIG.
It starts from the sector “FC” of the DA read of 2 (j) (the position of the 35th frame of the sector “FC”). Therefore, even if the frame jitter margin is considered, the start position of the DA read of the data subjected to the C2 prohibition / C1PC processing is the DA read.
Will certainly fit in the sector "FC", and will not affect the sector "1F" immediately before. Also, the linking point L on the DA read in FIG.
The distance to P is 112 frames, and C2 inhibition / C
1PC processing will not be missed. That is, FIG.
The request for the start timing of the C2 prohibition / C1PC process described in (1) is satisfied.

Next, looking at the end timing of the C2 prohibition / C1PC process, the DA read shown in FIG.
Since the 18 frames have passed from the linking point LP, the C2 prohibition / C1PC process is not removed from the discontinuous data sequence at the linking point LP.

Also, the end of the DA read period of the data subjected to the C2 inhibition / C1PC processing (see FIG. 12 (h))
In the present embodiment, the relationship between the DA read and the timing of the start position of the sector “FF” is as follows. The start position of the sector “FF” of the DA read can be obtained as shown in FIG. In other words, DA read sector "FF"
Is obtained by adding 196 (= 49 × 2) frames corresponding to two sectors of sectors “FD” and “FE” to a decoder delay of 132 frames, starting from time t1, 328 (=
132 + 196) frame position.

By the way, the timing described so far is obtained based on the ADIP sync shown in FIG.
Is actually based on the rising timing of the signal FD.START, but actually, there is a possibility that a "deviation" occurs between the data position based on the ADIP sync and the data position recorded on the disk. The amount of shift is defined as, for example, -10 and +26 frames as an allowable range. Therefore, DA read
As shown in FIG. 12 (k), the start position of the sector “FF” is 318 (= 328−1) obtained by subtracting 10 frames from the 328 frame that is the start position of the normal “FF”.
0) The position of the frame is the earliest as the start position timing of “FF”. In the present embodiment, by taking a further 5 frame margin, the position of the 313 (= 318-5) frame from time t1 is regarded as the earliest case as the start position timing of the sector "FF". I do.

According to FIG. 12H, the end position of the DAread affected by the C2 inhibition / C1PC process is 308 frames from the time point t1, which is the earliest in the sector "FF". It will be located 5 frames before the 313 frame regarded as the start position. In other words, the influence of the C2 prohibition / C1PC process is set so as not to affect the sector "FF" which is a sub data area. Thus, C2 inhibition / C shown in FIG.
The end timing of the 1PC process also satisfies the condition described with reference to FIG. 11 and is set to be appropriate.

3-f Circuit Configuration for Realizing Linking Process Next, referring to FIGS. 13 to 16 for the circuit configuration for realizing the linking process of the present embodiment described with reference to the timing chart of FIG. I will explain.

FIG. 13 shows a signal FD / START in the address decoder 10 based on the ADIP sync.
FIG. 3 is a block diagram illustrating a configuration of a circuit unit for generating and outputting a. The internal configuration of the address decoder 10 shown in FIG.
CRC check circuit 103, AND gate 104, 10
6 and flip-flops 105 and 107. The operation clock SCK is a clock synchronized with the EFM signal generated by the PLL circuit 54.

In this figure, the ADIP sync is supplied to the shift register 101 and the CRC check circuit 103. For example, the shift register 101 supplies the input ADIP sink to the decoder 102. In this case, the decoder 102 analyzes the input ADIP sink, and in this case, the signal ADIP · 1F which becomes H during the period of the sector “1F” and the subsequent sector “F”
A signal ADIP · FC which becomes H during the period “C” is generated and output. Also, the CRC check circuit 103 checks whether the input ADIP sink actually matches the sector number to be supported, and when a detection result indicating that the two match is obtained, the check signal CRCF is set to the H level. Is output by Note that the signal C
RCCL is a signal for clearing the operation result of the CRC check circuit 103, and is supplied to the CRC check circuit 103 at the timing of each sector break. This signal CRCCL is also supplied to the flip-flop 105,
107 is also inverted and input as an enable signal.

The signal ADIP ·
A signal CRCF that has been checked for 1F and sector “1F” is input. Therefore, sector "1F"
Is high, the AND gate 104 outputs an H level to the flip-flop 105. As a result, the flip-flop 105 outputs the H level for a period of one sector (at the same timing as the signal ADIP.FC).

The AND gate 106 outputs the output of the flip-flop 105, the signal ADIP.FC and the signal CRCF.
And the logical product of Therefore, if the ADIP signal corresponding to the sector “FC” is appropriate, the H level is output from the AND gate 104 to the flip-flop 107. Thereby, the signal A is output from the flip-flop 107.
An H level signal is output over a period corresponding to one sector after DIP / FC. This becomes a signal FD • START corresponding to the timing of the data of the sector “FD” supplied to the decoder unit 8.

That is, the circuit block shown in FIG. 13 includes two sectors “1” located immediately before sector “FD”.
After confirming the continuity of “F” and “FD”, the signal FD ・ S
It is configured to output TART, whereby, for example, a sector that is not actually the sector “FD” is erroneously recognized as the sector “FD” and the linking process is executed at careless timing. Such inconveniences are prevented.

FIG. 14 is a block diagram showing a configuration example of the linking process TG72. From the linking process TG72, as described above, the signals FC / GTOP and RAM reset for instructing the timing (FIG. 12D) for performing resynchronization (forcible gate open) as the linking process based on the signal FD / START. 12E is generated and output.

The rising edge detecting circuit 1 shown in FIG.
Reference numeral 10 denotes a signal (FD · START), which detects the rising edge of the signal, and outputs a detection signal to a counter (7 bits) 111.
Input to the load terminal. Thereby, the counter 111
Loads the value 0 to all bits at the rising timing of the signal FD.START. Counter 111
Is output to the decoder 115.

The clock RFCK is a read clock of the RTAM 58 of the read base counter 61 (see FIG. 2), and is obtained by dividing the frequency of the clock LRCK of the crystal timing generator 56 at a predetermined ratio. The rising edge of the clock RFCK is detected by the rising edge detection circuit 112, and the detection output is input to the AND gate 113. AND gate 113
Takes the logical product of the rising timing of the clock RFCK and the signal S2 via the inverter 114, and inputs the output to the carry-in of the counter 111. As a result, the counter 111
It operates so as to count up at every rising edge of.

Then, the value of 64 (4
0h), the signal S1 (H level) is output from the decoder 115. The rising edge of the signal S1 is detected by the rising edge detection circuit 116, and the output is supplied to the width expansion circuit 117. Width expansion circuit 117
Then, the detection pulse signal of the edge detection circuit 116 is expanded to twice the width of the reproduction clock SCK and output to the AND gate 118. The output of the width expansion circuit 117 and the inverted link-off signal LINKOFF are input to the AND gate 118. The link-off signal LINKOFF is a signal supplied as an H level when the linking process in the decoder unit 8 is set not to be performed. Therefore, if the linking process is enabled, the width expansion circuit 1
17 outputs the signal FC ·
It will be output as GTOP. Then, in the sync detecting section 55, the input signal FC · GTOP
, A signal GTOP for resynchronization is generated as described later with reference to FIG.

It should be noted that the signal FC ·
The reason why the width expansion of the GTOP is performed as described above is that the block that generates the signal GTOP for resynchronization in the sync detection unit 55 is actually one block of the reproduction clock SCK.
Clock PCK that is slower than one clock and faster than two clocks
By operating based on Thus, by making the pulse width of the signal FC · GTOP twice the width of the reproduction clock SCK, it is possible to prevent a detection error of the signal FC · GTOP. Then, in the sync detecting section 55, based on the input signal FC • GTOP, FIG.
The resynchronization process is executed by generating a signal GTOP as described later.

Further, the value of 69 (45
After counting up to h), the signal S2 is output from the decoder 115 at the H level. The rising edge of the signal S2 is detected by the rising edge detection circuit 119, and the signal S2 is input to the AND gate 118. Again, AND gate 11
Reference numeral 8 denotes a logical AND between the output of the rising edge detection circuit 119 and the inverted link-off signal LINKOFF.
The signal ROF is output from the gate 118.
At this time, when the signal S2 becomes H level, AND
The output of the gate 113 becomes L level, and the counting operation of the counter 11 is stopped. The signal ROF is branched and supplied to the base counter monitor 63 and the ECC processing unit. In response to the signal ROF, the base counter monitor 63 performs an operation of resetting the write timing of the write base counter 60 so that the jitter margin of the RAM 58 becomes the center. That is, a RAM reset is performed. In addition, the ECC processing unit 68 executes the C2 prohibition / C1PC processing at the timing shown in FIG. 12G based on the input signal ROF.

FIG. 15 shows a signal RO in the ECC processing unit.
C2 prohibited for 131 frame periods based on F /
A configuration example of a block for generating a flag FL · C1PC for requesting C1PC processing is shown. The signal ROF is detected at the rising edge by the rising edge detection circuit 131, and the output signal S11 is output to the set terminal of the flip-flop 138 and the counter (8 bits) 13
3 and is input. As a result, the output of the H level is continued from the flip-flop 138. That is, the flag FL · C1PC is generated and C2
The prohibition / C1PC process is started. At the same time, each bit of the counter 133 has a value of 0.
Is loaded. The AND gate 134 receives the clock RFCK via the rising edge detection circuit 132 and the signal S14 from the decoder 136 via the inverter 135. The output signal S13 of the AND gate 134 is input to the carry-in of the counter 133. The signal S14 indicates that the counter 133 has the value 131 (83h).
Is at the L level until the signal S is counted.
12 is the output signal S13 of the AND gate 134. For this reason, the counter 133 starts counting from the time when the signal ROF is input.
The counting up is started at the timing of the clock RFCK.

Then, the value of 13
When counting is performed up to 1 (83h), the decoder 13
6, the signal S14 is output as the H level. When the signal S14 is input to the reset terminal of the flip-flop 138 via the rising edge detection circuit 137, the flag FL · C1P which has been at the H level until now is output.
C changes to L level. That is, the flag FL · C1P
C is a signal that remains at the H level for 131 frame periods after the signal ROF is obtained.
This corresponds to the C2 prohibition / C1PC processing period of (g).

The value of “13” is stored in the counter 133.
When "1" (83h) is counted, the signal S1
4 changes to the H level, the output of the AND gate 134 becomes, and the counting operation of the counter 133 is stopped.

FIG. 16 is a block diagram showing the configuration of a circuit block for executing forced gate open (re-synchronization processing) as linking processing in sync detection section 55. The signal FG · GTOP output from the linking process TG72 as described in FIG. 14 is input to the flip-flop 141. Flip-flop 1
The clock PCK given to 41 has a cycle that is slower than one reproduction clock SCK and faster than two clocks as described above. Therefore, the signal FG / GTOP input to the flip-flop 141 is adjusted to the timing of the clock PCK and input to the set terminal of the flip-flop 142. As a result, the signal GTOP is output from the flip-flop 141 at the H level, but the sync detection unit 55 executes the forced gate open at the timing of the signal GTOP. For example, in the case of FIG. 3, a process for setting the window protection signal to the L level is performed as in a period T1 of FIG.

The OR gate 143 outputs the logical sum of the signal GTOP and the window timing signal described with reference to FIG. 3D as a signal S21. This signal S21 corresponds to the window signal described with reference to FIG. Then, this signal S21 and the detection output of the frame sync detection unit 145 (the detection sync in FIG. 3B) are input to the AND gate 144. Therefore, the AND gate 14
The masked sync MKDSY which is the output of No. 4 corresponds to the frame sync detected in the window. The sync detector 55 synchronizes the input signal with the decoder based on the masked sync MKDSY, and performs the resynchronization operation of the present embodiment during the period when the signal GTOP is at H level. On the other hand, during the period when the signal GTOP is at the L level, the window protection is in effect. For example, the window signal is at the H level as in the period T2 in FIG. Sync (MKDS MKDS)
Only Y) is treated as valid.

Note that the present invention is not limited to the embodiments described above. For example, the timing of the linking process shown in FIG. 12 can be changed according to actual use conditions and the like as long as necessary conditions are satisfied, and the linking process described with reference to FIGS. Other circuit configurations are also conceivable.

[0112]

As described above, according to the present invention, the resynchronization processing, the RAM reset, and the C2 inhibition / C1PC processing (linking processing) are performed at a predetermined timing in the linking area in the sector. In addition, the overflow / underflow of the RAM is prevented while preventing the effect from being exerted on the RAM, so that practically sufficient anti-rolling characteristics and the like can be obtained, and the error cannot be corrected due to the influence of the discontinuity of the data at the linking point. The area can be minimized, and the reliability of the reproduced data can be ensured. In the present invention, the linking process is configured to be executed at a timing generated on the decoder device side without using, for example, an external system controller or the like. In other words, since the execution control of the linking process is completed by the decoder device itself, the reliability of the control timing of the linking process is improved by that much, and the reliability is improved. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a playback device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a decoder according to the present embodiment.

FIG. 3 is a timing chart for explaining an outline of a resynchronization process.

FIG. 4 is a timing chart for explaining an outline of a RAM reset operation.

FIG. 5 is an explanatory diagram for describing an error correction code sequence of an error correction process.

FIG. 6 is a flowchart illustrating an error correction process including a C2 prohibition / C1PC process according to the present embodiment.

FIG. 7 is a flowchart illustrating an error correction process including a C2 prohibition / C1PC process according to the present embodiment.

FIG. 8 is an explanatory diagram for explaining a state of occurrence of an error correction error at a data discontinuity point.

FIG. 9 is an explanatory diagram for describing an outline of C2 prohibition / C1PC processing as linking processing.

FIG. 10: C2 inhibition / C1PC as linking processing
FIG. 9 is an explanatory diagram for explaining a processing start timing.

FIG. 11 shows C2 inhibition / C1PC as linking processing.
FIG. 9 is an explanatory diagram for explaining an end timing of a process.

FIG. 12 is a timing chart showing an execution timing of a linking process in the present embodiment.

FIG. 13 illustrates an address decoder according to the present embodiment.
FIG. 3 is a block diagram showing a configuration example of a circuit part for generating a signal FD / START.

FIG. 14 is a block diagram illustrating a configuration example of a linking process TG according to the present embodiment.

FIG. 15 is a block diagram showing a circuit configuration for generating a signal FL · C1PC for performing a C2 inhibition / C1PC process as a linking process in the ECC processing unit of the present embodiment.

FIG. 16 is a block diagram showing a circuit configuration for generating a signal GTOP for performing resynchronization as linking processing in the sync detector of the present embodiment.

FIG. 17 is an explanatory diagram of a sector structure of a mini disk.

FIG. 18 is an explanatory diagram of a RAM overflow of the decoder.

[Explanation of symbols]

1 disk, 2 spindle motor, 3 optical head, 7 RF amplifier, 8 decoder section, 9 servo circuit,
Reference Signs List 10 address decoder, 11 system controller, 12 memory controller, 13 buffer memory, 14 decoder unit, 51 binarization circuit, 52 register, 53 EFM demodulation unit, 54 PLL circuit, 55
Sync detector, 56 Timing generator, 58
RAM, 59 address generator, 60 write base counter, 61 read base counter, 68 ECC processor, 72 linking TG, 101 shift register, 102, 115, 133 decoder, 103 CR
C check circuit, 105, 107, 138, 141, 1
42 flip-flops, 110, 112, 116, 1
19, 131, 132, 137 Rising edge detection circuit, 111, 133 counter, 117 width extension circuit

Continued on the front page (72) Inventor Hideo Obata 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (3)

[Claims] An EFM demodulation is performed on an EFM signal using a clock synchronized with an input EFM signal, and then the EFM demodulated data is written into a memory means. After reading the data into the memory means, the error correction processing means performs error correction processing on the read data, and as a decoder device for outputting as reproduced data, a frame synchronization signal of all the input EFM signals is synchronized. A re-synchronization process for executing re-synchronization by treating as effective information for resetting; a reset process for executing a reset of a write address so that a jitter margin of the memory unit becomes a center; Error using the error correction code added to the data sequence A linking processing timing generating means configured to execute the error correction prohibition processing for preventing the error correction processing from being executed at a predetermined timing in the linking sector area of the sector of the input EFM signal. Decoder device. 2. The re-synchronization processing and the reset processing based on a sector position indication signal indicating a predetermined position of the linking sector area obtained based on absolute position information read from a recording medium. 2. The decoder according to claim 1, wherein the decoder is configured to generate an execution timing of the error correction prohibition processing. 3. An EFM demodulation is performed on the EFM signal using a clock synchronized with the input EFM signal, and the EFM demodulated data is written into a memory means. After reading the data from the memory means, the error correction processing means performs an error correction process on the read data and outputs the reproduced data as a decoding method. A re-synchronization process for executing re-synchronization by treating as effective information for resetting; a reset process for executing a reset of a write address so that a jitter margin of the memory unit becomes a center; Error using the error correction code added to the data sequence Wherein the error correction prohibition process for preventing the execution of the error correction process is executed at a predetermined timing in a linking sector area of a sector of the input EFM signal.