JPH10301797A - System for writing parity bit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a circuit for holding bits read from a RAM for parity and replacing the held bits with generated parity bits. SOLUTION: A buffer 6 with a gate selects one of 8 output lines constituting a data bus 35 connected with a data base 35 connected with a RAM 2 for parity corresponding to the storage position of a parity bit 12 indicated from a decoder 7 among 8 bits read from the designated address of the RAM 2 for parity based on an output from a decoder 7, controls a gate connected with the output line so that it can be turned on, and transmits the parity bit 12 outputted from a parity generator 3 and held in an incorporated buffer to the output line whose gate is controlled so as to be turned on. A parity data holding part 5 is provided with capacitors 4a-4h whose one edges are grounded and whose other edges are connected with the output lines of the buffer 6 with the gate, and a potential indicating the logical content of the 8 bits read from the RAM 2 for parity is held.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity bit writing system, and more particularly, to a parity configured by using a random access memory capable of storing a plurality of data bits in one address as a random access memory for storing parity bits. It relates to a bit writing method.

[0002]

2. Description of the Related Art In a conventional parity bit writing system of this type, as disclosed in Japanese Patent Application Laid-Open Nos. 61-296438 and 59-200350, for example, data bits and parity bits are stored. The storage means collectively and separately stores a data random access memory (hereinafter referred to as a RAM) for storing data and only one parity bit added to each of the data stored at each address of the data RAM. And a RAM for parity.

The following method is used to store the parity bit in the parity RAM.

Since a plurality of bits can be stored in one address of the parity RAM, a plurality of 1-bit parity bits for each of the above data are grouped in order and stored in one address of the parity RAM. ing. That is, if, for example, 8 bits can be stored in one address of the parity RAM, the parity bits for the eight data are grouped in the order of each data corresponding to the address on the data RAM by 8 bits. Is stored in one address.

When writing data output from a central processing unit (hereinafter referred to as a CPU) to an address specified by the CPU in a data RAM, the data is stored at the address and added to the data. The parity bit is stored in the parity RAM. The address on the parity RAM when the parity bit is stored in the parity RAM is specified by the CPU in correspondence with the address of the data RAM in which the data is written. When the CPU writes data to the data RAM, the CPU also accesses an address on the parity RAM, reads all bits of the address, and temporarily holds the read bits. At this time, there is a case where no parity bit has been written yet in the address from which a plurality of bits have been read, and a case where parity bits have already been written in some bits in some cases. In any case, which of the plurality of bits stored in the address is the bit indicating the position of the parity bit to be newly written depends on the address of the data to be written in the data RAM. Designated by the CPU. That is, the CPU specifies the address of the parity RAM in which the parity bit is written together with the address of the data RAM in which the data is written, and also sets the address of the plurality of storage bits in the address specified on the parity RAM. The number of the parity bit to be written is also specified. The parity bit is written based on the above address specification from the CPU and the bit position specification for writing the parity bit, of the parity bit write destination position among the plurality of bits read from the parity RAM and temporarily stored. The bit to be indicated is selected, and the selected bit is replaced with a parity bit added to the data. After the replacement with the parity bit is completed, the plurality of bits temporarily held until then are replaced by the parity RA.
Writing to the original address of M completes the writing of the parity bit.

Next, the details of the write operation to the data RAM 1 will be described with reference to the drawings.

FIG. 2 is a block diagram showing a configuration of a conventional parity bit writing system. FIG. 3 is similar to FIG.
FIG. 4 is an explanatory diagram showing a storage state of parity bits in a parity RAM shown in FIG.

The parity bit writing method shown in FIG.
This is a parity bit writing method when a data RAM composed of a random access memory and a parity RAM also composed of a random access memory are used.

The parity bit writing system of the present embodiment shown in FIG. 2 employs a CPU 9, an address bus 18a having a bus width of 16 bits, and a data bus 19 having a bus width of 8 bits.
Are connected to the CPU 9 and output from the CPU 9
An 8-bit data RAM 1 for storing 8 bits of data output from the CPU 9 as a data input signal 14 at an address designated by the bit address input signal 13, and an address bus 18 a having a bus width of 16 bits The CPU 9 is connected to an address bus 18b having a bus width of 13 bits (having a bus width of 13 bits at a branch point from the address bus 18a of 16 bits).
1 of 16-bit address input signal output from
At the address specified by the 3-bit address signal,
A parity RAM 2 of 1 address and 8 bits for storing a parity bit 12 generated to be added to the data stored in the data RAM 1 and a data bus 19 having the above bus width of 8 bits are connected to the data bus 19. A parity generator 3 for simultaneously inputting the 8-bit data stored in the RAM 1 and performing a parity operation on the 8-bit data, and outputting the generated parity bits 12, and a 13-bit address bus branched from the address bus 18a An address bus having a 3-bit bus width, which is an extension of the address bus 18b (the 13-bit address bus 18b
(The bus width becomes 3 bits at the branch point connected to AM2.)
18c, which decodes the lower three bits of the address input signal of the address input signal 13 and outputs the parity RAM
In order to indicate which bit position of the 8 bits read from 2 is the storage position of the parity bit added to the data stored in the data RAM 1, the bus width 8 connected to the output side is indicated. A decoder 7 for inverting the logical value of one output line corresponding to the storage position of the parity bit 12 among the eight output lines constituting the bit data bus 22, an output side of the parity generator 3 and a bus width 8 Bit data bus 23, the output side of the decoder 7 is connected to the 8-bit data bus 22, and the write data input side of the parity RAM 2 is connected to the bus width 8.
One of eight output lines constituting a bus whose write bus width to the parity RAM 2 is 8 bits corresponding to the storage position of the parity bit 12 indicated by the decoder 7 and is connected by the data bus 24 of bits. A book is selected, a gate connected to this output line is controlled to be turned on, and a parity bit 12 output from the parity generator 3 and held in a built-in buffer is transmitted to an output line whose gate is controlled to be turned on. The buffer 32 with a gate, which is connected to the output side of the decoder 7 and the data bus 22 having a bus width of 8 bits, is connected to the output side of the read data of the
Bit data bus 25 and connected to the input side of the write data of the parity RAM 2 via the 8-bit data bus 24, and the decoder 7 sends the data to the parity RAM 2 corresponding to the storage position of the parity bit indicated by the decoder 7. The parity RAM 2 is connected to seven output lines other than one of the eight output lines of the data bus 24 for writing.
The gates connected to the seven output lines are turned on in order to transmit the other bits as they are, except for the bit corresponding to the storage position of the parity bit, which has been read from and stored in the built-in buffer. Buffer 33 with gate
It is composed of

FIG. 3 shows that the data RAM 1 has 64 RAMs.
In a K-byte RAM, a parity bit added to data for each byte written in the data RAM 1 is 8K.
An example in which bytes are stored in the parity RAM 2 is shown.

As shown in FIG. 3, the data RAM 1 has an address 26 from an address "0" to an address "FFFF", and each address is from a least significant bit (LSB) 28 to a most significant bit (MSB). ) Up to 29 bits. The parity RAM 2 has an address 27 from an address "0" to an address "1FFF", and each address is composed of 8 bits from the least significant bit 30 to the most significant bit 31. The 1-bit parity for the 8-bit data at the address “0” of the data RAM 1 is stored in the least significant bit 30 of the address “0” of the parity RAM 2. The parity bit for the data at the address "1" of the data RAM 1 is stored in the second bit following the least significant bit 30 of the address "0" of the parity RAM 2, and the parity bit of the address "2" of the data RAM 1 is further stored. The address “0”, “1”,
When the parity bits for the data "2",..., "7" are sequentially stored in eight bits from the least significant bit 30 to the most significant bit 31 of the address "0" of the parity RAM 2, finally The parity bit for the data at the address “FFFF” in the data RAM 1 is stored in the most significant bit of the address “1FFF” in the parity RAM 2.

Next, the operation will be described.

First, the operation of writing data in the data RAM 1 shown in FIG. 1 will be described.

In order to write data to the data RAM 1, an address input signal 13 composed of 16 bits
When the data is input from the PU 9 to the data RAM 1, the data RAM 1 stores the data specified by the address input signal 13 from the addresses from the address "0" to the address "FFFF" shown in FIG. The address of the data RAM 1 is accessed.
At the same time, an address input signal composed of the upper 13 bits of the address input signal 13 is input to the parity RAM 2 and the address input signal causes the parity RAM 2 to store a parity bit added to the data. Is designated and accessed from addresses from address "0" to address "1FFF". At the same time, the lower three bits of the address input signal 13 are input to the decoder 7.

On the other hand, a data input signal 14, which is 8-bit data, is input from the CPU 9 to the data RAM 1. Subsequently, the data RAM write signal 8 is changed to CP.
When the data is input from U9 to the data RAM 1, the data R
Write designation for AM1 is performed, and data RAM
The data input signal 14 is written to the address specified by one address input signal 13. At the same time, since the data input signal 14 is also input to the parity generator 3, the parity generator 3
Parity is calculated for bit data, a parity bit is generated, and output to the gated buffer 32 via the 8-bit data bus 23.

Next, the CPU 9 issues a parity RAM.
The read signal 11 is input to the parity RAM 2.
At this time, the upper 13 bits of the address input signal 13 are already input to the parity RAM 2 in order to store the parity bit added to the data, and are configured by the upper 13 bits of the address input signal 13. Since the address on the parity RAM 2 designated by the CPU 9 is accessed by the address input signal, the least significant bit 3 of the accessed address is input by the input of the parity RAM read signal 11.
Eight bits from 0 to the most significant bit 31 are read and output to the buffer 33 with a gate.

On the other hand, the decoder 7 decodes the address input signal composed of the lower 3 bits of the input address input signal 13 and reads out the address input signal from the parity RAM 2 according to the decoding result, and the gated buffer 33
In order to indicate which bit position of the 8 bits output to is the storage position of the parity bit added to the data stored in the data RAM 1, eight output lines corresponding to the 8 bits are set. The logical value of one output line corresponding to the storage position of the parity bit 12 among the eight output lines is inverted. These eight output lines constitute a data bus 22 having a bus width of 8 bits, and are connected to a buffer 32 with a gate and a buffer 33 with a gate. Notifying the buffer 32 with a gate and the buffer 33 with a gate which bit position of the output 8 bits is the storage position of the parity bit.

The gated buffer 32 is connected to eight output lines constituting the data bus 22 from the decoder 7,
The logical value of one of the output lines is inverted by the decoder 7 to determine which bit position of the 8 bits output to the gated buffer 33 corresponds to the storage position of the parity bit. Shown from Therefore, the buffer with gate 32 stores 8 bits in the parity RAM 2 corresponding to the position of the output line where the logical value is inverted.
One of eight output lines constituting the data bus 24, which is a bit write bus, is selected, a gate connected to this output line is turned on, and the parity generator 3 is turned on.
And sends the parity bit 12 held in a built-in buffer to an output line whose gate is turned on.

The buffer with gate 33 connects one of eight output lines constituting a data bus 24 which is a write bus to the parity RAM 2 and corresponds to the storage position of the parity bit indicated by the decoder 7. In order to transmit the other bits except for the bit corresponding to the storage position of the parity bit read out from the parity RAM 2 and held in the built-in buffer to the other seven output lines except for the above, The gate connected to the output line is turned on.

Next, the CPU 9 issues a parity RAM.
The read release signal 15 is input to the parity RAM 2, and the read designation for the parity RAM 2 is released.

Next, the CPU 9 issues a parity RAM.
The write signal 10 is input to the parity RAM 2, and write setting for the parity RAM 2 is performed. In the parity RAM 2, the output from the buffer with gate 32 and the output from the buffer with gate 33 are stored in the least significant bit 30 of the same address accessed during the previous read operation.
To the most significant bit 31.

Finally, the CPU 9 sends a parity RAM.
2, a parity RAM write release signal 16 is sent out, and a data RAM write release signal 17 is sent out to the data RAM 1, and the write designation of the parity RAM 2 and the data RAM 1 is released. Thus, the operation of storing the parity bits at the time of writing data to the data RAM 1 is completed.

When reading data, the CPU
9 accesses the address of the data RAM 1 designated by 9 and reads out the data stored at that address, and also reads the data stored in the parity RAM 2 where the parity bit of the data is stored. A parity check at the time of reading is performed by accessing, reading a plurality of parity bits stored in the address, and selecting a parity bit corresponding to the data from the plurality of read parity bits. A detailed description is omitted.

[0024]

In the above-described conventional parity bit writing method, one address of the parity RAM can store a parity bit added to a plurality of data. In order to store a 1-bit parity bit for the data to be written to the data RAM in the parity RAM, all bits of the address are once read from the parity RAM and held, and of the plurality of held bits, the parity to be written is written. The bit position is selected, the bit at the selected position is replaced with the parity bit to be written, and then the data is written to the original address of the parity RAM. For this reason, a buffer circuit and a gate circuit necessary for holding the bits read from the parity RAM and replacing the held bits with the parity bits to be written are required, and the circuit becomes complicated accordingly. Has disadvantages.

An object of the present invention is to provide a parity bit writing method which temporarily holds bits read from a parity RAM and simplifies a circuit for inserting parity bits.

[0026]

According to the parity bit writing method of the present invention, first storage means for storing data and n (n
Is a positive integer greater than 1) bits of second storage means, and stores up to n parity bits of the data sequentially stored in the first storage means at the same address of the second storage means. Each time new data is stored in the first storage means, the second storage destination of a parity bit to be added to the new data.
The potential corresponding to the logical content of n bits, which is the storage content of the address, read from the address of the storage means is stored in n capacitors, and is added to the data newly stored in the first storage means. When a parity bit is generated, one of the n capacitors corresponding to the storage position of the parity bit is selected, and the potential held by the capacitor is changed with respect to the new data. After replacing with the potential corresponding to the logical content of the parity bit generated by the above, the potential held by the n capacitors is read from the second storage means to the n capacitors first. It is configured to write to the original address at the time of writing.

The parity bit writing method according to the present invention is characterized in that: (A) first storage means for storing data;
(B) a second address where n (n is a positive integer greater than 1) bits can be stored in one address, and parity bits added to the data are sequentially stored in the address in n bits at a time in the order of occurrence Storage means; (C) a parity generator for calculating parity for data stored in the first storage means to generate and output the parity bits; (D) storing the parity bit at a first address of the first storage means A storage position on the second storage unit of the parity bit added to the obtained data is determined in correspondence with the first address; A parity bit insertion position indicating means indicating which bit of the n bits corresponds to the position, and (E) when the data is written to the first storage means, The potential corresponding to the logical content of said n bits read from the second address of 憶 means,
(F) parity data holding means for holding the parity bits in the order of the n bits, and (F) the n number of the n bits provided in correspondence with the order of the n bits in order to insert the parity bits into the n bits. Selecting, from the capacitors, one capacitor corresponding to one of the n bits, corresponding to the storage position of the parity bit, based on the output from the parity bit insertion position indicating means;
Parity bit insertion means for replacing the potential held by the selected capacitor with a potential corresponding to the logical content of the parity bit output from the parity generator; (G) the parity bit insertion means After the replacement of the potential held by the capacitor,
And control means for writing the potential held by the n capacitors to the original address of the second storage means at the time of first reading.

The parity bit writing method according to the present invention is characterized in that the first storage means and the second storage means are each a random access memory.

The parity bit writing method according to the present invention is characterized in that the parity bit insertion position indicating means is constituted by a decoder.

The parity bit writing method according to the present invention is characterized in that the parity data holding means is composed of n capacitors.

Also, in the parity bit writing method according to the present invention, the parity bit insertion position indicating means may store the parity bit at the second address at the n address.
In order to indicate which bit of the bit the position corresponds to, n output lines corresponding to the n bits are provided, and the storage position of the parity bit among the n output lines The logical value of one output line corresponding to the above is inverted.

[0032]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a parity bit writing system according to the present invention.

The parity bit writing method shown in FIG. 1 uses the same data RAM 1 and parity RAM 2 as the parity bit writing method shown in FIG. The difference between the parity bit writing method shown in FIG. 1 and the parity bit writing method shown in FIG. 2 is that among the eight bits read from the parity RAM 2 provided in the parity bit writing method shown in FIG. Of 1
Instead of the gated buffer 32 and the gated buffer 33, which are circuits for replacing the contents of the bits with the parity bits output from the parity generator 3, in the parity bit writing method shown in FIG. And a parity data holding unit 5 having a capacitor.

The parity bit writing system of the present embodiment shown in FIG. 1 employs a CPU 9, an address bus 18a having a bus width of 16 bits, and a data bus 19 having a bus width of 8 bits.
, Which is connected to the CPU 9 and stores data output from the CPU 9.
And a parity bit added to the data stored in the data RAM 1, which is connected to an address bus 18 b having a bus width of 13 bits and which is branched from an address bus 18 a having a bus width of 16 bits. RAM 2 for parity and data bus 1 having a bus width of 8 bits
9, a parity generator 3 for performing a parity operation on data to be written to the data RAM 1 and generating and outputting a parity bit, and a bus width which is an extension of the 13-bit address bus 18b branched from the address bus 18a. It is connected to the 3-bit address bus 18c and indicates which bit position of the 8 bits read from the parity RAM 2 is the storage position of the parity bit added to the data stored in the data RAM 1. For this purpose, the decoder 7 inverts the logical value of one output line corresponding to the storage position of the parity bit 12 among the eight output lines constituting the data bus 22 having a bus width of 8 bits connected to the output side. Corresponding to 8 bits read from the specified address of the parity RAM 2,
It has eight output lines constituting the data bus 36, and each output line has a gate circuit for turning on and off,
Based on the output from the decoder 7, of the 8 bits read from the specified address of the parity RAM 2,
One of eight output lines constituting the data bus 35 connected to the parity RAM 2 corresponding to the storage position of the parity bit 12 indicated by the decoder 7 is selected,
A gate 6 that controls the gate connected to this output line to turn on and sends the parity bit 12 output from the parity generator 3 and held in the built-in buffer to the output line whose gate is controlled to be on. And the parity R through eight input / output lines constituting the data bus 35.
Eight parity data holding potentials indicating the logical contents of 8 bits read from AM 2, parity data holding having capacitors 4 a to 4 h having one end grounded and the other end connected to the output line of gated buffer 6. 5.

Next, the operation will be described.

The operation of writing data to the data RAM 1 shown in FIG. 1 will be described.

In order to store data in the data RAM 1 and write parity bits in the parity RAM 2,
From PU9, address input signal 13, data input signal 1
4. Data RAM write signal 8 and data RA
An M write release signal 17 is input to the data RAM 1, and a parity RAM write signal 10, a parity RAM read signal 11, a parity RAM read release signal 15, and a parity RAM write release signal 16 are input to the parity RAM 2. RAM 1 for data and RAM for parity by respective signals
2 is the same as the parity bit writing method shown in FIG. In addition, data is stored in the data RAM 1 and a parity bit to be added to the data stored in the data RAM 1 is written in the parity RAM 2.
From the address on the parity RAM 2 for storing the parity bit to be added to the data stored in the memory until the state of all the bits at that address is read out.
This is the same as the parity bit writing method shown in FIG. Therefore, the description of the same operation as that of the parity bit writing method of FIG. 2 will be omitted here.

Next, a detailed description will be given from the point where the data input signal 14 is input from the CPU 9 to the data RAM 1.

When the data input signal 14 is input from the CPU 9 to the data RAM 1, the parity generator 3
Also generates a parity bit for the 8-bit data input to the data RAM 1 and outputs the parity bit to the gated buffer 6. In addition, the CPU 9 sends a parity R
The AM read signal 11 is input to the parity RAM 2 and a read designation is made to the parity RAM 2.
At this time, the upper 13 bits of the address input signal 13 are already input to the parity RAM 2 in order to store the parity bit added to the data, and the address constituted by the upper 13 bits of the address input signal 13 is stored. Since the address on the parity RAM 2 specified by the CPU 9 is being accessed by the input signal, the 8-bit storage content of the accessed address is read out and the data bus 35 The data is output to the parity data holding unit 5 through the eight input / output lines. The parity data holding unit 5 includes eight bit holding capacitors 4a to 4h corresponding to the eight bits read from the parity RAM 2.
Is provided, eight capacitors 4a to 4h share and store eight bits of storage contents read and output from the parity RAM 2 for eight bits. That is, one capacitor holds one bit of stored content.

The decoder 7 decodes the address input signal composed of the lower three bits of the input address input signal 13 and reads out the address input signal from the parity RAM 2 according to the decoding result. Eight output lines corresponding to the eight bits are provided to indicate which bit position in the output eight bits is the storage position of the parity bit added to the data stored in the data RAM 1. Then, of the eight output lines, the logical value of one output line corresponding to the storage position of the parity bit 12 is inverted. The eight output lines constitute a data bus 22 having a bus width of 8 bits, and are connected to the buffer 6 with a gate. Is notified to the gated buffer 6 of which bit position in is the storage position of the parity bit.

In the buffer 6 with a gate, the data 8 written into the data RAM 1 from the parity generator 3 has already been written.
Since the parity bit corresponding to the bit data is output and held, the gate corresponding to the storage position of the parity bit specified by the output from the decoder 7 is controlled, and the parity bit is transmitted through the controlled gate. It outputs to the output line specified as the output of the decoder 7 among the output lines connected to the capacitors 4a to 4h in the parity data holding unit 5. Note that the control of the gate, the output line to which the controlled gate is connected is turned on by the control of the gate, and connected to other uncontrolled gates,
The output line is configured to be turned off. Therefore, the potential held by the capacitor in the parity data holding unit 5 corresponding to the storage position of the parity bit specified by the gate control signal is maintained in the potential state corresponding to the value of the parity bit. Further, the potential held by the other capacitor holds the previous potential.

For example, when the value of the parity data is "1", the potential held by the capacitor in the parity data holding unit 5 is high, and the value of the parity data is "0".
And the case where the parity bit is stored in an address where no parity bit is stored (in this case, all values of the 8 bits of this address are “0”). In the state where the data is first read out from the above address to the capacitor corresponding to the 8-bit value of the address where the parity bit is not stored, the capacitors 4a to 4h in the parity data holding unit 5 are considered. The potentials are all low, and the parity bit is “1” in a state where the data is output from the gated buffer 6 to the parity data holding unit 5 under the control of the gate.
Then, only the potential of the capacitor connected to the gate is shifted to a high potential corresponding to the value of the parity bit “1” and maintained, and if the parity bit is “0”, the capacitor connected to the gate is Is maintained at a low potential corresponding to the value "0" of the parity bit.

Next, the CPU 9 issues a parity RAM.
The read release signal 15 is input to the parity RAM 2, and the read designation is released. After this, CPU
From 9, a parity RAM write signal 10 is input to the parity RAM 2, and when write setting is performed on the parity RAM 2, the parity RAM 2 accesses the same address that was accessed during the previous read operation. The potential state of each capacitor of the parity data holding unit 5 is written through eight input / output lines constituting the data bus 35.

Thereafter, the parity RA is sent from the CPU 9.
For M2, the parity RAM write release signal 16
Is sent to the data RAM 1, and the data RAM write release signal 17 is sent out, and the write designation of the parity RAM 2 and the data RAM 1 is released, and the parity bit at the time of writing data to the data RAM 1 is released. The operation of ending the storage operation is the same as in FIG.

Incidentally, the operation for reading out the data stored in the data RAM 1 can be performed by reading out the potentials of the capacitors 4a to 4h in the parity data holding unit 5, and which potential Is selected in the same manner as in the prior art.

In the above description, the parity RAM is used.
Although 2 has been described as being constituted by a 1-address 8-bit RAM, it is not limited to an 8-bit RAM, and can be constituted by a 1-address n (n is a positive integer greater than 1) bit RAM.

[0048]

As described above, according to the parity bit writing method of the present invention, the number of capacitors corresponding to the number of read bits is provided as circuit means for temporarily holding the bits read from the parity RAM. This has the effect that the circuit for temporarily holding the bits read from the parity RAM and replacing the held bits with the generated parity bits can be simpler than the conventional circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a parity bit writing system according to the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional parity bit writing method.

FIG. 3 is an explanatory diagram showing a storage state of parity bits in a parity RAM shown in FIGS. 1 and 2;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 data RAM 2 parity RAM 3 parity generator 4 a to 4 h capacitor 5 parity data holding unit 6 buffer with gate 7 decoder 8 data RAM write signal 9 CPU 10 parity RAM write signal 11 parity RAM read signal 12 parity bit 13 Address input signal 14 Data input signal 15 Parity RAM read release signal 16 Parity RAM write release signal 17 Data RAM write release signal 18a-18c Address bus 19 Data bus 22-25 Data bus 26,27 Address 32,33 With gate Buffer 35, 36 Data bus

Claims (6)

[Claims] 1. first storage means for storing data;
A parity bit of the data is stored, where n is 1
And a second storage unit of (positive integer greater than) bits, so that up to n parity bits of the data sequentially stored in the first storage unit can be stored at the same address of the second storage unit. Each time the new data is stored in the first storage means, the storage content of the address read from the address of the second storage means, which is the storage destination of the parity bit added to the new data Is a potential corresponding to the logical content of n bits
When a parity bit to be held in the capacitors and added to the data newly stored in the first storage means is generated, the parity bit corresponds to the storage position of the parity bit.
After selecting one of the n capacitors and replacing the potential held by the capacitor with a potential corresponding to the logical content of the parity bit generated for the new data Parity bit writing, wherein the potentials held by the n capacitors are written to the original addresses when the n capacitors were previously read from the second storage means. method. (A) first storage means for storing data, and (B) n (n is a positive integer greater than 1) bits can be stored in one address, which is added to the data. A second storage unit in which parity bits are sequentially stored in the address in the order of n bits at a time, and (C) a parity for data stored in the first storage unit is calculated to generate and output the parity bit. A parity generator, wherein (D) a storage position on the second storage unit of the parity bit added to the data stored in the first address of the first storage unit is stored in the first address. A parity bit insertion position indicating means for indicating which bit of the n bits of the second address on the second storage means is determined correspondingly; When writing data to the first storage means, the potential corresponding to the logical content of the n bits read from the second address of the second storage means corresponds to the order of the n bits. (F) the parity bit is inserted from the n capacitors provided in correspondence with the order of the n bits in order to insert the parity bit into the n bits. Based on the output from the insertion position indicating means,
One capacitor corresponding to one bit of the n bits corresponding to the storage position of the parity bit is selected, and the potential held by the selected capacitor is determined by:
Parity bit inserting means for replacing with a potential corresponding to the logical content of the parity bit output from the parity generator, (G) after replacing the potential held by the selected capacitor by the parity bit inserting means, A parity bit writing method, comprising: control means for writing the potential held by the n capacitors to the original address of the second storage means at the time of first reading. 3. A parity bit writing method according to claim 1, wherein said first storage means and said second storage means are each a random access memory. 4. The parity bit writing method according to claim 2, wherein said parity bit insertion position indicating means is constituted by a decoder. 5. The parity bit writing method according to claim 2, wherein said parity data holding means is composed of n capacitors. 6. The parity bit writing method according to claim 2, wherein said parity bit insertion position indicating means sets a storage position of said parity bit at a second address in any bit of said n bits. It has n output lines corresponding to the n bits in order to indicate whether it is the corresponding position, and among the n output lines, one of the output lines corresponding to the storage position of the parity bit. A parity bit writing method characterized by inverting a logical value.