JPH10294425A - Integrated circuit protective device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit protective device which can lower the voltage for operating a controlled rectifier element as a semiconductor integrated circuit protective element with the minimum circuit area. SOLUTION: SCRs(silicon-controlled rectifiers) 5 and 6 are incorporated in a protective device 1 connected to the input-output terminal 19 of an LSI (large scale integration) circuit 18 and the n-type layer 9 corresponding to the n-gate of the SCR 5 is connected to the power source 20 of the LSI circuit 18. The p-type layer 13 corresponding to the p-gate of the SCR 6 is connected to a grounding terminal through a resistor 21. When positive ESD(electrostatic discharge) is impressed upon the terminal 19 and the potential at the ESD is higher than the sum of the voltage at the power source 20 and the forward voltage at a p-n junction 22a, the SCR 5 conducts to discharge the ESD through the ground and, when negative ESD is impressed upon the terminal 19 and the potential at the ESD is negatively higher than the sum of the ground potential and the forward voltage at a p-n junction 25a, the SCR 6 conducts to discharge the ESD through the ground.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a silicon integrated circuit connected to an external signal terminal of a semiconductor integrated circuit to prevent the semiconductor integrated circuit from being destroyed when a voltage exceeding a predetermined range is applied to the external signal terminal. The present invention relates to an integrated circuit protection device including a control rectifier.

[0002]

SUMMARY OF THE INVENTION An electrostatic discharge (Electro Static Disch) which is a kind of electrostatic noise applied to a large-scale integrated circuit (hereinafter, referred to as an LSI) composed of a semiconductor.
There are various types of events. For example, (1) static electricity is discharged when a charged human body or object directly touches an LSI terminal, or (2) static electricity is discharged to an electronic device through a metal object held by a charged human body. If so, there are.

In response to the ESD events (1) and (2), there is a standard set to guarantee that LSIs and electronic devices do not malfunction even when static electricity of a constant voltage is discharged. I do. For (1), MIL, EI
There is an AJ standard and an IEC standard for (2). In order to cope with such a standard, a protection element for ESD measures is formed inside an LSI.

However, even if a protection element such as a transistor or a diode is formed inside the LSI, there is a limit to the response time and the amount of discharge of the discharge current due to ESD, so even if the MIL and EIAJ standards can be cleared,
As in the case of the IEC standard, it was not possible to cope with a severe application in which an applied voltage of ± 2 to 8 kV was applied by a contact discharge method.

Therefore, it has been considered to use a silicon controlled rectifier (hereinafter, referred to as SCR) as a protection element capable of controlling a large current capable of complying with the IEC standard. The SCR also has favorable properties such as low resistance during conduction, low power consumption and low heat generation.

However, if only the SCR is formed inside the LSI and both terminals of the SCR are connected between, for example, the input / output terminal of the LSI and the internal circuit and the ground, the ES
If the voltage applied between the input / output terminal of the LSI and the ground by D is not 70 V or more, the SCR does not operate as a protection element. Therefore, when the applied voltage is a relatively low value of less than 70 V, there is a problem that the LSI cannot be protected.

As a technique for lowering the operating voltage when the SCR functions as a protection element, for example, Japanese Unexamined Patent Application Publication No.
There is one disclosed in JP-A-53407. This solves the above problem by combining an SCR with an inverter gate.
An extra area for the protection element is required for the formation of the inverter gate, which leads to an increase in chip size.

The present invention has been made in view of the above circumstances, and has as its object to reduce the voltage at which a silicon controlled rectifying element operates as a protection element for a semiconductor integrated circuit with a minimum circuit area. And a protective device for the integrated circuit.

[0009]

According to the first aspect of the present invention, there is provided a silicon-controlled rectifying device in which one end and the other end of an input terminal are connected to an external signal terminal and a ground terminal of a semiconductor integrated circuit. For example, when static electricity is applied to an external signal terminal of a semiconductor integrated circuit as a voltage outside a predetermined range, a forward current flows through a pn junction due to a difference between the static electricity voltage and an operation reference voltage. Since the conduction is performed, the static electricity is discharged through a path via the ground, thereby preventing the voltage of the static electricity from being applied to the semiconductor integrated circuit.

Therefore, if the difference between the voltage outside the predetermined range and the reference voltage for operation is a value sufficient to allow a forward current to flow through the pn junction of the silicon controlled rectifier, the silicon controlled rectifier conducts. Since it operates as a protection element, unlike the conventional one, there is no need to form an extra circuit, and it is possible to operate the silicon controlled rectifying element with a minimum circuit area even when the applied voltage is relatively low. Yes, it can be made compact as a whole.

According to the integrated circuit protection device of the present invention, the anode of the silicon controlled rectifier is connected to the external signal terminal of the semiconductor integrated circuit, the cathode is connected to the ground terminal, and the operating reference is connected to the n gate. Since a positive voltage protection element is configured by applying a voltage, for example, when positively charged static electricity is applied to an external signal terminal of the semiconductor integrated circuit, the static electricity voltage and the n-gate are applied. A forward current flows through the pn junction due to the difference from the operating reference voltage, and the positive voltage protection element conducts and operates. Therefore, it is possible to cope with a case where the voltage outside the predetermined range has a positive polarity.

According to the third aspect of the present invention, since the reference voltage for operation is set equal to the voltage of the power supply for operation of the semiconductor integrated circuit, the normal reference signal applied to the external signal terminal of the semiconductor integrated circuit is provided. At the level of the input signal, the positive polarity voltage protection element does not operate, and when a voltage exceeding a predetermined range exceeding the operation power supply of the semiconductor integrated circuit is applied, the positive polarity voltage protection element operates. Accordingly, sufficient and appropriate protection of the semiconductor integrated circuit can be performed, and it is not necessary to prepare a separate power supply for supplying an operation reference voltage to the positive voltage protection element.

According to the fourth aspect of the present invention, the cathode of the silicon controlled rectifier is connected to the external signal terminal of the semiconductor integrated circuit, the anode is connected to the ground terminal, and the p-gate is connected via the resistor. Since it is configured as a negative voltage protection element to which an operation reference voltage is given by being connected to a ground terminal, for example, when static electricity charged to a negative polarity is applied to an external signal terminal of the semiconductor integrated circuit, A forward current flows through the pn junction due to the difference between the voltage of the static electricity and the ground potential applied to the p-gate, and the element for negative voltage protection conducts and operates. Therefore, it is possible to cope with the case where the voltage outside the predetermined range has a negative polarity.

According to a fifth aspect of the present invention, there is provided an integrated circuit protection device comprising a plurality of silicon controlled rectifiers, which can cope with either positive or negative polarity of a voltage out of a predetermined range. Therefore, the semiconductor integrated circuit can be protected regardless of the polarity of the voltage outside the predetermined range.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram schematically showing a cross section of a protection device for an integrated circuit (hereinafter, referred to as a protection device) 1 of the present invention. In FIG. 1, a protection device 1 includes two n-type layers formed by diffusion or the like in a p-type layer 2 of a substrate portion.
SCRs (silicon controlled rectifiers, positive voltage protection elements) 5 and SCRs (silicon controlled rectifiers, negative voltage protection elements) as shown by two-dot chain lines in FIG. 6 is formed.

The SCR 5 is configured as follows. A p-type layer 7 is formed inside the n-type layer 3 and the p-type layer 7 is formed.
Further, an n-type layer 8 is formed inside. Further, a high concentration n (n +)-type layer 9 and a p-type layer 10 are formed inside the n-type layer 3.

That is, the p-type layer 10, the n-type layer 3, the p-type layer 7,
The SCR 5 is constituted by the pnpn structure of the n-type layer 8, the p-type layer 10 corresponds to the anode, the n-type layer 8 corresponds to the cathode, and the n-type layer 9 inside the n-type layer 3 corresponds to the n-gate. I have.

The SCR 6 is configured as follows. A p-type layer 11 is formed inside the n-type layer 4 and
The n-type layer 12 and the high-concentration p (p +)
Forming layer 13 is formed. Further, a p-type layer 14 is formed inside the n-type layer 4.

That is, the p-type layer 14, the n-type layer 4, and the p-type layer 1
The SCR 6 is constituted by a pnpn structure composed of a 1, n-type layer 12 such that the p-type layer 14 corresponds to an anode, the n-type layer 12 corresponds to a cathode, and the p-type layer 13 inside the p-type layer 11 corresponds to a p-gate. Has become.

In the p-type layer 2, high-concentration p-type layers 15 and 16 for wiring connection are formed corresponding to the SCRs 5 and 6. Together with the p-type layer 8 and the p-type layer 14, they are connected to a ground terminal by, for example, aluminum wiring.

The input terminal 17 of the protection device 1 is connected to the p-type layer 10
And an n-type layer 12 and an input / output terminal (external signal terminal) 19 of an LSI (semiconductor integrated circuit) 18. LSI 18 is 2-5 V from power supply 20
Operation power is supplied. The power supply 20 is also connected to the n-type layer 9 of the protection device 1 so as to supply an operation reference voltage to the n-type layer 9 (n-gate) of the SCR 5.

On the other hand, the p-type layer 13 (p-gate) of the SCR 6
Is connected to the ground terminal together with the p-type layer 14 via the resistor 21. The resistor 21 is formed of a semiconductor resistor, a thin film resistor, or the like on the substrate, and has a resistance of about 10 to 100.
It is set to about Ω. In FIG. 1, the protection device 1 and the LSI 18 are shown as separate bodies, but actually,
Both are integrally formed as a monolithic IC.

FIG. 2 is a diagram showing the protection device 1 in an equivalent circuit. As is well known, the SCRs 5 and 6 have a configuration in which a pnp transistor and an npn transistor are combined.

That is, in the SCR 5, the p-type layer 10,
a pnp transistor 22 having an n-type layer 3 (n-type layer 9) and a p-type layer 7 as an emitter, a base and a collector, respectively;
The p-type layer 3, the p-type layer 7, and the n-type layer 8 are a collector, a base,
This is a combination of an npn-type transistor 23 serving as an emitter.

In the SCR 6, the p-type layer 14,
The n-type layer 4 and the p-type layer 11 (p-type layer 13)
Pnp transistor 24 used as base and collector
And an npn-type transistor 2 using the n-type layer 4, the p-type layer 11, and the n-type layer 12 as a collector, a base, and an emitter, respectively.
5 is combined.

The base of the transistor 22 which is the n-gate of the SCR 5 and the collector of the transistor 23 are connected to the power supply 20, and the collector of the transistor 24 which is the p-gate of the SCR 6 and the transistor 25
Is connected to a ground terminal via a resistor 21.

Next, the operation of the present embodiment when an electrostatic discharge (hereinafter referred to as ESD) is applied to the input / output terminal 19 of the LSI 18 as a voltage outside the predetermined range will be described with reference to FIG.

(1) When ESD is Positive The potential of the n-type layer 9 corresponding to the n gate of the SCR 5 is equal to the voltage of the power supply 20. Therefore, the input / output terminal 19, ie, S
The ESD voltage applied to the anode of CR5 is
If the voltage is larger than the sum of the voltage of 0 and the forward voltage (for example, about 0.7 V) of the pn junction 22a including the p-type layer 10 and the n-type layer 9, the pn junction 22a has a forward direction. Electric current flows. Since a forward current flowing through the pn junction 22a is equivalent to a base current flowing through the transistor 22, the transistor 22 is turned on.

Then, when the collector current of the transistor 22 flows as the base current of the transistor 23, the transistor 23 is also turned on, and both the transistors 22 and 23 are turned on, and the SCR 5 is turned on. Since the ESD applied to the input / output terminal 19 is discharged from the ground terminal to the outside via the SCR 5, the ESD is not applied to the LSI 18.

When no ESD is applied to the input / output terminal 19 while the SCR 5 is conducting, the potential of the p-type layer 10 decreases. Then, the potential of the p-type layer 10 is
When the voltage becomes lower than the sum of the voltage of 0 and the forward voltage of the pn junction 22a, the base current of the transistor 22 stops flowing, and the transistor 22 is turned off. Then, the transistor 23 is also turned off, so that the SCR 5 is also turned off.

The maximum amplitude level of a signal applied to the input / output terminal 19 as an input / output signal of the LSI 18 is usually L level.
Since the input / output signal is equal to or lower than the operating voltage of the SI 18, even if such an input / output signal is applied, no forward current flows through the pn junction 22a, and the SCR 5 does not become conductive. Input / output normally.

(2) When ESD is Negative The p-type layer 13 corresponding to the p-gate of the SCR 6 is connected to the ground terminal via the resistor 21 as described above.
Therefore, the ground potential corresponds to the operating reference voltage,
The ESD voltage applied to the input / output terminal 19, that is, the cathode of the SCR 6, is applied to the p-type layer 11 and the n-type layer 12.
If the voltage is higher (negative polarity) than the forward voltage of the n junction 25a, a forward current flows through the pn junction 25a.
The fact that a forward current flows through the pn junction 25a means that
Since the base current is equal to the flow of the transistor 25, the transistor 25 is turned on.

Then, the base current of the transistor 24 also flows when the collector current flows to the transistor 25, the transistor 24 is also turned on, and both the transistors 25 and 24 are turned on, and the SCR 6 is turned on. Since the negative ESD applied to the input / output terminal 19 is discharged through a path via the ground, the
18 is not applied.

From the state in which the SCR 6 is conducting, the ESD is not applied to the input / output terminal 19, the potential of the n-type layer 12 rises, and the sum of the ground potential and the forward voltage of the pn junction 25a becomes ( When it becomes low (at the negative polarity), the base current of the transistor 25 stops flowing, and the transistor 25 is turned off. Then, the transistor 24 is also turned off, so that the SCR 6 is also turned off.

Since the minimum amplitude level of the input / output signal of the LSI 18 is normally higher than the ground potential (with positive polarity), even if such an input / output signal is applied to the input / output terminal 19, the pn junction 25a Since no forward current flows, SC
R6 does not become conductive and the normal input / output signal is LSI
18 is normally input and output.

As described above, according to this embodiment, the LSI 1
8 is provided with SCRs 5 and 6 and the n-gate of SCR 5 is connected to the power supply 2 of the LSI 18.
0, and the p-gate of the SCR 6 is connected to the ground terminal via the resistor 21, so that when a positive ESD is applied to the input / output terminal 19, the potential of the ESD becomes the voltage of the power supply 20 and the pn If the sum is larger than the sum of the forward voltage of the junction 22a and the forward voltage, the SCR 5 is turned on to discharge the ESD through a path via the ground. If a negative ESD is applied to the input / output terminal 19, If the potential of the ESD is negative and greater than the sum of the ground potential and the forward voltage of the pn junction 25a, the SCR 6 is turned on to discharge the ESD through the path via the ground.

Accordingly, when the ESD has a positive polarity, the voltage is higher than the voltage of the power supply for operation of the LSI 18 in the pn junction 2.
If the voltage is higher by the forward voltage of 2a, LSI18 is added to SCR5.
When the ESD has a negative polarity, the voltage is lower than the ground potential at the pn junction 2.
If the negative voltage is higher by the forward voltage of 5a, the SCR 6 can perform the protection operation.

Therefore, the protection against the ESD can be performed appropriately and sufficiently, and unlike the related art, when the SCR is used for the protection device, an extra circuit is not formed and the ESD is reduced with a minimum circuit area. It is possible to cause the SCR to perform a protection operation even when the voltage of the
The whole protection device 1 can be made compact. Also,
Regardless of whether the polarity of the ESD applied to the input / output terminal 19 is positive or negative, it is possible to protect the ESD voltage from being applied to the LSI 18. And SCR5
It is not necessary to prepare a separate power supply for supplying an operation reference voltage to the n gate.

The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. The protection device 1 may be provided with only one of the SCRs 5 and 6 without providing both. The external signal terminal is not limited to the input / output terminal 19 but may be an input terminal or an output terminal. The operation reference voltage applied to the n gate of the SCR 5 does not necessarily need to be set equal to the voltage of the power supply 20 of the LSI 18. For example, depending on the configuration of the interface between the LSI 18 and the external circuit, the LSI
The power supply voltage of the input / output buffer is set higher (for example, 5 V) than the operation power supply voltage of 18 (for example, 3 V).
In this case, the operation reference voltage may be set equal to the power supply voltage of the input / output buffer. Semiconductor integrated circuits are LSI
For example, ULSI or MSI may be used, and the scale of integration is not limited as long as it is an integrated circuit.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a cross section of an integrated circuit protection device connected to an external signal terminal of a semiconductor integrated circuit, showing an embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of the protection device for an integrated circuit;

[Explanation of symbols]

1 is an integrated circuit protection device, 5 is an SCR (silicon controlled rectifier, positive voltage protection element), 6 is an SCR (silicon controlled rectifier, negative voltage protection element), and 8 is an n-type layer (cathode). , 9 is an n-type layer (n-gate), 10 is a p-type layer (anode), 12 is an n-type layer (cathode), 13 is a p-type layer (p-gate), 14 is a p-type layer (anode), 18 is L
SI (semiconductor integrated circuit), 19 is an input / output terminal (external signal terminal), 20 is a power supply (power supply for operation), 21 is a resistor, 22
a and 25a show a pn junction.

Claims (5)

[Claims] 1. A silicon controlled rectifier element connected to an external signal terminal of a semiconductor integrated circuit and for preventing the semiconductor integrated circuit from being damaged when a voltage out of a predetermined range is applied to the external signal terminal. In the integrated circuit protection device provided, the silicon controlled rectifier has one end of an input terminal connected to an external signal terminal of the semiconductor integrated circuit and the other end connected to a ground terminal. A forward current flows through the pn junction due to the difference between the voltage applied to the external signal terminal of the circuit and the reference voltage for operation, so that the pn junction becomes conductive and a voltage outside the predetermined range is applied to the semiconductor integrated circuit. A protection device for an integrated circuit, characterized in that the protection device is configured to prevent the occurrence of a problem. 2. A positive electrode having an anode connected to an external signal terminal of the semiconductor integrated circuit, a cathode connected to a ground terminal, and an operation reference voltage applied to an n gate. 2. The protection device for an integrated circuit according to claim 1, wherein the protection device is configured as a neutral voltage protection element. 3. The integrated circuit protection device according to claim 2, wherein the operation reference voltage is set equal to a voltage of an operation power supply of the semiconductor integrated circuit. 4. The silicon controlled rectifier has a cathode connected to an external signal terminal of the semiconductor integrated circuit, an anode connected to a ground terminal, and a p-gate connected to a ground terminal via a resistor. 2. The integrated circuit protection device according to claim 1, wherein the protection device is configured as a negative voltage protection element to which an operation reference voltage is applied. 5. A semiconductor device comprising a plurality of silicon-controlled rectifying elements so that the voltage outside the predetermined range can be applied to both positive and negative voltages. The protection device for an integrated circuit according to claim 1.