JPH1027847A - Integrated semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration in the device performance of a MOS transistor, etc., by a method wherein an impurity diffusion preventing layer, with which the diffusion of impurities into a semiconductor substrate is prevented, is formed between polycrystalline silicon and the semiconductor substrate. SOLUTION: In an integrated semiconductor device wherein an electric active region 3 formed on a semiconductor substrate 1 is electrically connected using impurity-containing polycrystalline silicon 6, an impurity diffusion preventing layer 5, which prevents the diffusion of impurities into the semiconductor substrate 1, is formed between the polycrystalline 6 and the semiconductor substrate 1. For example, a MOS transistor is formed on the semiconductor substrate 1, an interlayer insulating film 14 is formed and a contact hole 12 is opened. Then, the first polycrystalline silicon film 5, having the impurity density sufficiently lower than a source and drain region 3 is formed, and a suitable thickness of the film is left inside the contact hole 12 by etching the whole surface. Subsequently, the second polycrystalline silicon 6 is formed on over the contact hole 12, and an etching treatment is conducted so as to obtain the desired wiring form.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to polycrystalline silicon in which two or more active element regions exist and in which some or all of means for electrically connecting the active regions contain impurities. The present invention relates to an integrated semiconductor device used.

[0002]

2. Description of the Related Art FIG. 9 is a view showing a conventional integrated semiconductor device, in which 1 is a semiconductor substrate, 2 is an element isolation, 3 is a source / drain region of a MOS transistor, 4 is a gate electrode, 7 is a side wall, 13 is a wiring using polycrystalline silicon containing impurities, and 14 is an interlayer insulating film. FIG. 10 is an enlarged view of a connection portion between the source / drain region 3 and the polycrystalline silicon 13 of the integrated semiconductor device of FIG. In the figure, a broken line 11 indicates a diffusion range of impurities of the polycrystalline silicon 13 into the semiconductor substrate 1.

In an integrated semiconductor device, aluminum or an alloy containing aluminum is usually used as a wiring material. However, in a process after forming the wiring, a temperature limit of 450 ° C. is generated at a maximum, and a process requiring heat application is required. Cannot be performed after the wiring step. Therefore, if it is necessary to form a wiring before forming a metal wiring, the polycrystalline silicon 13 containing impurities having conductivity is used. Generally, phosphorus or boron is used as this impurity. In addition, since such wiring has higher resistance than metal wiring, impurities are included in polycrystalline silicon to a concentration close to supersaturation in order to reduce resistance. For example, a metal silicide such as TiSi2 or WSi2 and a multilayer structure are used. Then, a method of further lowering the resistance may be used.

[0004]

Since the conventional integrated semiconductor device is constructed as described above, as shown in FIG. A phenomenon in which impurities permeated the substrate 1 occurred. This results in the impurity being diffused to the position of the junction forming the source / drain of the MOS transistor formed on the semiconductor substrate 1, for example, to the position indicated by the broken line 11, so that the characteristics of the MOS transistor, for example, Sub-threshold voltage (Vt
h) and source-drain breakdown voltage (BVds) have been conventionally concerned. Further, as the miniaturization of the semiconductor element progresses, the connection position between the gate electrode 4 and the polycrystalline silicon 13 is becoming shorter and shorter, which has a problem that the influence on the transistor characteristics is further increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and suppresses the diffusion of impurities from polycrystalline silicon to a semiconductor substrate, thereby preventing the effect on MOS transistor characteristics and preventing high performance. It is an object to obtain a highly integrated semiconductor element.

[0006]

SUMMARY OF THE INVENTION An integrated semiconductor device according to the present invention is an integrated semiconductor device for electrically connecting to an electrically active region formed on a semiconductor substrate by using polycrystalline silicon containing impurities. In the semiconductor device, an impurity diffusion preventing layer for preventing the impurity from diffusing into the semiconductor substrate is formed between the polycrystalline silicon and the semiconductor substrate.

Further, a metal silicide compound is formed on polycrystalline silicon.

A first polycrystalline silicon electrically connected to an electrically active region formed on a semiconductor substrate, and a second polycrystalline silicon formed on the first polycrystalline silicon Silicon, and one or both of the type and concentration of impurities of the first polycrystalline silicon and the second polycrystalline silicon are different.

Further, the impurity concentration of the first polycrystalline silicon is lower than the impurity concentration of the second polycrystalline silicon.

The first polycrystalline silicon is polycrystalline silicon containing no impurities.

[0011] The impurities of the first polycrystalline silicon and the second polycrystalline silicon are at least one of phosphorus, boron, arsenic, antimony, bismuth, gallium, indium and thallium.

Further, a metal silicide compound is formed on the second polycrystalline silicon.

A first polycrystalline silicon electrically connected to an electrically active region formed on a semiconductor substrate and a metal silicide compound formed on the first polycrystalline silicon are It is provided.

Further, an impurity diffusion preventing layer is formed between the first polycrystalline silicon and the semiconductor substrate to prevent impurities of the first polycrystalline silicon and the second polycrystalline silicon from diffusing into the semiconductor substrate. It was done.

In a semiconductor device for electrically connecting an electrically active region formed on a semiconductor substrate using polycrystalline silicon containing an impurity, the concentration of the impurity contained in the polycrystalline silicon may be reduced in a layered manner. To be continuously changed.

Further, the impurity concentration increases continuously from the lower layer to the upper layer of the polycrystalline silicon.

Further, a metal silicide compound is formed on polycrystalline silicon.

Further, an impurity diffusion preventing layer for preventing impurities contained in the polycrystalline silicon from diffusing into the semiconductor substrate is formed between the polycrystalline silicon and the semiconductor substrate.

The impurities contained in the polycrystalline silicon are at least one of phosphorus, boron, arsenic, antimony, bismuth, gallium, indium and thallium.

The impurity diffusion preventing layer is made of titanium nitride,
At least one of silicon oxide and silicon nitride.

The metal silicide compound is at least one of nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, aluminum silicide, and ruthenium silicide.

In a semiconductor device for electrically connecting an electrically active region formed on a semiconductor substrate using polycrystalline silicon containing an impurity, the impurity of the polycrystalline silicon is arsenic, antimony, It is at least one of bismuth, gallium, indium, and thallium.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing an integrated semiconductor device according to Embodiment 1 of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an element isolation, 3 is a source / drain region of a MOS transistor, 4 is a gate electrode, 5 is first polycrystalline silicon, 6 is second polycrystalline silicon, 7 is a side wall. , 12 are connection holes, and 14 is an interlayer insulating film. FIG. 2 is an enlarged view of a connection portion between the source / drain region 3 and the polycrystalline silicon 5 of the integrated semiconductor device of FIG. In the figure, the broken line 11a indicates the first polysilicon 5
1 shows the range of diffusion of the impurity into the semiconductor substrate 1.

Hereinafter, the manufacturing method will be described with reference to FIG.
A device isolation 2, a gate electrode 4, and a source / drain region 3 are formed on a semiconductor substrate 1 by a conventional method, an interlayer insulating film 14 is formed, and a connection hole 12 of a wiring layer is formed by an etching method (FIG. 1a). ). Next, a first polycrystalline silicon 5 having an impurity concentration sufficiently lower than the impurity concentration of the source / drain region 3 is formed (FIG. 1B). (FIG. 1c). The thickness of the first polycrystalline silicon 5 is
Although it depends on the depth of the connection hole 12, it is generally from 20 nm to 5 nm.
About 0 nm shows good characteristics. Subsequently, a second polycrystalline silicon film 6 is formed on this upper portion, and photolithography and etching processes are performed to obtain a desired wiring shape. The impurity concentration of the first polycrystalline silicon 5 is desirably set to about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , but this is because the second polycrystalline silicon 6 and the source / drain It is desirable to determine the impurity concentration in comparison with the impurity concentration of the region 3. In some cases, it can be used without containing impurities. Further, since the second polycrystalline silicon 6 is used as it is as a wiring, it is necessary to keep the resistance low. Therefore, the impurity concentration is desirably set to about 1 × 10 ²⁰ cm ⁻³ to 1 × 10 ²¹ cm ^−3, which is higher than the impurity concentration of first polycrystalline silicon 5.

As described above, the present embodiment is characterized in that the first polycrystalline silicon 5 having a low impurity concentration is formed immediately below the second polycrystalline silicon 6 having a high impurity concentration. As shown by arrows, the diffusion of impurities from the second polycrystalline silicon 6 proceeds via the first polycrystalline silicon 5 in the heat treatment after the formation of the wiring step, and as a result, the impurities diffuse in the semiconductor substrate 1. The distance becomes smaller. On the other hand, the diffusion of impurities from the first polycrystalline silicon 5 into the semiconductor substrate 1 can be almost ignored because the impurity concentration of the first polycrystalline silicon 5 is sufficiently lower than the impurity concentration of the source / drain region 3. The diffusion position of the impurity can be substantially suppressed to the position indicated by the broken line 11a. When the impurity concentration of the first polycrystalline silicon 5 is low, there is a concern that the resistance of the connection portion with the semiconductor substrate 1 may increase. However, by suppressing the height of the first polycrystalline silicon 5 from about 20 nm to about 50 nm, Since the rise in resistance is minimized and the impurity concentration of the first polycrystalline silicon 5 is increased by the diffusion of impurities from the second polycrystalline silicon 6, the resistance is actually lower than that at the time of film formation. Almost negligible. In order to further reduce the resistance, a metal silicide layer composed of at least one of nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, aluminum silicide, and ruthenium silicide is laminated and integrated on the upper layer of the second polycrystalline silicon 6. It is also possible to have a so-called polycide structure.

Embodiment 2 FIG. As impurities to be contained in the first polycrystalline silicon 5 and the second polycrystalline silicon 6, phosphorus is generally used for N-type and boron is used for P-type.
Arsenic, antimony, bismuth, gallium, indium, thallium, which is an atom heavier than phosphorus or boron, is added to both the first polycrystalline silicon 5 and the second polycrystalline silicon 6 or only to the second polycrystalline silicon 6. By using at least one of the above, a greater effect can be obtained. That is, since heavy atoms are used as impurities, the semiconductor substrate 1
Diffusion of impurities into the inside becomes slow. In particular, when only the first polycrystalline silicon 5 is contained, it is not always necessary to make the impurity concentration lower than that of the second polycrystalline silicon 6. In some cases this is not a problem.

Embodiment 3 FIG. 3 is a sectional view showing an integrated semiconductor device according to a third embodiment of the present invention. As shown in the figure, the first polycrystalline silicon 5 may be formed on the side surface of the connection hole 12 depending on the film thickness when the first polycrystalline silicon 5 is formed. Since the impurities of the second polycrystalline silicon 6 diffuse through the region of the first polycrystalline silicon 5, the same effect as in the first embodiment can be obtained.

Embodiment 4 In the first embodiment, the first polycrystalline silicon 5 having a low impurity concentration is buried in the inside of the connection hole 12, but the second polycrystalline silicon 6 is formed immediately below the second polycrystalline silicon 6 as shown in FIG. A third polycrystalline silicon 8 having a lower impurity concentration than the polycrystalline silicon 6 is continuously formed, and the second polycrystalline silicon 6 and the third polycrystalline silicon 8 are simultaneously processed to form a third polycrystalline silicon 8. Similar effects can be obtained by using the crystalline silicon 8 as a part of the wiring. At this time, there is a concern that the resistance is increased due to the third polycrystalline silicon 8, but there is almost no problem by the same method as in the first embodiment.

As in the second embodiment, the impurities contained only in the second and third polycrystalline silicon or the third polycrystalline silicon 8 include arsenic and antimony, which are atoms that are heavier than phosphorus and boron. A greater effect can be obtained by using indium gallium or the like. In particular, when only the third polycrystalline silicon 8 is contained, it is not always necessary to make the impurity concentration lower than that of the second polycrystalline silicon 6. In some cases, there is no problem even with the impurity concentration of In order to further reduce the resistance, it is possible to form a so-called polycide structure in which a metal silicide layer is laminated on the second polycrystalline silicon 6 and integrated as in the first embodiment. Needless to say.

Embodiment 5 In the first embodiment, the first polycrystalline silicon 5 having a low impurity concentration is buried in the inside of the connection hole 12, but as shown in FIG. 5, the diffusion of the impurity is performed instead of the first polycrystalline silicon. The same effect can be obtained even if the conductive impurity diffusion preventing layer (hereinafter, referred to as a barrier layer) 9 for preventing the diffusion is formed thin. In this case, there are various materials as the material of the barrier layer 9, but there are titanium nitride and silicon nitride as metal-based materials, and a silicon oxide film (thickness of several Å to 20 Å) which is an insulator. Can also be used as a barrier layer because it has conductivity due to electron tunnel effect. This barrier layer is of course also effective when used in combination with the structures of the first to fourth embodiments.

Embodiment 6 FIG. In the fourth embodiment, the second polycrystalline silicon 6 is located immediately below the second polycrystalline silicon 6.
The third polycrystalline silicon 8 having a lower impurity concentration than that of the second polycrystalline silicon 6 was continuously formed. However, as shown in FIG. The same effect can be obtained even if the film is formed so that the concentration of the impurities is high. The impurity concentration at the start of film formation is approximately the same as that of the first polycrystalline silicon 5 shown in the first embodiment or a state without impurities, and finally the second polycrystalline silicon 5 shown in the first embodiment is formed. It is desirable that the concentration be approximately the same as that of crystalline silicon. Needless to say, the polycide structure of the first embodiment or the barrier layer of the fifth embodiment is also effective.

Embodiment 7 In the fourth embodiment, the second polycrystalline silicon 6 is located immediately below the second polycrystalline silicon 6.
Although the third polycrystalline silicon 8 having a lower impurity concentration than that of the first polycrystalline silicon was continuously formed, as shown in FIG. 7, depending on the respective film thicknesses when the first and second polycrystalline silicon were formed, In some cases, a metal silicide layer 15 such as tungsten silicide formed on the second polycrystalline silicon is formed inside the connection hole 12. Even in this case, the third embodiment is used.
The same effect as described above is obtained, and the resistance of the connection hole 12 is reduced. Embodiment 5 of course
It is needless to say that it is effective even when used together with the barrier layer.

Embodiment 8 FIG. In the first embodiment, the second polycrystalline silicon 6 having a high impurity concentration is formed on the first polycrystalline silicon 5 having a low impurity concentration.
In place of the second polycrystalline silicon 6, a metal silicide layer 15 made of at least one of nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, aluminum silicide, and ruthenium silicide may be formed as shown in FIG. . Also in this case, it can be used together with the barrier layer of the fifth embodiment.

[0034]

As described above, according to the first aspect of the present invention, there is provided an integrated circuit for electrically connecting to an electrically active region formed on a semiconductor substrate using polycrystalline silicon containing impurities. In the semiconductor element, an impurity diffusion preventing layer is formed between the polycrystalline silicon and the semiconductor substrate to prevent the diffusion of the impurity into the semiconductor substrate, so that the impurity of the polycrystalline silicon can be effectively diffused into the semiconductor substrate. It is possible to obtain a high-performance integrated semiconductor device which can be suppressed and does not cause deterioration of device performance such as a MOS transistor.

According to the second aspect of the present invention, a metal silicide compound is formed on polycrystalline silicon.
The effect of further lowering the resistance without increasing the impurity concentration of the polycrystalline silicon can be obtained.

According to the third aspect of the present invention, the first polycrystalline silicon electrically connected to the electrically active region formed on the semiconductor substrate, and the first polycrystalline silicon The second polycrystalline silicon formed thereon, the first polycrystalline silicon and the second polycrystalline silicon are different in any one or both of the impurity type and concentration, so that the polycrystalline silicon impurity Can be effectively suppressed from diffusing into the semiconductor substrate, and an effect of manufacturing a high-performance integrated semiconductor device which does not cause deterioration of device performance such as a MOS transistor can be obtained.

According to the fourth aspect of the present invention, the impurity concentration of the first polycrystalline silicon is lower than the impurity concentration of the second polycrystalline silicon. Can be effectively suppressed from spreading to
The effect is obtained that a high-performance integrated semiconductor device such as a MOS transistor, which does not cause deterioration of device performance, can be manufactured.

According to the fifth aspect of the present invention, since the first polycrystalline silicon is polycrystalline silicon containing no impurity, the impurity does not diffuse into the semiconductor substrate, and the first polycrystalline silicon does not diffuse into the semiconductor substrate. The effect of producing a high-performance integrated semiconductor device that does not cause performance deterioration can be obtained.

According to the sixth aspect of the invention, the impurities of the first polysilicon and the second polysilicon are at least one of phosphorus, boron, arsenic, antimony, bismuth, gallium, indium and thallium. Therefore, the effect of further suppressing the diffusion of impurities into the semiconductor substrate can be obtained.

According to the seventh aspect of the present invention, since the metal silicide compound is formed on the second polycrystalline silicon, the effect of further lowering the resistance without increasing the impurity concentration of the polycrystalline silicon is obtained. can get.

According to the invention of claim 8, the first polycrystalline silicon electrically connected to the electrically active region formed on the semiconductor substrate, and the first polycrystalline silicon With the metal silicide compound formed thereon, the effect of further lowering the resistance without increasing the impurity concentration of polycrystalline silicon can be obtained.

According to the ninth aspect of the present invention, the impurities of the first polycrystalline silicon and the second polycrystalline silicon diffuse into the semiconductor substrate between the first polycrystalline silicon and the semiconductor substrate. Since the impurity diffusion preventing layer is formed, the diffusion of impurities of polycrystalline silicon into the semiconductor substrate can be effectively suppressed, and a high-performance integrated semiconductor device that does not cause deterioration of device performance such as a MOS transistor can be provided. The effect that can be manufactured is obtained.

According to the tenth aspect of the present invention, there is provided a semiconductor device for electrically connecting to an electrically active region formed on a semiconductor substrate using polycrystalline silicon containing impurities. Since silicon is formed by continuously changing the concentration of impurities contained in a layer, the diffusion of impurities of polycrystalline silicon into the semiconductor substrate can be effectively suppressed, and the performance of elements such as MOS transistors does not deteriorate. The effect that a high-performance integrated semiconductor element can be manufactured is obtained.

According to the eleventh aspect of the present invention, since the impurity concentration continuously increases from the lower layer to the upper layer of the polycrystalline silicon, the impurity of the polycrystalline silicon diffuses into the semiconductor substrate. Can be effectively suppressed, and a high-performance integrated semiconductor device that does not cause deterioration of device performance such as a MOS transistor can be produced.

According to the twelfth aspect of the present invention, since the metal silicide compound is formed on the polycrystalline silicon, the effect of further reducing the resistance without increasing the impurity concentration of the polycrystalline silicon can be obtained.

According to the thirteenth aspect of the present invention, an impurity diffusion preventing layer for preventing impurities contained in polycrystalline silicon from diffusing into the semiconductor substrate is formed between the polycrystalline silicon and the semiconductor substrate. Therefore, the diffusion of impurities of the polycrystalline silicon into the semiconductor substrate can be effectively suppressed.
The effect of manufacturing a high-performance integrated semiconductor device that does not cause deterioration of device performance such as an S transistor can be obtained.

According to the fourteenth aspect of the present invention, the impurity contained in the polycrystalline silicon is at least one of phosphorus, boron, arsenic, antimony, bismuth, gallium, indium, and thallium. The effect of further suppressing the diffusion of impurities can be obtained.

According to the fifteenth aspect of the present invention, since the impurity diffusion preventing layer is made of at least one of titanium nitride, silicon oxide and silicon nitride, it is possible to prevent impurities of polycrystalline silicon from diffusing into the semiconductor substrate. Can be effectively suppressed,
The effect is obtained that a high-performance integrated semiconductor device such as a MOS transistor, which does not cause deterioration of device performance, can be manufactured.

According to the present invention, the metal silicide compound is at least one of nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, aluminum silicide, and ruthenium silicide. Is obtained.

According to the seventeenth aspect of the present invention, there is provided a semiconductor device for electrically connecting to an electrically active region formed on a semiconductor substrate using polycrystalline silicon containing impurities. The impurities in silicon are arsenic,
Since it is at least one of antimony, bismuth, gallium, indium, and thallium, the diffusion of impurities of polycrystalline silicon into the semiconductor substrate can be effectively suppressed.
The effect of manufacturing a high-performance integrated semiconductor device that does not cause deterioration of device performance such as an S transistor can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional structural view showing an integrated semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional structural view showing an integrated semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional structural view showing an integrated semiconductor device according to a third embodiment of the present invention;

FIG. 4 is a sectional structural view showing an integrated semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a sectional structural view showing an integrated semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a sectional structural view showing an integrated semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a sectional structural view showing an integrated semiconductor device according to a seventh embodiment of the present invention.

FIG. 8 is a sectional structural view showing an integrated semiconductor device according to an eighth embodiment of the present invention.

FIG. 9 is a sectional structural view showing a conventional integrated semiconductor device.

FIG. 10 is a schematic sectional view for explaining a conventional integrated semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate, 2 element isolation, 3 source / drain region, 4 gate electrode, 5 first polycrystalline silicon, 6
Second polycrystalline silicon, 7 Side wall, 8 Third polycrystalline silicon, 9 Impurity diffusion prevention (barrier)
Layer, 10 polycrystalline silicon with impurity concentration gradient, 1
1. Impurity region diffused from polycrystalline silicon, 12
Connection hole, 13 polycrystalline silicon, 14 interlayer insulating film, 1
5 Metal silicide layer

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yuji Abe 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Yuki Tokuda 2-3-2 Marunouchi 3-chome, Chiyoda-ku, Tokyo Inside Ryo Denki Co., Ltd. (72) Inventor Kazuyuki Sugahara 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Three-Bedroom Incorporated (72) Inventor Tatsuo Omori 2-3-2 Marunouchi, Chiyoda-ku, Tokyo (72) Inventor Kenji Yasumura 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Sanishi Electric Co., Ltd.

Claims (17)

[Claims] 1. An integrated semiconductor device for electrically connecting an electrically active region formed on a semiconductor substrate using polycrystalline silicon containing impurities, wherein the polycrystalline silicon and the semiconductor substrate are connected to each other. An integrated semiconductor device, wherein an impurity diffusion preventing layer for preventing the impurity from diffusing into the semiconductor substrate is formed between the layers. 2. The integrated semiconductor device according to claim 1, wherein a metal silicide compound is formed on polycrystalline silicon. 3. A first polycrystalline silicon electrically connected to an electrically active region formed on a semiconductor substrate, and a second polycrystalline formed on the first polycrystalline silicon. An integrated semiconductor device comprising silicon, wherein one or both of the type and concentration of impurities of the first polycrystalline silicon and the second polycrystalline silicon are different. 4. The integrated semiconductor device according to claim 3, wherein the impurity concentration of the first polysilicon is lower than the impurity concentration of the second polysilicon. 5. The integrated semiconductor device according to claim 3, wherein the first polycrystalline silicon is polycrystalline silicon containing no impurities. 6. The method of claim 1, wherein the impurities of the first polysilicon and the second polysilicon are at least one of phosphorus, boron, arsenic, antimony, bismuth, gallium, indium and thallium. 6. The integrated semiconductor device according to any one of 3 to 5. 7. The method according to claim 3, wherein a metal silicide compound is formed on the second polycrystalline silicon.
The integrated semiconductor device according to any one of the above. 8. A first polycrystalline silicon electrically connected to an electrically active region formed on a semiconductor substrate, and a metal silicide compound formed on the first polycrystalline silicon. An integrated semiconductor device, comprising: 9. An impurity diffusion preventing layer for preventing impurities of the first polysilicon and the second polysilicon from diffusing into the semiconductor substrate is formed between the first polysilicon and the semiconductor substrate. 9. The integrated semiconductor device according to claim 3, wherein: 10. A semiconductor element for electrically connecting an electrically active region formed on a semiconductor substrate using polycrystalline silicon containing an impurity, wherein the concentration of the impurity contained in the polycrystalline silicon is reduced in a layered manner. An integrated semiconductor device characterized by being formed by continuously changing the shape of a semiconductor device. 11. The integrated semiconductor device according to claim 10, wherein the impurity concentration increases continuously from the lower layer to the upper layer of the polycrystalline silicon. 12. The method according to claim 10, wherein a metal silicide compound is formed on polycrystalline silicon.
2. The integrated semiconductor device according to 1. 13. An impurity diffusion preventing layer formed between polycrystalline silicon and a semiconductor substrate to prevent impurities contained in the polycrystalline silicon from diffusing into the semiconductor substrate. The integrated semiconductor device according to any one of claims 12 to 13. 14. The method according to claim 10, wherein the impurities contained in the polycrystalline silicon are at least one of phosphorus, boron, arsenic, antimony, bismuth, gallium, indium, and thallium. 3. The integrated semiconductor device according to claim 1. 15. The integrated semiconductor device according to claim 1, wherein the impurity diffusion preventing layer is at least one of titanium nitride, silicon oxide, and silicon nitride. 16. The metal silicide compound is at least one of nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, aluminum silicide, and ruthenium silicide. An integrated semiconductor device according to claim 1. 17. A semiconductor device for electrically connecting an electrically active region formed on a semiconductor substrate using polycrystalline silicon containing an impurity, wherein the impurity of the polycrystalline silicon is arsenic, antimony, An integrated semiconductor device comprising at least one of bismuth, gallium, indium, and thallium.