JPH10257780A - Control for multi-level inverter and device therewith - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the utilization factor of a DC power source and improve the voltage range which is capable of outputting by adding offset to the voltage commands of respective phases so that the total of the maximum and minimum of the voltage commands which designated the instantaneous values of the respective phases of three-phase alternating current may be zero or zero voltage command value. SOLUTION: Respective voltage commands of the U-phase, V-phase, and W-phase prepared by a voltage command preparation function 1 are inputted in a maximum detection function (max. detection function) 2 which detects the maximum of three voltage commands and outputs it, and a minimum detection function (min. detection function) 3 which detects their minimum. The detected value of the detection function (max. detection function) 2 and the detected value of the min. detection function 3 are inputted in an adding function 4 and added. The added value by the adding function 4 is inputted in a dividing function 5 and divided by 2. That is, a mean value of the maximum and minimum of respective instantaneous three-phase voltage commands is calculated by the adding function 4 and the dividing function 5. It is thus possible to increase utilization factor of a DC power source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method and a control device for a multilevel inverter which is a current converter for converting a direct current of a three-level inverter or the like into an AC phase voltage having a potential of three or more levels. The present invention relates to a control method of a multi-level inverter capable of maximizing the use of a DC power supply voltage and suppressing a fluctuation of a neutral point potential, and a control device for implementing the method.

[0002]

2. Description of the Related Art In recent years, since a switching element having a characteristic capable of self-extinguishing has been put to practical use, an inverter capable of easily obtaining a high-voltage large-capacity AC output with little harmonic distortion has been developed.
Multi-level inverters have been used. The multi-level inverter includes a plurality of capacitors connected in series that divide a supplied DC voltage, and a connection point between the capacitors is set to a predetermined potential, for example, a neutral point potential in the case of a three-level inverter. It has a power conversion function of converting into an AC phase voltage having three or more potentials. The basic configuration of a PWM (pulse width modulation) type output switching circuit of a three-level inverter which has recently attracted attention among many levels is configured as shown in FIG.

In FIG. 10, DA is a three-phase AC power supply line, and 40 is a rectifier circuit. The alternating current rectified by the rectifier circuit 40 is supplied to the positive power line DP and the negative power line DN. Two capacitors 15 and 16 connected in series are connected between the positive power line DP and the negative power line DN. Between the positive power supply line DP and the negative power supply line DN, three-phase AC output U-phase, V-phase, and W-phase
Each phase circuit has self-extinguishing characteristics, for example, IG
Four switching elements such as BT and GTO are connected in series. That is, as a switching element of each phase,
25U, 26U, 36U, 35U for U phase, 2 for V phase
5V, 26V, 36V, 35V, 25W, 26 for W phase
W, 36W, and 35W are connected in parallel.

[0004] Further, a connection point between the capacitors 15 and 16;
A diode 27U is provided between the connection point of the U-phase switching elements 25U and 26U, and the switching elements 36U and 3U are connected to each other.
A diode 37U is connected between the connection point of 5U and the connection point of the capacitors 15 and 16 and the V-phase switching element 25.
A diode 27V is connected between the connection point between V and 26V, a diode 37V is connected between the connection point between the switching elements 36V and 35V, and a connection point between the capacitors 15 and 16 and W
A diode 27W is provided between the connection point of the switching elements 25W and 26W of the phase, and the switching elements 36W and
Diodes 37W are connected between the connection points of W, respectively. An AC load device 41, for example, an induction motor, is connected to a connection point between the U-phase switching elements 26U and 36U, a connection point between the V-phase switching elements 26V and 36V, and a connection point between the W-phase switching elements 26W and 36W. ing.

In the circuit shown in the above figure, a switching pulse is output to each of the above-mentioned switching elements in order to output a frequency and a voltage corresponding to the AC load device 41 at a predetermined frequency from a control device (not shown). Therefore, for example, at the timing of supplying power from the U phase to the AC load device 41, the switching element 26U is turned on during that period, and the switching element 25U is turned on while the switching pulse output from the control device is high. Therefore, when the switching element 25U is turned on, a positive voltage is supplied to the U-phase circuit of the AC load device 41 from the positive power supply line DP, and when the switching element 25U is turned off, the on state of the switching element 26U continues. Therefore, the neutral point potential at the connection point between the capacitors 15 and 16 connected between the positive power supply line DP and the negative power supply line DN via the diode 27U
Connected to phase circuit.

At the timing when the current flows from the AC load device 41 to the U phase, the switching element 36U is turned on during that period, and the switching element 35U is turned on while the switching pulse output from the control device is high. Therefore, when the switching element 35U is turned on,
When a current flows from the U-phase circuit of the AC load device 41 to the negative source line DN and the switching element 35U is turned off,
Since the ON state of the switching element 36U continues, the capacitors 15 and 16 are connected via the diode 37U.
Is connected to the U-phase circuit of the AC load device 41. The V-phase and W-phase operate in the same manner as described above, and a predetermined three-phase AC power is supplied to the AC load device.

In the switching circuit of the three-level inverter described above, the neutral point potential, which is the connection point between the capacitors 15 and 16, is affected by the change in the current flowing through each capacitor from the neutral point corresponding to the switching situation. so,
It fluctuates without reaching the absolute neutral point potential. For this reason, a voltage equal to or higher than the reference value is applied to both ends of the switching element, and there is a risk that the switching element is sometimes destroyed by an overvoltage. Further, since the voltage becomes unbalanced, a desired normal output voltage may not be obtained. In order to prevent the fluctuation of the neutral point potential, the capacitances of the capacitors 15 and 16 may be increased. However, if the capacitors are increased, the cost and the space for arrangement are increased, so that there is a practical limit. For that purpose, various techniques for suppressing the neutral point potential fluctuation have been proposed. For example, a switching pulse output from a control device (not shown) is controlled not by a normal sine wave but by a modulated wave to which a third harmonic or an even harmonic is added.

[0008] There are also techniques disclosed in Japanese Patent Application Laid-Open Nos. 5-227796 and 7-79574. Japanese Unexamined Patent Publication No. 5-227796 discloses a technique that suppresses only a particularly large third harmonic component among fluctuations in neutral point voltage, and controls the amplitude ratio and phase of the third harmonic component for suppression to the fundamental wave. Is constant regardless of the inverter frequency.
It is configured to give a subharmonic component to a fundamental wave command. Also, a table disclosed in Japanese Patent Application Laid-Open No. 7-79574 is a table for adding even-order harmonics (for example, sixth-order harmonics and second-order harmonics) of the inverter fundamental frequency to each phase output voltage command of the inverter. , A multiplier, an adder, etc., and a potential fluctuation at a neutral point of the DC power supply circuit is detected by a voltage deviation of a DC input capacitor, and based on the magnitude thereof, an even harmonic to be added to an output voltage command. Means such as an adder, an adjuster, and a multiplier for determining the size of.

[0009]

By the way, for example, the above-mentioned switching pulse output from the control device is set to three times.
When controlled by a modulated wave to which phase harmonics and even harmonics are added,
In order to utilize the change of the output voltage in order to suppress the voltage fluctuation, for example, as in the correction waveform examples according to the conventional correction method shown in FIGS. 11 and 12, the maximum positive and negative voltages are DC voltages supplied. There is a problem that the voltage range that can be output is narrowed because the signal leveling out is reached. In each of FIGS. 11 and 12, the horizontal axis corresponds to one cycle of the U phase, and the vertical axis sets the zero volt point to 0 and sets the voltage of the positive power supply line DP to +1.
, The voltage of the negative power supply line DN is indicated by -1. In FIG. 11, AX is a correction signal for fixing a predetermined 60-degree section of each phase to ON, AU, AV, and AW are U-phase and V, respectively.
In FIG. 12, BX is a correction signal that gives a potential change at a neutral point at three times the frequency, and BU, BV, and BW are U, respectively. The output operation signal before the PWM processing in which the phase, the V phase, and the W phase are corrected is illustrated.

According to the device disclosed in Japanese Patent Application Laid-Open No. Hei 5-227796 and the circuit disclosed in Japanese Patent Application Laid-Open No. Hei 7-79574, in order to suppress the fluctuation of the neutral point potential, the entire output voltage is reduced. The zero phase is shifted so as to move in parallel. However, when the output voltage is shifted in the plus or minus direction, the maximum voltage on the touched side is limited by the applied DC voltage. Therefore, in order to output a required AC peak voltage, it is necessary to increase the applied DC voltage, and the utilization rate of the DC voltage is reduced.

By the way, even if the potential fluctuation at the neutral point can be reduced to zero and the use efficiency of the space is increased by reducing the size of the capacitor as much as possible, it is impossible to limit the allowable ripple current of the capacitor. In addition, a phase signal for a fundamental wave is required as control information when a harmonic is used for a correction signal. In the above description, a three-level inverter has been described, but a multilevel inverter such as a four-level inverter naturally has the same problem. The present invention solves the above-mentioned problems (problems) of the conventional device, and suppresses the neutral point potential fluctuation and requires phase information within a range where there is no practical problem with an appropriate capacitor capacity calculated from the allowable ripple current. It is an object of the present invention to provide a control method of a multi-level inverter and a device therefor which can increase the utilization rate of a DC power supply and improve the output voltage range by simple means.

[0012]

Means for Solving the Problems The applicant of the present invention has already filed a patent application as disclosed in Japanese Patent Application Laid-Open No. 9-9643, which discloses an invention related to an inverter control method and an apparatus invented by the same inventor as the present application. doing. The technology described in the specification of the prior application is a technology as a two-level inverter that controls and outputs AC power having a predetermined amplitude value.
However, the present invention has been completed by paying attention to the fact that if the technology of the prior application is extended and applied to a multi-level inverter including a three-level inverter, the problems of the above-described conventional technology in the multi-level inverter can be solved. That is, in the multilevel inverter control method according to the present invention, the sum of the maximum value and the minimum value of the voltage commands specifying the instantaneous value of each phase in the three-phase AC is 0 V or the zero voltage command value (DC voltage value). The offset is added to the voltage command of each phase so as to be equal to (a command value corresponding to ２). in this case,
When the phase information can be obtained, the above-described method is applied to the phase angle of the AC signal having the same period and the half of the amplitude of each of the three-phase voltage commands.
30 degrees (330 degrees) to 30 degrees and 150 degrees to 210
The value obtained by adding the degree components for three phases may be added to the voltage command of each phase.

[0013] Further, a control device for performing the above method includes:
A maximum value detection function that detects the maximum value of each of the three-phase voltage commands, a minimum value detection function that detects the minimum value of each of the three-phase voltage commands, and the output and minimum value detection of the maximum value detection function An addition function for adding the output of the function, a division function for halving the addition result of the addition function, and subtracting or adding the output of the division function from each of the three-phase voltage commands. Three sets of voltage command correction calculation functions are provided, and the outputs of the three sets of voltage command correction calculation functions are configured as corrected true voltage commands for each of the three phases.

In this case, when phase information is obtained, 3
Corresponds to the voltage command generation function of generating each voltage command of the phase alternating current, and has a phase angle of −30 degrees (330 degrees) to 30 degrees of the phase angle of the AC signal having the same cycle with half the amplitude of each of the three phase voltage commands. 1
A correction signal generation function for generating and outputting a signal having a continuous component of 50 to 210 degrees, and three sets of voltage command correction calculations for subtracting or adding the output of the correction signal generation function from each of the three-phase voltage commands Function may be provided.

Since the present invention employs the above-described method and the control device, it is possible to suppress the fluctuation of the neutral point potential,
The utilization rate of the DC power supply can be increased up to 100%.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment in which the present invention is applied to a three-phase PWM type three-level inverter which is a typical example of a multi-level inverter shown in FIG.
The second embodiment will be described in detail with reference to FIGS. First Embodiment: FIG. 1 is a block diagram of a third embodiment for carrying out the present invention.
1 shows a configuration of a first embodiment of a control device of a level inverter, and shows a function of generating a gate signal for turning on / off a switching element constituting a three-level inverter (hereinafter, simply referred to as an inverter). The configured inverter circuit itself is omitted, and FIG. 2 shows an inverter circuit unit.

In FIG. 1, reference numeral 1 designates a three-phase voltage command generation function for generating a voltage command for each phase which is specified or set by the host controller of the inverter and specifies the frequency and voltage of the inverter output. The U-phase, V-phase, and W-phase voltage commands generated and output by the voltage command generation function 1 are detected by a maximum value detection function (hereinafter, a MAX detection function) that detects and outputs the maximum value of the three voltage commands. 2) and a minimum value detection function (hereinafter referred to as a MIN detection function) 3 for detecting and outputting the minimum value. The detection value of the MAX detection function 2 and the detection value of the MIN detection function 3 are input to an addition function 4 and added. The value added by the addition function 4 is divided by the division function 5
And divided by 2. That is, the average value of the maximum value and the minimum value of the three-phase voltage commands at each moment is calculated by the addition function 4 and the division function 5. The U-phase voltage command generated and output by the voltage command generation function 1 is input to the first voltage command correction calculation function 6, and the V-phase voltage command is output to the second voltage command correction function 6.
, And the W-phase voltage command is input to a third voltage command correction calculation function 8.

The above-mentioned average value is a voltage command correction signal according to the present invention, and includes a first voltage command correction calculation function 6, a second voltage command correction calculation function 7, and a third voltage command correction function. Each is input to the calculation function 8. The first voltage command correction calculation function 6 outputs an output operation signal SU that is a U-phase corrected true voltage command, and the second voltage command correction calculation function 7 corrects the V-phase. Output operation signal SV
And the third voltage command correction calculation function 8 outputs a W-phase corrected output operation signal SW. The corrected output operation signal of each phase is input to a switching circuit constituting a main circuit of the inverter, which will be described later with reference to FIGS.

FIG. 2 shows a switching circuit constituting a main circuit of the inverter. FIG. 2 is representatively shown because the U, V, and W phase circuits are common. Therefore,
The four first to fourth switching elements connected in series for each phase are 25, 26, 36, and 35, the two diodes for each phase are 27 and 37, and the output operation signals SU, SV, and SW are SS. Are representatively shown. 2, the output operation signal SS is input to the plus terminal of the first comparison circuit 21 and the minus terminal of the second comparison circuit 31. A minus signal terminal of the first comparison circuit 21 and a plus terminal of the second comparison circuit 31 correspond to three phases of a triangular waveform having a predetermined amplitude and a predetermined frequency as shown in FIG. The reference signals TP and TN for PWM are generated,
Each has been entered.

In FIG. 3, TP is a plus-side reference signal having a triangular waveform that changes to a level of 0 or more, and SS is an output operation signal. Therefore, from the first comparison circuit 21, in a range where the output operation signal SS is larger than the plus side reference signal TP,
The plus side gate signal GP that changes between the low level GPn and the high level GPp is output. TN is a negative-side reference signal having a triangular waveform that changes to 0 level or less, and the output operation signal SS is low in a range smaller than the reference signal TN from the second comparison circuit 31 to which the negative-side reference signal TN is input. A negative gate signal GN that changes between the level GNn and the high level GNp is output. Therefore, with a duty ratio proportional to the level of the output operation signal,
The plus side gate signal GP and the minus side gate signal GN change.

In FIG. 2, the plus side gate signal GP output from the first comparison circuit 21 is input to the first dead time circuit 22 and the first polarity inversion circuit 23, and the output of the first polarity inversion circuit 23 is output. Are input to the second dead time circuit 24. The negative gate signal GN output from the second comparison circuit 31 is supplied to the third dead time circuit 32.
And the second polarity inversion circuit 33, and the output of the second polarity inversion circuit 33 is input to a fourth dead time circuit 34. Further, the first dead time circuit 22 is connected to the control gate of the first switching element 25, and the second dead time circuit 24 is connected to the control gate of the third switching element 36. The time circuit 32 is connected to the control gate of the fourth switching element 35, and the fourth dead time circuit 34 is connected to the second switching element 35.
6 is connected to the control gate.

Each of the dead time circuits has a delay in starting the switching element.
In the case of T, about 10 microseconds, each input pulse is cut out to mask the function of the gate signal for each switching element, and the simultaneous operation of each switching element is prohibited. Next, the operation will be described with reference to FIG. For example, during the period in which the plus-side gate signal GP is being output due to each of the above-mentioned gate signals, since the minus-side gate signal GN is not being output, the second switching element 26 is kept on, and the plus-side gate signal is being output. When the signal GP is at the timing of GPp, the first switching element 25 is turned on, and when the plus gate signal GP is at the timing of GPn, the third switching element 36 is turned on.

During the period in which the negative gate signal GN is being output, the third switching element 36 is kept on since the positive gate signal GP is not being output, and the negative gate signal GN is not output. At the timing of GNp, the fourth switching element 35 is turned on, and at the timing of the negative gate signal GN being GNn, the second switching element 26 is turned on.
Thus, in a period in which the positive gate signal GP and outputs, to the power load device from the switching circuit of the inverter, the output operation signal SS to the corresponding current + I _S is supplied, and outputs a negative-side gate signal GN During this period, a current corresponding to the output operation signal SS is supplied to the switching circuit of the inverter from the power load device.
I _S flows. That is, the three-phase AC voltages corresponding to the levels of the U-phase, V-phase, and W-phase voltage commands generated and output by the voltage command generation function 1 are applied to the power load device 41 illustrated in FIG.

Next, the operation of the functional configuration shown in FIG. 1 will be described with reference to FIG. 1 and FIGS. In the above-described functional configuration, the voltage command generation function 1 outputs voltage commands for each phase as shown in FIG. FIG. 4 shows a temporal change (waveform) of the voltage command, wherein the horizontal axis represents one cycle of the U-phase voltage command in units of an angle in which one cycle is 360 degrees, and the vertical axis represents the phase of each phase. The voltage command is indicated by full scale +1 to -1. In the figure, VU is a U-phase voltage command, VV is a V-phase voltage command, and VW is a W-phase voltage command. U-phase voltage command VU, V-phase voltage command V
The V and W phase voltage commands VW correspond to the MAX detection function 2 and M
Input to IN detection function 3. MAX detection function 2 and MIN
The detection values of the respective detection functions 3 are input to an addition function 4 and added, and the added values are input to a division function 5 and divided by two. That is, by the addition function 4 and the division function 5, a correction signal of the voltage command as shown in R in FIG. 5, which is the average value of the maximum value and the minimum value of the three voltage commands at each instant, is obtained.

The correction signal is input to a first voltage command correction calculation function 6, and the first correction command function 6 subtracts the correction signal from the U-phase voltage command to obtain a correction signal SU shown in FIG. The obtained U-phase output operation signal is obtained and input to the second voltage command correction calculation function 7, where the correction signal is subtracted from the V-phase voltage command in FIG. , The corrected V-phase output operation signal is input to the third voltage command correction calculation function 8, and the third voltage command correction calculation function 8 corrects the W-phase voltage command from the W-phase voltage command. By subtracting the signal, a corrected W-phase output operation signal indicated by SW in FIG. 5 is obtained. The correction signal R shown in FIG.
The time-varying waveforms of the voltage command correction signal and the corrected output operation signal of each phase are shown in units of an angle in which one cycle is 360 degrees for one cycle of the U-phase voltage command. By correcting the voltage command of each phase as described above, the neutral point of each phase voltage command is operated, and the maximum value of the line voltage output from the inverter can be used up to the maximum value of the DC voltage.

The correction signal obtained as a result of the above calculation is
The shape is theoretically as shown in FIG. FIG. 6 shows the temporal change (waveform) of the correction signal, and the horizontal axis shows
Time cycle of phase voltage indicating an arbitrary voltage command is set to 36 for one cycle.
The angle of 0 degree is shown as a unit, and the curve a shown on the vertical axis shows the amplitude of the phase voltage by the maximum amplitude +1 to -1. The curve b shown in the figure is a half of the curve a, and the phase angle of the curve b is from -30 degrees (330 degrees) to 30 degrees and 15 degrees.
A curve c having a continuous range of 0 to 210 degrees is the correction signal described above. The above-described temporal change of the correction signal becomes a temporal change of the neutral point potential of the three-phase alternating current that is converted and output by the inverter based on the corrected output operation signal.

In the description of the above embodiment, in each voltage command correction calculation function, the correction signal is subtracted from the voltage command. However, as is apparent from FIG.
Due to the correction signal calculation function, when a correction signal whose phase is deviated by 180 degrees (or of opposite polarity) with respect to the curve c shown in FIG. 6 can be obtained, the calculation function for voltage command correction can be changed to an addition function. Needless to say, the same voltage command can be obtained as the corrected output operation signal of each phase shown in FIG.

FIGS. 7 and 8 show examples of the results obtained by the above-mentioned correction means. FIG. 7 shows the characteristics of the power load device. The horizontal axis indicates the output torque of the power load device in percentage, and the vertical axis indicates the peak value of the neutral point potential fluctuation. Further, j ₁ indicates a state of the conventional PWM method, and k ₁ indicates a state corrected based on the present invention. FIG.
Indicates the modulation rate on the horizontal axis and the voltage utilization rate on the vertical axis. Further, j ₂ indicates a state of the conventional PWM method, and k ₂ indicates a state corrected based on the present invention. That is, according to the present invention, it is possible to theoretically output linearly up to 2 / (3) ^1/2 times of the uncorrected PWM output voltage. Further, according to the correction means described above, the neutral point potential fluctuation can be suppressed within a range in which there is no practical problem with the capacitor capacity calculated from the allowable ripple current.

Second Embodiment: Next, a second embodiment of the present invention will be described with reference to FIG. In the figure, 1
A is a three-phase voltage command generation function for constructing and outputting a U-phase voltage command VU, a V-phase voltage command VV, and a W-phase voltage command VW by digital processing. Is a correction signal generating function for generating and outputting a correction signal R which changes over time shown in FIG. The correction signal R has a first voltage command correction calculation function 6A corresponding to the U phase, a second voltage command correction calculation function 7A corresponding to the V phase, and a third voltage command correction calculation function corresponding to the W phase. 8A. The U-phase voltage command output from the three-phase voltage command creation function 1A is input to the first voltage command correction calculation function 6A, and the V-phase voltage command is output to the second voltage command correction calculation function 7A. The W-phase voltage command is input to the third voltage command correction calculation function 8A. The calculation function for each voltage command correction is a subtraction function when the phase relationship between the voltage command and the correction signal of each phase is as shown in FIG. 6, and the phase relationship between the voltage command and the correction signal with respect to FIG. 1
If it is deviated by 80 degrees (or has a reverse polarity), the addition function may be used. The U-phase corrected output operation signal SU is output from the first voltage command correction calculation function 6A, and the V-phase corrected output operation signal SV is output from the second voltage command correction calculation function 7A. From the voltage command correction calculation function 8A of FIG.
The phase-corrected output operation signal SW is output. The calculation functions for each voltage command correction and thereafter are the same as those in the first embodiment described above, and a description thereof will be omitted.

Third Embodiment: As a third embodiment of the present invention, although not shown, the voltage command creation function shown in the first and second embodiments is the same as that of the second embodiment. Embodiments that can be executed by digital processing are conceivable. In the case of the embodiment having such a configuration, a voltage command equivalent to the directly corrected operation output signal may be created without creating a voltage command and a correction signal for each phase.

The above description shows a basic method for realizing the technical idea of the present invention. It should be noted that it is necessary to appropriately apply and modify the present invention in accordance with the conditions and specifications of the inverter to which the present invention is applied. Of course. For example, in each embodiment, the case where the present invention is applied to a three-level inverter has been described. However, in order to apply the present invention to other multi-level inverters such as a four-level inverter, FIG. The PWM switching circuit configuration may be a circuit configuration suitable for a system corresponding to the number of levels of a target multilevel inverter. Although the functional configuration example of the device that executes the first embodiment has been described as being configured by hardware in FIG. 1, the technical concept based on the present invention is implemented by software in accordance with the control function of the inverter main body. Alternatively, hardware and software may be appropriately mixed.

[0032]

According to the present invention, since the above-described method and the apparatus are configured, the following excellent effects are obtained. By means that does not require phase information, it can be widely applied to any configuration and intended multilevel inverter. Neutral point potential fluctuation can be suppressed within a range where there is no practical problem with the capacitor capacity calculated from the allowable ripple current. Since the utilization rate of the DC power supply can be increased to 100%, the AC peak voltage can be used up to the full applied DC voltage.

[Brief description of the drawings]

FIG. 1 is a schematic configuration block diagram illustrating a basic configuration of a first embodiment of the present invention.

FIG. 2 is a schematic block diagram showing a basic configuration of a PWM switching circuit constituting a main circuit of an inverter to which the present invention is applied.

FIG. 3 is a waveform diagram of a main part showing a basic operation of the PWM switching circuit shown in FIG. 2;

FIG. 4 is a waveform diagram of a temporal transition illustrating a voltage command of each phase according to the first embodiment.

FIG. 5 is a waveform diagram of a temporal transition for explaining a relationship between a corrected voltage command of each phase and a correction signal in the first embodiment.

FIG. 6 is a waveform diagram of a temporal transition illustrating a correction signal according to the first embodiment.

FIG. 7 is a characteristic diagram for comparing neutral point potential fluctuations between the first embodiment and the conventional method.

FIG. 8 is a characteristic diagram for comparing the voltage utilization ratio between the first embodiment and the conventional method.

FIG. 9 is a schematic configuration block diagram illustrating a configuration of a second exemplary embodiment of the present invention.

FIG. 10 is a schematic block diagram of an inverter to which the present invention and the prior art are applied.

FIG. 11 is a waveform diagram of a temporal change of a corrected voltage command and a correction signal of each phase according to an example of a conventional voltage command correction unit.

FIG. 12 is a waveform diagram of a voltage command of each phase and a temporal transition of a correction signal, which are corrected by another example of the conventional voltage command correction means different from FIG.

[Explanation of symbols]

1, 1A: Voltage command creation function 1Aa: Correction signal creation function 2: MAX detection function (maximum value detection function) 3: MIN detection function (minimum value detection function) 4: Addition function 5: Division function 6, 7, 8 , 6A, 7A, 8A: Calculation function for voltage command correction (addition function or subtraction function) 15, 16: Capacitor 21, 31: Comparison circuit 23, 33: Polarity inversion circuit 22, 24, 32, 34: Dead time circuit 25 , 26, 35, 36: Switching element 27, 37: Diode SU, SV, SW, SS: Output operation signal TP, TN: Reference signal

Claims (4)

[Claims] In a multi-level inverter for converting DC power into three-phase AC power, the sum of a maximum value and a minimum value of voltage commands that specify instantaneous values of each phase in three-phase AC is 0 V.
Alternatively, a method of controlling a multi-level inverter, wherein an offset is added to a voltage command of each phase so as to be equal to a zero voltage command value (a command value corresponding to の of the DC voltage). 2. A maximum value detecting function for detecting a maximum value of each voltage command specifying an instantaneous value of each phase in a three-phase alternating current, and a minimum value detecting a minimum value of each of said three phase voltage commands. A value detection function, an addition function for adding the output of the maximum value detection function and the output of the minimum value detection function, a division function for halving the addition result of the addition function, and an output of the division function. And three sets of voltage command correction calculation functions for subtracting or adding values from the three-phase voltage command values. The output of the three sets of voltage command correction calculation functions is a true voltage of each of the three phases. A control device for a multi-level inverter, wherein the control device is a command. 3. A multi-level inverter for converting DC power into three-phase AC power, wherein the phase of an AC signal having the same cycle as an amplitude of 1/2 of each voltage command specifying an instantaneous value of each phase in three-phase AC. A method for controlling a multilevel inverter, characterized in that a value obtained by adding components of angles of −30 degrees (330 degrees) to 30 degrees and 150 degrees to 210 degrees for three phases is added to a voltage command of each phase. 4. A three-phase AC corresponding to a voltage command generating function for generating a voltage command for designating an instantaneous value of each phase, the AC having the same cycle and an amplitude of 1/2 of each voltage command of the three phases. -30 degrees (330 degrees) to 30 degrees and 15 degrees of the phase angle of the signal
A correction signal generation function for generating and outputting a signal obtained by adding the components of 0 to 210 degrees for three phases, and three sets for subtracting or adding the output value of the correction signal generation function from each of the three-phase voltage command values A multi-level inverter control device, comprising: