JPH10233578A - Method for forming insulating layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an insulating layer of high flatness with good efficiency by a method wherein a dummy pattern is formed in the gap between conductor patterns and, in this state, both faces of a base material are coated simultaneously with a high-viscosity resin material. SOLUTION: Both faces of a core board 2 which constitutes a multilayr printed-wiring board are provided with inner-layer conductor patterns 3, and dummy patterns 5 are formed in parts in which the width of gaps 4 between the inner-layer conductor patterns 3 is large. Then, in this state, both faces of a base material 15 are coated simultaneously with resin varnishes V1, V2 as high-viscosity resin materials, so that an interlayer insulating layer 6 which comprises a first insulating layer 7 and a second insulating layer 8 is applied. Thereby, the interlayer insulating layer of high flatness can be formed, and an exposure fog can be prevented surely. As a result, the formation accuracy of an outer-layer conductor pattern or the like can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for forming an insulating layer.

[0002]

2. Description of the Related Art In the manufacture of printed wiring boards, there is a step of forming an insulating layer by applying a resin material to a base material having a conductor pattern. As an example, formation of an interlayer insulating layer in the production of a multilayer printed wiring board by a full additive process can be cited. The procedure will be briefly described below with reference to FIGS.

[0003] First, a copper-clad laminate is used as a starting material,
A core substrate 33 having an inner conductor pattern 32 on both surfaces of a substrate 31 is manufactured. Next, after applying a varnish of a photosensitive resin to the core substrate 33, drying, exposure and development are performed. A mask 35 is brought into close contact with the interlayer insulating layer 34 thus obtained (see FIG. 8), and a via hole forming hole 36 is formed by photolithography. Thereafter, surface roughening treatment, application of catalyst nuclei, formation of a permanent resist 37, and electroless copper plating are performed to form an outer layer conductor pattern 38 and a via hole 39 (see FIG. 9).

[0004] When a curtain coater or the like is used as a coating device, it is necessary to apply varnish to one surface first, and then turn over the remaining surface. That is, in this type of apparatus, coating cannot be performed simultaneously on both surfaces. Therefore, it has been proposed in recent years to improve workability by performing simultaneous double-sided coating using a vertical roll coater that processes the core substrate 33 in an upright state. When this type of apparatus is used, some measures have been taken, such as setting the viscosity of the varnish to be higher in order to prevent dripping of the varnish.

[0005]

However, in the method of simultaneous double-sided coating using a vertical roll coater, since the viscosity of the resin varnish is set to be high, unlike the case where a low-viscosity varnish is used, the flow is different. Can not be expected to have a leveling effect. Therefore, the inner layer conductor pattern 3
If there is a large gap 40 between the two, the varnish falls there, and it is easy for the entire surface of the interlayer insulating layer 34 to undulate. In addition, such undulations cause exposure fogging and defective mounting.

The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a method for forming an insulating layer capable of efficiently forming an insulating layer having high flatness.

[0007]

In order to solve the above-mentioned problems, according to the first aspect of the present invention, a high-viscosity resin material is applied to a base material having a conductor pattern to cover the conductor pattern. In the method for forming an insulating layer,
A gist of the present invention is a method for forming an insulating layer, characterized in that a dummy pattern is provided in a gap between the conductor patterns, and the high-viscosity resin material is simultaneously applied to both surfaces of the base material in that state.

According to a second aspect of the present invention, in the first aspect, the high-viscosity resin material is applied by a vertical roll coater. According to a third aspect of the present invention, in the first or second aspect, the conductor pattern has a thickness of 20 mm.
μm ~ 40μm, the dummy pattern, the clearance between itself and the conductor pattern is 0.5mm
It is assumed that the distance is set to be less than.

Hereinafter, the "action" of the present invention will be described. According to the first aspect of the present invention, since the gap between the conductor patterns is filled with the dummy pattern, the width of the gap is substantially reduced. Therefore, the resin material is less likely to fall into the gap during application, and undulation of the resin material is suppressed. As a result, the flatness of the formed insulating layer is improved. Further, by simultaneously applying the resin material to both surfaces of the base material, the insulating layer is efficiently formed. Further, the dummy pattern provided between the gaps can be formed simultaneously with the conductor pattern. Therefore, no special process is required for forming the dummy pattern, and there is no fear that the workability is deteriorated.

According to the second aspect of the present invention, since the vertical roll coater is a coating apparatus suitable for simultaneous double-side coating, the high-viscosity resin material is surely and quickly coated on both sides of the base material. Therefore, waviness is more reliably suppressed, and the efficiency of forming the insulating layer is higher.

According to the third aspect of the present invention, by providing the clearance to be less than 0.5 mm, the amount of undulation is suppressed to within 10 μm.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a multilayer printed wiring board according to an embodiment of the present invention will be described below in detail with reference to FIGS.

As shown in FIGS. 1 and 3 (e), a core substrate 2 constituting a multilayer printed wiring board 1 of the present embodiment
Has an inner conductor pattern 3 on both surfaces thereof. Where the width of the gap 4 between the inner conductor patterns 3 is large,
A dummy pattern 5 is provided. The inner conductor pattern 3 and the dummy pattern 5 are covered with an interlayer insulating layer 6. Here, the interlayer insulating layer 6 includes a first insulating layer 7 and a second insulating layer 8. The surface of the second insulating layer 8 located on the surface layer is a roughened surface 8a having a large number of minute anchor recesses. A permanent resist 9 is formed on the roughened surface 8a, and an outer conductor pattern 10 is formed in a portion where the permanent resist 9 is not formed. Also,
The inner conductor pattern 3 and the outer conductor pattern 10 are:
They are electrically connected by via holes 11 provided in the interlayer insulating layer 6. That is, the inner conductor pattern 3 and
A buildup layer is formed by the outer layer conductor patterns 10 and the interlayer insulating layer 6 that insulates them.

Next, a procedure for manufacturing the multilayer printed wiring board 1 will be described. First, as shown in FIG. 3A, FR-4 formed by bonding copper foil 16 on both surfaces of a base material 15
Grade copper-clad laminate 17 was prepared as a material for manufacturing core substrate 2. The thickness of the copper foil 16 was 35 μm. Using the copper-clad laminate 17, etching was performed by a conventionally known subtractive method to form inner layer conductor patterns 3 on both front and back surfaces. At the same time, the dummy pattern 5 was also formed in the gap 4 between the inner layer patterns 3 (see FIGS. 1 and 3 (b)). Then, in this state, the interlayer insulating layer 6 was formed by simultaneously applying resin varnishes V1 and V2 as a high-viscosity resin material to both surfaces of the base material 15.

FIGS. 2A and 2B schematically show the main part of a coating apparatus (vertical roll coater) used in the present embodiment. The vertical roll coater
It has a pair of rolls R1 standing upright. Then, the core substrate 2, which is the object to be coated, passes between these rolls R1 to form a resin varnish V1.
, V2 are applied simultaneously on both sides. Here, photosensitive resin varnishes V1 and V2 are used.

Further, the direction of travel of the base material when the resin varnishes V1, V2 are applied by the vertical roll coater is preferably a direction perpendicular to the direction in which the inner conductor pattern 3 extends (FIG. 2 (b)). )). Test results relating to this will be described later.

Here, the resin varnish V1 for forming the first insulating layer 7 is prepared as follows. First, 60 parts by weight of cresol novolak type epoxy resin (manufactured by Kyoeisha) and bisphenol A type epoxy resin (manufactured by Yuka Shell)
40 parts by weight, 5 parts by weight of an imidazole-type curing agent (manufactured by Shikoku Chemicals), 5 parts by weight of a photosensitive monomer (manufactured by Kyoeisha), 5 parts by weight of a photoinitiator (manufactured by Kanto Chemical), and 0.5 parts by weight of a photosensitizer Was prepared. Then, 70% by weight of this raw material
And 30% by weight of ceramic fine powder (trade name, manufactured by Tatsumori, trade name: Admafine, average particle size: about 2 μm). Further, while adding diethylene glycol diethyl ether to the mixture, the viscosity of the mixture was higher than usual by homodisper, that is, 3000 cp.
Adjusted to s ~ 7000 cps. And this mixture is 3
The desired resin varnish V1 was obtained by kneading using this roll.

The resin varnish V2 for forming the second insulating layer 8 is prepared as follows. First, the ceramic fine powder dispersed in the resin varnish V1 was changed to an epoxy fine powder (trade name, manufactured by Toray Co., Ltd .; Trepearl, average particle size: about 3 μm), and the others were the same as the resin varnish V1. V2 was adjusted. The viscosity of the resin varnish V2 was made higher than usual, that is, 8,000 cps to
It was adjusted to 12000 cps.

Here, the resin varnish V at the time of coating is used.
1, The viscosity of V2 is preferably from 2000 cps to 100,000 cps, preferably from 5000 cps to 20,000 cps, and most preferably from 8,000 cps to 15,000 cps.

If the value of the viscosity is too small, the resin varnish V1
, V2 are sagged due to the inclination of the base material 15, and it is impossible to apply the double-sided coating by the vertical roll coater.
On the other hand, if the viscosity value is too large, the resin varnishes V1, V2
Owing to a low fluidity, the coating operation becomes difficult.

After the preparation of the two types of resin varnishes V 1 and V 2, the first resin varnish V 1 was first applied to the core substrate 2 using a vertical roll coater. Further, the applied resin varnish V1 was dried at 80 ° C. for 15 minutes so that the resin varnish V1 did not adhere even if touched with a finger. Thus, the first insulating layers 7 were formed on both surfaces of the core substrate 2 (see FIG. 3C).

Subsequently, a resin varnish V2 was applied to the surface of the first insulating layer 7 using the same vertical roll coater, and dried at 80 ° C. for 15 minutes to make it dry to the touch. Thereby, the second insulating layer 8 was formed on the surface of the first insulating layer 7.

In this manner, the surface of the core substrate 2 is provided with a first insulating layer 7 having a thickness of 40 to 60 μm and a thickness of 20 to 40 μm.
m of the second insulating layer 8 was covered.
Next, a predetermined mask was brought into close contact with the front and back surfaces of the core substrate 2 for forming the via hole forming holes 18 by photolithography. In this state, the interlayer insulating layer 6 was exposed by a parallel exposure machine (Oak Seisakusho, trade name; 401B type). The exposure amount was 400 mJ / cm ² . Next, development was performed using a developer (trade name: Eterna IR, manufactured by Asahi Kasei Corporation). As a result, a via hole forming hole 18 was formed in a predetermined portion of the interlayer insulating layer 6.

Next, 3 J / c using an ultraviolet irradiation device.
By irradiating m ² ultraviolet rays, the interlayer insulating layer 6 was temporarily cured. Further, 100 with respect to the core substrate 2
The interlayer insulating layer 6 was fully cured by sequentially performing a heat treatment at 1 ° C. for 1 hour and a heat treatment at 150 ° C. for 3 hours.

Next, a chromic acid (Cr) having a concentration of 800 g / l
By immersing the core substrate 2 in ₂ O ₃ ) for 20 minutes, the resin filler dispersed only in the second insulating layer 8 was selectively dissolved. By such a surface roughening treatment of the interlayer insulating layer 6, a roughened surface 8a having a large number of concave portions for anchors was formed on the surface of the interlayer insulating layer 6. The average depth of the anchor recess was 15 to 25 μm. Thereafter, the core substrate 2 was immersed in the neutralizing solution and washed with water.

Next, using a commercially available chemical copper plating catalyst nucleation system (made by Shipley), the roughened surface 8
A palladium catalyst nucleus was applied to a and the inner wall surface of the via hole forming hole 18. Then, by heating the core substrate 2 at 120 ° C. for 40 minutes, the palladium catalyst nucleus was fixed to the roughened surface 8 a and the inner wall surface of the via hole forming hole 18.

Subsequently, a permanent resist 9 was formed on the surface of the core substrate 2 as follows. First, a photosensitive liquid resist (manufactured by San Nopco, trade name: Nopco Cure L)
100 cps to 15 using butyl cellosolve acetate
The viscosity was adjusted to 0 cps. Next, a liquid liquid resist was uniformly applied to both front and back surfaces of the core substrate 2 using a roll coater (trade name: MRC6510, manufactured by Thermotronics Trading). Next, the liquid resist layer was brought into a touch-dry state by drying at 80 ° C. for 30 minutes. 3 μm thick
７7 μm.

Further, a photosensitive dry film (trade name: Nopcocure F, manufactured by San Nopco) was laminated on the surface of the liquid resist layer in a dry state to the touch. Laminate is laminator (manufactured by Hakuto, trade name: MACH-500)
This was performed using At that time, the conveyor speed was 1.0m / m
in, roll pressure 2 kg / cm ² , roll temperature 95
° C.

Thus, a permanent resist 9 composed of a liquid resist layer and a dry film was formed on the entire roughened surface 8a of the interlayer insulating layer 6. Next, an exposure mask is arranged on the surface of the core substrate 2, and in this state, an exposure machine (manufactured by Hakuto, HA
(P24LRD). Exposure amount is 350m
J / cm ² . Thereafter, development was performed using a spray developing machine. Then, using the above-described ultraviolet irradiation device, 3
The permanent resist 9 was provisionally cured by irradiating ultraviolet rays of J / cm ² . Next, 15 for the core substrate 2
The permanent resist 9 was fully cured by heating at 0 ° C. for 30 minutes. The thickness of the permanent resist 9 after the main curing is 40 μm
６０60 μm.

Next, by immersing the core substrate 2 in an electroless copper plating bath for additive, copper plating having a thickness of 28 μm was deposited on a portion where the permanent resist 9 was not formed. As a result, as shown in FIG.
The outer layer conductor pattern 10 was formed on the roughened surface 8a. At the same time, the via holes 11 were formed by depositing copper plating on the inner wall surfaces of the via hole forming holes 18.

Next, the formation of the dummy pattern 5 will be described in more detail. In the graph of FIG. 4, the vertical axis indicates the amount of undulation (μm) on the surface of the interlayer insulating layer 6 when the thickness of the inner conductor pattern 3 is 35 μm. The horizontal axis indicates the size (mm) of the gap 4 of the inner conductor pattern 3. A curve C1 shown in the graph of FIG. That is, this is an example in which no dummy pattern 5 is provided in the gap 4. The curves C2 and C3 are both data of the present embodiment,
That is, the data when the dummy pattern 5 is provided in the gap 4 is shown. More specifically, the curve C2 is data when the substrate traveling direction is set as shown in FIG. 2A, and the curve C3 is data when the substrate traveling direction is set as shown in FIG. 2B. .

According to the above graphs, in all cases, the point where the peak of the swell amount is common when the gap 4 is 2.5 mm to 3.0 mm is common. It is also common that the swell amount decreases as the size of the gap 4 becomes smaller than the peak.

However, when the curves C1, C2, C3 are compared, the curves C2, C2 of the present embodiment are more excellent than the curve C1 of the conventional example.
It can be seen that the amount of undulation is smaller in C3. In addition, it can be understood that the undulation amount is further reduced if the base material traveling direction is a direction parallel to the direction in which the inner conductor pattern 3 extends. Further, in the curves C2 and C3, when the gap 4 is less than 0.5 mm, the amount of undulation is surely 10 μm.
It turns out that it becomes lower. Therefore, the undulation amount is 10μ.
If it is desired to keep the value at m or less, for example, the conditions may be set as follows. That is, when the thickness of the inner conductor pattern 3 is 20 μm to 40 μm, the clearance 4 a between the dummy pattern 5 itself and the inner conductor pattern 3 is set to less than 0.5 mm.

This will be described with reference to FIG. In the figure, four inner layer conductor patterns 3 exist on a base material 15. Three of them are in a linear and parallel relationship, and the gap 4 between them is also much smaller than 0.6 mm. On the other hand, the other one is bent at one place unlike the others. Accordingly, the gap 4 between the inner conductor pattern 3 and the inner conductor pattern 3 adjacent thereto is partially large. In the first dashed area H1 of FIG.
The size of the gap 4 is less than 0.5 mm. For this reason, it is not necessary to provide the dummy pattern 5 in this portion. On the other hand, in the second broken line region H2 in FIG. 1, the size of the gap 4 is 0.5 mm or more. Therefore,
The dummy pattern 5 is provided in this portion. In this case, the value of the clearance 4a is set to 0.
Set to less than 5 mm.

Incidentally, if the thickness of the inner conductor pattern 3 is 1
When the thickness is 0 μm to 20 μm, the dummy pattern 5 is preferably provided such that the clearance 4a is less than 1.0 mm. The thickness of the inner conductor pattern 3 is 4
When the thickness is 0 μm to 60 μm, the dummy pattern 5 is preferably provided such that the clearance 4a is less than 0.3 mm.

Next, the characteristic effects of this embodiment will be listed. (A) In the present embodiment, the dummy patterns 5 are provided in the gaps 4 between the inner conductor patterns 3, and in this state, resin varnishes V1 and V2, which are high-viscosity resin materials, are simultaneously applied to both surfaces. Therefore, a portion of the gap 4 having a large space is filled with the dummy pattern 5 having the same height. Therefore, the width of the gap 4 is substantially reduced. Therefore, the resin varnishes V1 and V2 hardly fall into the gap 4 during coating. As a result, the undulation of the surface of the formed interlayer insulating layer 6 is suppressed, and the flatness of the interlayer insulating layer 6 is improved. Therefore, the exposure fog, which has conventionally been regarded as a problem, is reliably prevented. That is, as a result of improving the adhesiveness when the mask is arranged on the interlayer insulating layer 6, there is no partial gap between the two. This leads to an improvement in the opening accuracy of the via hole forming hole 18 and an improvement in the formation accuracy of the outer layer conductor pattern 10.

(B) Further, according to the method of this embodiment in which both surfaces are coated simultaneously, compared to the method of coating one surface at a time,
The interlayer insulating layer 6 can be efficiently formed. Especially,
Here, since a vertical roll coater, which is a coating apparatus suitable for simultaneous double-side coating, is used, a high-viscosity resin varnish V
1, V2 can be applied reliably and quickly. Therefore, use of this device contributes to further improvement in the efficiency of forming the interlayer insulating layer 6 and more reliable suppression of undulation.

(C) Further, since the dummy pattern 5 can be formed simultaneously with the inner conductor pattern 3, there is no need for a special process for forming the dummy pattern 5 and there is no fear that the workability is deteriorated. In addition, since both 3 and 5 are derived from the copper foil 16 of the same copper-clad laminate 17, they have the same height.

(D) Since the surface of the core substrate 2 on which the interlayer insulating layer 6 is formed by the above method is higher than that of the conventional one, polishing of a belt sander or the like is performed even if nodules are generated after plating. Can be uniformly and easily removed.

It should be noted that the present invention is not limited to the above embodiment, but can be changed to, for example, the following forms. The interlayer insulating layer does not necessarily have to have a two-layer structure. For example, as in another example of a multilayer printed wiring board 21 shown in FIG. Note that the interlayer insulating layer 6 is composed of only the second insulating layer 8 of the embodiment.

The printed wiring board 26 of another example shown in FIGS. 6 and 7 has a plurality of pads 22 as conductor patterns. In the figure, these pads 22 have a circular shape and are separated by a gap 24. Further, the entire base material 15 is covered with a solder resist 25 as an insulating layer, and the pad 22 is exposed from an opening 27 of the solder resist 25. And the pad 22
Are surrounded by the dummy pattern 23. Therefore, the dummy pattern 23 is also present between the gaps 24. When the thickness of the pad 22 and the dummy pattern 23 is 20 μm to 40 μm, the clearance 24 a between the dummy pattern 23 and the pad 22 is preferably less than 0.5 mm. The reason is as described above. If the two-sided simultaneous coating is performed on the core substrate 2 configured as described above, the solder resist 25 having high flatness can be efficiently formed.

The pad 22 may be formed as an outer conductor pattern. In this case, the printed wiring board 2
If CSP 6 is used for CSP, the height of the bump formation surface is less likely to vary, resulting in an advantage that mounting defects are reliably prevented.

The application of high-viscosity resin varnishes V1 and V2 by a coating device other than the vertical roll coater used in the embodiment, for example, screen printing or the like, is also permitted.
However, a vertical roll coater is superior to the others in that it is suitable for simultaneous double-side coating.

Here, in addition to the technical ideas described in the claims, the technical ideas grasped by the above-described embodiments are listed below together with their effects. (1) The method for forming an insulating layer according to claim 1, wherein the dummy pattern has substantially the same height as the conductor pattern around the dummy pattern.

(2) In Claims 1 to 3, the viscosity of the high-viscosity resin material at the time of coating is from 2000 cps to 10
0000cps (preferably 5000cps to 20000cp
s, most preferably 8,000 cps to 15,000 cps). According to this method, sagging hardly occurs even when the coating is performed in a state where the base material is set up, so that the simultaneous double-side coating can be easily performed.

(3) In the above (1) to (3), when the high-viscosity resin material is applied by the vertical roll coater, the direction of travel of the base material extends from the conductive pattern formed on the base material. A method for forming an insulating layer, wherein the direction is parallel to the direction. According to this method, undulation on the surface of the insulating layer can be suppressed more reliably.

(4) In Claims 1-3, the conductor pattern is an inner layer conductor pattern constituting a build-up layer, and the insulating layer is an interlayer insulator for insulating the inner layer conductor pattern and the outer layer conductor pattern. A method for forming an insulating layer, which is a layer. According to this method, an interlayer insulating layer having high flatness is formed, and exposure fog is reliably prevented. As a result, it is possible to improve the formation accuracy of the outer layer conductor pattern and the like.

The technical terms used in the present specification are defined as follows. "Build-up layer: A layer formed by alternately laminating insulating layers and conductor layers."

[0049]

As described in detail above, according to the first to third aspects of the present invention, the swelling of the surface of the insulating layer can be suppressed and the workability of the insulating layer can be improved. A forming method can be provided.

According to the second aspect of the present invention, undulation on the surface of the insulating layer can be suppressed more reliably, and the efficiency of forming the insulating layer can be further increased. According to the third aspect of the present invention, the amount of undulation on the surface of the insulating layer can be suppressed to within 10 μm.

[Brief description of the drawings]

FIG. 1 is a partial plan view showing a base material before an insulating layer is formed in an embodiment embodying the present invention.

FIG. 2A is a schematic perspective view showing a state in which a base material is advanced along a direction in which a gap extends, and FIG. 2B is a schematic view showing a state in which the base material is advanced in a direction perpendicular thereto. Perspective view.

FIGS. 3A to 3E are schematic cross-sectional views illustrating a procedure for manufacturing a multilayer printed wiring board.

FIG. 4 is a graph showing a relationship between a gap and an undulation amount.

FIG. 5 is a schematic sectional view showing another example of a multilayer printed wiring board.

FIG. 6 is a partial plan view showing a base material before an insulating layer is formed in another example.

FIG. 7 is a schematic cross-sectional view showing a state after forming an insulating layer on the base material of FIG. 6;

FIG. 8 is a schematic cross-sectional view showing a state after formation of an insulating layer of a base material in a conventional technique.

FIG. 9 is a schematic sectional view showing a conventional multilayer printed wiring board.

[Explanation of symbols]

3. Inner layer conductor pattern as conductor pattern, 4, 24
... gap, 5 ... dummy pattern, 8 ... interlayer insulating layer as insulating layer, 10 ... outer layer conductive pattern as conductor pattern, 15 ... substrate, 22 ... pad as conductive pattern, 25 ... solder resist as insulating layer, V1, V
2… Resin varnish as a high-viscosity resin material.

Claims (3)

[Claims] 1. A method for forming an insulating layer covering a conductor pattern by applying a high-viscosity resin material to a base material having the conductor pattern, wherein a dummy pattern is provided in a gap between the conductor patterns. The method for forming an insulating layer, wherein the high-viscosity resin material is simultaneously applied to both surfaces of the substrate in that state. 2. The method according to claim 1, wherein the high-viscosity resin material is applied by a vertical roll coater. 3. The conductor pattern has a thickness of 20 μm to 40 μm.
3. The method of claim 1, wherein when the thickness is μm, the dummy pattern is provided such that a clearance between the dummy pattern and the conductor pattern is less than 0.5 mm. 4.