JPH1021182A - Interrupt processing system and controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To promptly deal with the interrupt given from a controller which is connected to an extension bus. SOLUTION: The input/output controllers 160 to 163 connected to an extension bus 15 can be inputted to and outputted from any of interruption lines int(a) to int(d) of the bus 15. The interrupt factor registers of IOC 160 to IOC 163 can show a a specific IOC that caused an interrupt factor. Receiving an interrupt request from a bus adapter 130 via a host bridge 11, a CPU 10 reads one of interrupt factor registers of the IOC 160 to IOC 163. Thus, the IOC that caused an interrupt factor can be known and an access is given to this IOC for execution of the interrupt processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing method and a control device which are particularly suitable for processing an interrupt from an input / output control device connected to an expansion bus.

[0002]

2. Description of the Related Art In order to transmit an interrupt from an input / output control unit (IOC) connected to a bus such as a PCI bus or a VME bus to a processor, a dedicated interrupt line is provided for each slot of the bus. . The number of interrupt lines is from 4 to 16 (4 on the PCI bus, VME
7 buses), which is relatively small.

In a relatively small-scale system such as a personal computer or a workstation, the number of input / output control devices connected to the bus is usually one to four. Few. However, some systems require more input / output controllers than the number of interrupt lines.

In such a case, a bus adapter for further expanding the bus is connected to any one slot on the bus, and an input / output controller is connected to each slot on the expanded expansion bus. At this time, there is a problem of processing an interrupt from the input / output control device connected to the extension bus.

FIG. 5 is a block diagram of a conventional computer system with a bus extension. In this example,
Both the basic bus and the expansion bus are PCI buses.

In this system, the 0th bus on the basic bus 12
Interrupt lines intA to intD are assigned to each of the slots 12a to 12d. A bus adapter 430 is connected to the 0th slot 12a, and an expansion bus 15 is connected to the bus adapter 430 to extend the bus. Interrupt lines inta to intd are also assigned to the 0th slot 15a to the third slot 15d on the expansion bus 15, respectively. Although it is written separately in the figure, the interrupt line i
ntA to intD and inta to intd constitute part of the buses 12 and 15, respectively. Also, the input / output control devices IOC-B131 to IOC-D133, IOC
-A'460 to IOC-d'463 are all connected to an input / output device (not shown).

Here, the IOC connected to the basic bus 12
-B131 to IOC-D133, if an interrupt factor (including an interrupt factor generated by a connected input / output device; the same applies hereinafter), an interrupt line i
The CPU 10 is notified via the ntB to intD and the host bridge 11 that an interrupt factor has occurred. At this time, the host bridge 11 can determine which IOC has issued the interrupt request. However, the IOC-a'460-IOC-d 'connected to the extension bus 15
If an interrupt factor occurs in any of the I / O modules 463, the host bridge 11 cannot directly determine which IOC has issued the interrupt request. IOC-a'46
This is because even if an interrupt factor occurs in any of 0 to IOC-d'463, the host bridge 11 can only determine that an interrupt request has been issued from the bus adapter 430.

Accordingly, IOC-a'460-IOC-
If an interrupt factor occurs in any of d'463, there must be means for determining which IOC has issued the interrupt request.

[0009] As a device which realizes this determination means by hardware, there is a bus expansion device of an information processing device described in JP-A-2-230356. FIG. 6 is a block diagram of this bus expansion device, and FIG.
Shown in

In this bus expansion apparatus, when a slave 34 (one of a plurality of slaves) provided on an expansion bus 35 outputs an interrupt signal 37, the interrupt signal 37 is converted into one of a plurality of interrupt signals 38. The signal is input to the OR circuit 33. Then, a signal 39 of a predetermined level is output from the OR circuit 33 to the basic bus 36. At the same time,
A predetermined level bit of the interrupt signal 38 of the register 32 is turned ON. When the central processing unit 31 provided on the basic bus 36 receives the interrupt signal (S31), if the interrupt signal is the interrupt level assigned to the expansion bus 35, the central processing unit 31 accesses the register 32 in the expansion device (S3).
2). Then, it checks which interrupt level on the extension bus 35 is being output (S33, S34), and accesses the slave 34 corresponding to the interrupt level to perform processing (S35).

In order to extend the bus according to this example, it was necessary to provide an OR circuit and a register, but these had to be provided in the expansion device. Referring to the example of FIG. 5, in order to determine which IOC on the expansion bus caused the interrupt, an interrupt line must be drawn into the bus adapter 430 and an OR circuit and a register must be provided in the bus adapter 430. I had to.

By the way, as for standard input / output buses such as a PCI bus and a VME bus, a large number of bus bridge chips in which functions are provided in a single chip for bus expansion are commercially available. However, these commercially available bus bridge chips are not configured to capture a dedicated interrupt line in order to avoid an increase in cost due to an increase in the number of pins.

On the other hand, in order to shorten the development period of the device and reduce the cost, it is more advantageous to configure the bus adapter using a commercially available bus bridge chip. In particular, changing the configuration of basic hardware such as a bus adapter is more expensive than changing the configuration of peripheral hardware. Therefore, in a bus adapter as a bus expansion device that is currently commercialized, the determination of which device on the expansion bus caused the interrupt factor is entirely left to software (interrupt processing routine) processing.

FIG. 8 is a flow chart showing the operation of this interrupt processing routine. First, when an interrupt factor occurs in any of the IOCs connected to the expansion bus,
The corresponding bit of a register (interrupt factor register) indicating that an interrupt factor has occurred in the IOC is turned on. This interrupt request is notified to the bus adapter 430 via the interrupt line of the extension bus. Then, the bus adapter 430 determines that the bus adapter 430 itself has caused an interrupt factor, and
Request an interrupt (S41). Next, the CPU 10
Assigns 0 to a variable n in order to sequentially check the state of the interrupt factor register of the IOC connected to the extension bus 15 (S42).

Next, the CPU 10 controls the n-th
The status of the interrupt factor register of the IOC connected to the slot is read (S43), and it is determined whether the bit of the interrupt factor register is ON (S4).
4). If it is determined that the bit of the interrupt factor register is not ON, 1 is added to the variable n (S45), and the process returns to step S43. If it is determined that the corresponding bit of the interrupt factor register is ON, it is determined that the IOC has issued an interrupt request, and the interrupt processing is performed by saving the register of the CPU 10 and a program status word (PSW) ( S46).

In the example shown in FIG. 5, it is assumed that IOC-d'463 has issued an interrupt request. Since the IOC-d '463 is connected to the third slot 15d, the IOC-a'
460, IOC-b '461, IOC-c' 462, read out the interrupt factor register and determine that the bit is not ON, and then read the IOC-d '463 interrupt factor register and determine that the bit is ON. It is determined that this is issuing an interrupt request. Only after these processes are performed can the process proceed to the interrupt process. FIG. 9 shows a time chart from the occurrence of an interrupt factor to the shift to interrupt processing in this example.

As described above, if software processing is used to determine the input / output control device on which an interrupt factor has occurred on the expansion bus, it may take a very long time to proceed to interrupt processing. . However, there is a problem in that changing the configuration of the bus adapter as an expansion device, which is basic hardware, is disadvantageous in terms of cost.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems of the prior art, and has a control on an expansion bus without changing the configuration of an expansion device which is basic hardware. An object of the present invention is to provide an interrupt processing method and a control device that can promptly respond to an interrupt request from a device.

[0019]

In order to achieve the above object, the interrupt processing method of the present invention is as follows.

When an interrupt occurs, processing means for processing the interrupt, a basic bus connected to the processing means, expansion means for expanding the basic bus,
An extension bus connected to the extension means; and a plurality of control means connected to the extension bus and generating an interrupt request to the processing means via the extension bus, the extension means and the basic bus. The basic bus has a basic bus interrupt line for transmitting a signal indicating that an interrupt has occurred, and the basic bus transmits a signal indicating that an interrupt has occurred. A basic bus interrupt line, wherein the expansion bus has a plurality of expansion bus interrupt lines corresponding to each of the plurality of control means for transmitting a signal indicating that an interrupt has occurred to the control means. At least one of the plurality of control means has a storage means for storing signal states of the plurality of expansion bus interrupt lines. When the processing unit is notified that an interrupt request has been generated from any one of the plurality of control units, the processing unit refers to the storage unit, and based on the state of the storage unit referred to here, An interrupt processing method in which an interrupt request is specified after identifying which control unit has generated the interrupt request.

Here, when an interrupt request is generated in any one of the control means, the occurrence of the interrupt request is transmitted to the expansion means via one of the expansion bus interrupt lines, and Transmits an interrupt to the processing unit via the basic bus interrupt line, assuming that an interrupt has occurred from the expansion unit.

The interrupt processing system of the present invention is configured as described above, so that when an interrupt occurs in one of the plurality of control units connected to the expansion bus, the processing unit changes the state of the temporary storage unit. Only by reading, it is possible to specify which control means has caused the interruption.

Therefore, regardless of where the control means that generated the interrupt is connected to the expansion bus, it is possible to respond promptly to the interrupt from the control means. In addition, there is no need to change the configuration of the extension means at all.

It is possible to adopt a configuration in which only one of the plurality of control means has the storage means, or a configuration in which all of the plurality of control means have the storage means. In short, there may be one or more control means having the storage means.

Further, the control device of the present invention is connected to a bus having a plurality of interrupt lines, and is provided with storage means for storing the states of the signals of the plurality of interrupt lines in the interrupt processing device via the bus. It is.

Here, the temporary storage means includes a first register consisting of a plurality of bits in which only one bit corresponding to an interrupt line is flagged, and a signal indicating an interrupt request to one of the interrupt lines of the bus. A plurality of logic circuits for performing a logical operation on an output signal of each bit of the first register and a signal indicating an interrupt request to output only the output signal to each interrupt line of the bus, and It can be configured to have a second register that inputs and holds a signal on each interrupt line.

If this control device is applied to a system having an expansion bus which has been used in the past, the interrupt generated by any control device connected to the expansion bus can be performed without any change in the configuration of other devices. I can respond quickly.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a computer system in which a bus is extended according to an embodiment of the present invention. In this example, both the basic bus and the expansion bus are PCI buses.

In this system, the CPU 10 is connected to the basic bus 12 via the host bridge 11. The basic bus 12 has four slots 12a to 12d, and interrupt lines intA to intD are assigned to input / output control devices connected to the 0th slot 12a to the third slot 12d. 0th slot 1
A bus adapter 130 is connected to 2a as a bus expansion device. The expansion bus 15 is connected to the bus adapter 130 to extend the bus. 15a for expansion bus 15
-15d, and the 0th slot 15a
To the third input / output control device connected to the third slot 15d. Although illustrated separately in the figure, the interrupt lines intA to intD and inta to intd constitute a part of the buses 12 and 15, respectively.

The first slot 12b of the basic bus 12, the second slot 12b
The input / output control devices IOC-B131, IOC-C132, IO
C-D133 is connected. The 0th slot 15a, the first slot 15b, the second slot 15c, and the third slot 15d of the expansion bus 15 are respectively provided with input / output control devices IOC-a160, IOC-b161, and IOC-c.
162 and IOC-d 163 are connected. Each of these input / output control devices is connected to an input / output device (not shown).

Each interrupt line inta of the extension bus 15
~ Intd are all IOC-a160 to IOC-d
163. And IOC-a160-I
The OC-d 163 is capable of inputting / outputting any of the interrupt lines.

Next, the input / output to / from the interrupt line of each input / output control device will be described in detail. FIG. 2 is a block diagram illustrating an interrupt notification unit of the input / output control device according to the embodiment of the present invention.

The interrupt notification unit includes an INTE register 20, an AND gate 21, and an open collector element 2.
2, an interrupt factor register 23, and an amplifier 24. Here, the INTE register 20 and the interrupt factor register 23 are connected to the extension bus 15.

The INTE register 20 is set so that the initial setting routine of the CPU 10 at the time of starting up the system allows the initialization routine to correspond to each of the interrupt lines inta to intd.
Turn on any one bit of EA to IED. In the present embodiment, the IOC-a
IEA at 160, IEB at IOC-b161,
The IEC is turned on in the IOC-c 162, and the IED is turned on in the IOC-d 163.

The AND gate 21 is connected to the IOC-a 160
When an interrupt factor occurs in the IOC-d 163, the output of each bit of the INTE register 20 is set so that a signal indicating that an interrupt factor has occurred in only one of the corresponding interrupt lines inta to intd can be output. And the logical product of

The output signal of the AND gate 21 is written into each bit of IA, IB, IC and ID of the interrupt factor register 23, and indicates that an interrupt factor has occurred in the input / output control device. In addition, IA, I
The output signal of each bit of B, IC and ID is output to interrupt lines inta to intd. The open collector element 22 cuts off the voltage in order to avoid turning on the IA, IB, IC and ID bits of the interrupt factor register of another input / output control device.

Further, the interrupt lines inta to intd
Are amplified by the amplifier 24, and these are amplified by the OA, OB, OC, and O of the interrupt factor register 23, respectively.
Write to each bit of D. Then, the CPU 10 reads the contents of the interrupt factor register 23 via the extension bus 15, the bus adapter 130, the basic bus 12, and the host bridge 11. The CPU 10 can also determine which other input / output control device has caused the interrupt factor based on the state of the interrupt factor register 23 read here.

The operation in the interrupt processing routine according to one embodiment of the present invention will be described below. FIG. 3 is a flowchart showing the operation of the embodiment of the present invention.

First, the IOC-a1 connected to the extension bus
When an interrupt factor occurs in any of 60 to IOC-d 163, one of the IA to ID bits of the interrupt factor register 23 is turned on. This is the interrupt line i
bus adapter 13 via any of nta to intd
0 is notified. Bus adapter 130 is bus adapter 1
30 itself issues an interrupt factor to the CPU 10 via the host bridge 11 and requests an interrupt (S
11). Next, the IOC-a 160 to I
The state of any one of the interrupt factor registers 23 of the OC-d 163 is read (S12). Next, the read interrupt factor register 23 determines whether or not the interrupt factor register 23 belongs to the input / output control device that generated the interrupt factor by checking the state of the IA to ID bits (S13).

If it is determined that the interrupt is caused by the IOC that caused the interrupt, the interrupt processing is continued by saving the register of the CPU 10 and the PSW as it is (S15). If it is determined that the interrupt is not of the IOC that caused the interrupt, the read interrupt factor register 2
The IOC that caused the interrupt is accessed based on the status of the OA to OD bits 3 (S14). Then, C
The interrupt processing is performed by saving the registers and the PSW of the PU 10 (S15).

A specific example will be described. IOC-d
163 causes an interrupt, and the CPU 10 sets the IOC-a
It is assumed that the contents of the interrupt factor register 23 are read.

When the system is started, the IOC-a16
IA to ID and OA to OD bits of all interrupt factor registers 23 of 0 to IOC-d 163 are all OFF.
It is in the state of. In addition, INT of IOC-d163
The IED bit of the E register 20 is turned on. I
When an interrupt factor occurs in the OC-d 163, the ID bit of the interrupt factor register 23 of the IOC-d 163 is turned on by the output of the AND gate 21. Then, the interrupt line intd is turned ON, and the IO
The OD bits of the interrupt factor registers 23 of the C-a 160 to IOC-d 163 are turned on.

When the interrupt line intd is turned on, the bus adapter 130 is notified that an interrupt factor has occurred. The bus adapter 130 is a bus adapter 1
Assuming that an interrupt factor has occurred in itself, an interrupt request is issued to the CPU 10 via the host bridge 11.
The CPU 10 that has been requested to interrupt the host bridge 1
1. Read the contents of the interrupt factor register 23 of the IOC-a 160 via the basic bus 12, the bus adapter 130 and the expansion bus 15. The IA bit of the interrupt factor register 23 read here is OFF, and the OD bit is O.
Since it is N, the CPU 10 knows that the IOC-d 163 caused the interrupt factor.

Then, the CPU 10 accesses the IOC-d 163 and shifts to interrupt processing. FIG. 4 shows a time chart of the operation during this time.

As described above, in the computer system according to the present embodiment, even when an interrupt factor occurs in the input / output control device on the expansion bus, it is possible to promptly proceed to the interrupt processing. In addition, since there is no need to change the configuration of the bus adapter, which is the basic hardware, the disadvantage of cost is relatively small.

In the computer system of the above embodiment, all the input / output control devices on the expansion bus have the above-described interrupt notification unit. I just need to get it. When the CPU receives an interrupt request from the bus adapter, the CPU always reads the interrupt factor register of the input / output control device having the interrupt notification unit. This is because even one input / output control device having an interrupt processing unit can determine which input / output control device has caused the interrupt factor.

In the above-described embodiment, an example has been described in which the bus for connecting the input / output control device external to the computer is extended. However, in the case where information is transferred between computers or when the bus-connected LAN is used. The present invention can be applied to the case of extension.

[0049]

As described above, according to the interrupt control method of the present invention, when an interrupt is received from the control means connected to the expansion bus, it is possible to promptly proceed to the interrupt processing. In addition, since there is no need to change the configuration of the expansion means, which is the basic hardware, there is little disadvantage in terms of cost.

Further, by using the control device of the present invention, it is possible to promptly respond to an interrupt from the control means connected to the expansion bus while maintaining upward compatibility with the conventional system.

[Brief description of the drawings]

FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention.

FIG. 2 is a block diagram of an interrupt notification unit of the input / output control device according to the embodiment of the present invention.

FIG. 3 is a flowchart showing an operation of one embodiment of the present invention.

FIG. 4 is a time chart of an example of the operation of the embodiment of the present invention.

FIG. 5 is a block diagram of a conventional computer system.

FIG. 6 is a block diagram of a conventional bus expansion device.

FIG. 7 is a flowchart showing the operation of a conventional bus expansion device.

FIG. 8 is a flowchart showing the operation of the conventional example.

FIG. 9 is a time chart of an example of the operation of the conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 CPU 11 Host bridge 12 Basic bus 15 Expansion bus 130 Bus adapter 131-133, 160-163 I / O control device (I
OC) intA to intD, inta to intd Interrupt line 20 INTE register 21 AND gate 22 Open collector element 23 Interrupt factor register

Claims (6)

[Claims] 1. A processing means for processing an interrupt when an interrupt occurs, a basic bus connected to the processing means, an expansion means for expanding the basic bus, and a connection to the expansion means. And a plurality of control means connected to the expansion bus and generating an interrupt request to the processing means via the expansion bus, the expansion means and the basic bus. Wherein the basic bus has a basic bus interrupt line for transmitting a signal indicating that an interrupt has occurred; and the extension bus transmits the signal indicating that an interrupt has occurred to the control means. And a plurality of extension bus interrupt lines corresponding to each of the plurality of control means. At least one of the plurality of control means includes a plurality of extension bus interrupt lines. And a storage unit for storing a signal state of an interrupt line, wherein the processing unit refers to the storage unit when an interrupt request is transmitted from any one of the plurality of control units. An interrupt processing method in which an interrupt request is specified from which control means has generated an interrupt request based on the state of the storage means referred to here. 2. When an interrupt request is generated in any one of the control means, the occurrence of the interrupt request is transmitted to the expansion means via one of the expansion bus interrupt lines, and the expansion means 2. The interrupt processing method according to claim 1, wherein the interrupt is transmitted to the processing unit via the basic bus interrupt line, assuming that an interrupt has occurred from the extension unit. 3. The method according to claim 1, wherein only one of said plurality of control means has said storage means.
Interrupt processing method described in 1. 4. The interrupt processing method according to claim 1, wherein all of said plurality of control means have said storage means. 5. A control device connected to a bus having a plurality of interrupt lines to generate an interrupt request to an interrupt processing device via the bus, the storage unit storing a state of a signal of the plurality of interrupt lines. Control device equipped with 6. A storage device comprising: a first register comprising a plurality of bits in which only one bit corresponding to an interrupt line to which a control device is connected is flagged; A plurality of logic circuits for performing a logical operation on an output signal of each bit of the first register and a signal indicating an interrupt request to output the signal to only one of the lines and outputting the signal to each interrupt line of the bus; 6. The control device according to claim 5, further comprising a second register for inputting and holding a signal on each interrupt line of the bus.