JPH1021697A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which the cell of a spare column can be tested before a fuse corresponding to a defective column is laser-cut. SOLUTION: A line 2 is connected with NMOSFETs 5, 6 through first and second fuses 3, 4, respectively. The NMOSFETs 5, 6 are connected, respectively, with the first and second address signal terminals 7, 8. The NMOSFETs 5 is connected in series with a PMOSFET 9 which is interrupted by feeding a power supply voltage to the gate thereof. Under that state, a signal is fed only to the first signal terminal 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a redundancy circuit of a semiconductor memory device.

[0002]

2. Description of the Related Art As the capacity of a semiconductor memory increases, it becomes rapidly difficult to manufacture a memory array containing no defective bit. In particular, in the case of a memory developed using a new manufacturing technique, the defect level at the time of initial trial production is high, and the yield is extremely low.

[0003] As a measure to solve such problems, EC
The use of a C (Error Checking and Correction) circuit has been studied, but a satisfactory result in terms of speed and the like has not been obtained. At present, in practice, a redundant circuit technique for adding a few redundant rows and columns and replacing defective cells, rows and columns is used.

FIG. 5 shows a circuit of a memory array having two redundant rows (spare rows). If there is a defective bit in the normal array, the spare data is programmed so as to perform a selecting operation for an address signal corresponding to the row. Thus, when an address including a defective bit is input, a spare decoder is selected, and at the same time, a selection inhibition signal is output to a normal row decoder. Therefore, a spare row is selected instead of a regular row.

FIG. 4 is a circuit diagram of the spare decoder of FIG. Normally, the above programming is performed by laser cutting the fuses 103 and 104 corresponding to the defective address (Fuse Blow).
It is completed by doing. By doing so, the spare decoder (redundant circuit) is activated for the first time.

More specifically, when a defective address is input to the address input terminals 107 and 108, the corresponding fuses 103 and 104 are all blown.
Even if the SFETs 105 and 106 are conducting, the node
Is held at the “H” level. Since the node is “H”, a spare column is selected and a defective address is relieved.

[0007]

However, since the conventional column spare decoder is not activated unless the fuse is physically cut by a laser, the fuse corresponding to the defective address is cut, and the die sort is performed again.
Spare cells need to be tested.

In view of the above problems, it is an object of the present invention to provide a semiconductor memory device capable of testing cells in a spare column before laser cutting a fuse corresponding to a defective address.

[0009]

In order to solve the above problems, a semiconductor memory device according to the present invention comprises a power supply voltage terminal,
A selection terminal and a spare selection terminal, a line electrically connecting the power supply voltage terminal and the selection terminal and the spare selection terminal, first and second fuses each having one end connected to the line, The first and second switching elements, each having one main electrode terminal connected to the other end of the first and second fuses, respectively, and the control electrode terminals of the first and second switching elements are respectively electrically connected. A first and a second address signal terminals connected to each other; and a third switching element connected to the other main electrode terminal of the first switching element.

In the present invention, the spare cell is selected without cutting the laser by keeping the third switching element in a cut-off state, and inputting a signal only to the first address signal terminal in this state. Is done. Therefore, a spare cell can be tested without performing laser cutting.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to a first embodiment of the present invention will be described with reference to the drawings. In this embodiment, a column spare decoder for a memory cell array having 128 Kbit columns will be described. FIG.
In the case of a DRAM driven by 5 V, 5 V of 3.3 V
In the case of a V-driven DRAM, a 3.3 V power supply voltage terminal 1 is a column selection terminal (not shown, connected to a column selection driver via a delay circuit or an OR circuit).
The line 2 is connected to the ode. The line 2 branches between the power supply voltage terminal 1 and the node, and the SCS
It is extended to Ln (Spare Colemn Select Line) 1 terminal.

A first fuse 3 is connected to the line 2 in accordance with eight address data, and a second fuse 4 is connected in accordance with the eight address inversion data. Each of the first fuses 3 is connected to the drain of an NMOSFET 5 that is a first switching element, and each of the second fuses 4 is connected to the drain of an NMOSFET 6 that is a second switching element.

A first address signal terminal 7 corresponding to eight address data is connected to the gate of the NMOSFET 5, and a second address signal terminal which is an inverted component of the first address signal terminal 7 is connected to the gate of the NMOSFET 6. 8
Is connected.

The source of the NMOSFET 5 is connected to the drain of a PMOSFET 9 as a third switching element. The source of the NMOSFET 6 is grounded (Vs
s). The gate of the PMOSFET 9 is shared and connected to Pad to which the power supply voltage is applied.

Next, the operation of the semiconductor memory device will be described. For example, if the memory cell in the 16th column is defective, the address of this column (000100
00) is input, the node goes to “H” level, a spare column must be selected, and a spare decoder (redundant circuit) needs to be activated.

At this time, the address of the spare column is set to (1
1111111) (pseudo address). Then, the power supply voltage is applied to the gate of each PMOSFET 9 to shut off the PMOSFET 9. In this case,
Each terminal A3C, A2C of the first address signal terminal 7,
.., Even if a signal is input to A7C (that is, even if the address (11111111) is selected), the voltage between the gate and the source does not exceed the threshold, and therefore
Since the MOSFET 5 does not conduct, the node goes high and the spare decoder is activated.
Therefore, the spare cell can be tested without cutting the first fuse 3 corresponding to (11111111) with a laser.

After the test, the pad is grounded, and among the first address input terminal 7 and the second address input terminal 8 corresponding to the address (00010000) of the defective memory cell, BA3C, BA2C, BA4C, A9C, BA5
The first fuse 3 and the second fuse 4 corresponding to the respective terminals of C, BA8C, BA6C and BA7C are laser cut. When the defective address is input to the column spare decoder, the corresponding fuse has been blown, so that n
mode is held at the “H” level. Therefore, a spare column is selected, and a spare decoder (redundant circuit) starts up.

As described above, in this embodiment, the source of the NMOSFET 5 as the first switching element is connected to the PMOS.
An FET 9 is connected, and a power supply voltage is input to the gate of the PMOSFET 9 so that a spare cell corresponding to the address of the spare column and without cutting the first fuse 3 corresponding to the first address input terminal 7 can be provided. Can be tested. In this embodiment, the PMO
Although the SFET 9 is used, an NMOSFET may be used. In that case, the gate needs to be grounded.

Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 2, the upper half is exactly the same as the spare column decoder of the first embodiment, and therefore the description is omitted. A line 12 is connected to the power supply voltage terminal 1 in addition to the line 2. This line 12 is connected to the power supply voltage terminal 1 and the node 2
And SCSLn (Spare Colemn Select Li
ne) Extension to 2 terminals.

A third fuse 13 is connected to the line 12 corresponding to eight address data, and a fourth fuse 14 is connected to the eight address inversion data.
Is connected. The drain of an NMOSFET 15 is connected to each of the third fuses 13, and the drain of an NMOSFET 16 is connected to each of the fourth fuses 14.

A third address signal terminal 17 corresponding to eight address data is connected to the gate of the NMOSFET 5, and a fourth address signal terminal which is an inverted component of the third address signal terminal 17 is connected to the gate of the NMOSFET 6. 18 are connected.

The source of the NMOSFET 16 is a PMOS
The drain of the FET 19 is connected. Also, NMOSF
The source of ET15 is grounded (connected to Vss). PM
The gate of the OSFET 19 is shared and connected to Pad to which the power supply voltage is applied.

Next, the operation of the semiconductor memory device will be described. For example, if the memory cells in the 16th and 72nd columns are defective, the addresses (00
When (010000) and (01001100) are input, the node becomes “H” level, a spare column must be selected, and a spare decoder (redundant circuit) needs to be activated.

At this time, the two addresses of the spare column are set to (11111111) and (000000000) (pseudo addresses). And each PMOSFET 9,
By applying a power supply voltage to the gate of the PMOS 19, the PMOS
The FETs 9 and 19 are cut off. Thus, even if a signal is input to each of the terminals A3C, A2C,..., A7C of the first address signal terminal 7 (that is, the address (1111
Even if 1111) is selected), the voltage between the gate and the source does not exceed the threshold value, so that the NMOSFET 5
Does not conduct, node1 attains the "H" level, and the spare decoder is activated. Therefore (11
The spare cell at the address (11111111) can be tested without cutting the first fuse 3 corresponding to (111111) with a laser.

Similarly, when the PMOSFET 19 is shut off, each terminal BA3 of the fourth address signal terminal 18 is turned off.
Even if a signal is input to C, BA2C,..., BA7C (that is, even if the address (00000000) is selected), the voltage between the gate and the source does not exceed the threshold value, so that the NMOSFET 16 becomes conductive. Therefore, node2 becomes "H" level, and the spare decoder is activated. Therefore, the spare cell corresponding to the address (00000000) can be tested without cutting the fourth fuse 14 corresponding to (00000000) by laser.

After the test, Pad is grounded, and among the first address input terminal 7 and the second address input terminal 8 corresponding to the address (00001000) of the defective memory cell, BA3C, BA2C, BA4C, BA9C, A5
The first fuse 3 and the second fuse 4 corresponding to the respective terminals of C, BA8C, BA6C and BA7C are laser cut. Similarly, of the third address input terminal 17 and the fourth address input terminal 18 corresponding to the address (001001100) of another defective memory cell, BA3
C, A2C, BA4C, BA9C, A5C, A8C, B
The third fuse 13 and the fourth fuse 14 corresponding to the respective terminals of A6C and BA7C are laser cut. When the defective address is input to the column spare decoder, node1 or node2 is held at "H" level because the corresponding fuse is blown. Therefore, a spare column is selected, and a spare decoder (redundant circuit) starts up.

As described above, in the present embodiment, the NMOSFET 5 and the NMOSFET
PMOSFETs 9 and 19 are connected to the sources of the PMOSFETs 16, respectively. The power supply voltage is input to the gates of the PMOSFETs 9 and 19 to correspond to the address of the spare column, and to input the first address input terminal 7 and the fourth address. The spare cell can be tested without cutting the first fuse 4 and the fourth fuse 14 corresponding to the input terminal 18. In this embodiment, the PMOSFE
Although T9 and T19 are used, an NMOSFET may be used. In that case, the gate needs to be grounded.

Next, a semiconductor memory device according to a third embodiment of the present invention will be described with reference to FIG. Power supply voltage terminal 1
Is connected to a node which is a column selection terminal (not shown, connected to a column selection driver via a delay circuit or an OR circuit). This line 2 branches between the power supply voltage terminal 1 and the node,
It is extended to one SLn (Spare Colemn Select Line) terminal.

A first fuse 3 is connected to the line 2 corresponding to eight address data, and a second fuse 4 is connected to the eight address inversion data. Each of the first fuses 3 is connected to the drain of an NMOSFET 5 that is a first switching element, and each of the second fuses 4 is connected to the drain of an NMOSFET 6 that is a second switching element.

A first address signal terminal 7 corresponding to eight address data is connected to the gate of the NMOSFET 5, and a second address signal terminal which is an inverted component of the first address signal terminal 7 is connected to the gate of the NMOSFET 6. 8
Is connected. Source of NMOSFET 5 and NMO
The source of SFET 6 is grounded (connected to Vss).

A PMOSFET is provided between the node of the first fuse 3 and the second fuse 4 connected to the line 2 and the node.
29 is inserted. Pad is connected to the gate of the PMOSFET 29 via a fuse 30.

Next, the operation of the semiconductor memory device will be described. For example, if the memory cell in the 16th column is defective, the address of this column (000100
00) is input, the node goes to “H” level, a spare column must be selected, and a spare decoder (redundant circuit) needs to be activated.

Before activating the spare decoder, a power supply voltage is first applied to Pad. Then PMOSFET2
9 shuts off, and the node holds the high potential of Pad. Therefore, as in the first embodiment, the node becomes "H" level, and the spare decoder is activated. Therefore, the spare cell can be tested without cutting the first fuse 3 and the second fuse 4 with a laser.

After the test, Pad is set to the ground potential, and the fuse 30 is cut. Then, of the first address input terminal 7 and the second address input terminal 8 corresponding to the address (00010000) of the defective memory cell, BA3C, B3
A2C, BA4C, A9C, BA5C, BA8C, BA
The first fuse 3 and the second fuse 4 corresponding to the respective terminals of 6C and BA7C are laser cut. When the defective address is input to the column spare decoder, the node is held at "H" level because the corresponding fuse is blown. Therefore, a spare column is selected and a spare decoder (redundant circuit) is activated. When a normal address is input, a current conduction path is formed between the power supply voltage terminal 1 and Pad and the ground, so that the node becomes "L" level and the spare decoder is not activated.

As described above, in this embodiment, the effects of the first and second embodiments can be satisfied, and the number of PMOSFETs added to the conventional spare decoder can be greatly reduced. This is advantageous for high integration. Although the description so far has been made on the column spare decoder, it is needless to say that this can be applied to the row spare decoder.

[0036]

According to the present invention, a spare cell can be tested without blowing a fuse.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 3 is a circuit diagram of a semiconductor memory device according to a third embodiment of the present invention;

FIG. 4 is a circuit diagram of a conventional semiconductor memory device;

FIG. 5 is a circuit configuration diagram of a conventional memory cell array circuit with spare columns.

[Explanation of symbols]

1, 101 power supply voltage terminal 2, 12, 102 line 3 first fuse 4 second fuse 5, 6, 15, 16, 105, 106 NMOSFE
T 7 First address signal terminal 8 Second address signal terminal 9, 19, 29 PMOSFET 13 Third fuse 14 Fourth fuse 17 Third address signal terminal 18 Fourth address signal terminal 30, 103, 104 Fuse 107, 108 Address signal terminal

Claims (10)

[Claims] A power supply voltage terminal; a selection terminal and a spare selection terminal; a line electrically connecting the power supply voltage terminal with the selection terminal and the spare selection terminal; and one end connected to the line. First and second fuses; first and second switching elements each having one main electrode terminal connected to the other end of the first and second fuses; First and second address signal terminals electrically connected to the control electrode terminals of the switching element, and a third switching element connected to the other main electrode terminal of the first switching element. A semiconductor memory device. 2. The method according to claim 1, wherein the third switching element is a PMOS.
2. The semiconductor memory device according to claim 1, wherein the device is an FET, and a power supply voltage is applied to a gate of the FET. 3. The device according to claim 2, wherein the third switching element is an NMOS.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an FET, and its gate is at a ground potential. 4. The first address signal terminal is connected to the first address signal terminal.
2. The semiconductor memory device according to claim 1, wherein the address signal terminal is an inverted input terminal. 5. The semiconductor memory device according to claim 1, wherein said selection terminal is connected to a spare decoder. 6. A power supply voltage terminal, first and second selection terminals, first and second spare selection terminals, the power supply voltage terminal, the first selection terminal, and the first spare selection terminal. A second line electrically connecting the power supply voltage terminal with the second selection terminal and the second spare selection terminal; and a first line electrically connecting the power supply voltage terminal with the second selection terminal and the second spare selection terminal. First and second fuses each having an end connected thereto; third and fourth fuses each having one end connected to the second line; and the other of the first and second fuses. First and second switching elements each having one end connected to one main electrode terminal; and third third elements each having one main electrode terminal connected to the other end of the third and fourth fuses. A fourth switching element; and a control electrode terminal of the first and second switching elements. First and second address signal terminals electrically connected to each other; third and fourth address signal terminals electrically connected to control electrode terminals of the third and fourth switching elements, respectively; A fifth switching element connected to the other main electrode terminal of the first switching element; and a sixth switching element connected to the other main electrode terminal of the fourth switching element. A semiconductor memory device characterized by the following. 7. The fifth and sixth switching elements are P
7. The semiconductor memory device according to claim 6, wherein the power supply voltage is applied to a gate of the MOSFET. 8. The fifth and sixth switching elements are NM.
7. The semiconductor memory device according to claim 6, wherein the device is an OSFET and a gate thereof is at a ground potential. 9. The first address signal terminal is connected to the first address signal terminal.
7. The semiconductor memory device according to claim 6, wherein said fourth address signal terminal is an inverted input terminal of said third address signal terminal. 10. The semiconductor memory device according to claim 6, wherein said first and second selection terminals are connected to a spare decoder.