JPH10199267A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a non-volatile semiconductor memory device which can control a distribution range of a threshold voltage within a narrow range and can improve data retention resistance and read disturbing resistance of memory cell. SOLUTION: A pulse controller 20 outputs a control signal Sp for selecting a pulse voltage Vp to a multiplexer 10 depending the predetermined threshold voltage Vth, moreover produces a control signal ϕp for controlling a program pulse width depending on the level of the selected pulse voltage Vp and its inverted signal/ϕp and then outputs these signals to a word line switch 40. The word line switch 40 controls the program pulse width to be impressed to the selected word line with a row decoder 30 depending on these control signals. Therefore, distribution width of the threshold value Vth of the memory cell after the writing operation can be controlled within the narrow range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art A non-volatile semiconductor memory device injects charges (electrons) into a charge storage layer which is electrically insulated from the surroundings and discharges charges from the charge storage layer to form a storage element (hereinafter referred to as a storage element). , A memory cell) and stores data according to the threshold voltage.
The charge storage layer (hereinafter referred to as a floating gate) is electrically insulated from its surroundings, and the injected charge is held almost permanently, so that the written data is stored until the next writing. At the time of reading, the potential of the bit line connected to the selected memory cell is set according to the threshold voltage of the selected memory cell. By detecting this potential, the data stored in the selected memory cell is read.

FIG. 6 shows a structure of a memory cell of a nonvolatile semiconductor memory device and a bias state at the time of writing and erasing. As shown, the memory cell of the nonvolatile semiconductor memory device includes a control gate 1, a floating gate 2, a source diffusion layer 3, a drain diffusion layer 4, and a substrate 5. FIG. 6 shows a memory cell formed on the p substrate, and the source diffusion layer 3 and the drain diffusion layer 4 are each formed of an n ⁺ region. An interlayer insulating film is formed between the control gate 1 and the floating gate 2, and a gate insulating film is formed between the floating gate 2 and a channel region therebelow. These are omitted in FIG. ing.

As shown in FIG. 6A, at the time of writing, a high positive voltage Vg, for example, 10 V, is applied to the control gate 1, and a voltage Vd, for example, 5 V, is applied to the drain diffusion layer 4. I have. Source diffusion layer 3 and substrate 5 are biased to ground potential GND. In such a bias state, electrons flow from the source diffusion layer 3 toward the drain diffusion layer 4 in the channel region, and a part of the electrons accelerated in the pinch-off region near the drain diffusion layer becomes hot electrons (hot electrons). , Which are captured by the floating gate 2. Floating gate 2 by writing
Are injected into the memory cell, and the threshold voltage of the memory cell increases. The threshold voltage is controlled according to the voltage value of the write voltage Vg applied to the control gate 1 at the time of writing and the application time of the voltage Vg.

The erasing of the memory cell is performed in a bias state shown in FIG. A negative voltage, for example, -1
A voltage of 0 V is applied, the drain diffusion layer 4 is brought into a floating state, a voltage of, for example, 5 V is applied to the source diffusion layer 3, and the substrate 5 is biased to the ground potential GND. In such a bias state, electrons are extracted from the floating gate 2 to the source diffusion layer 3 by Fowler-Nordheim tunneling (FN tunneling). Also,
There is also an ultraviolet erasing method in which electrons are emitted from the floating gate 2 by ultraviolet irradiation.

As described above, at the time of writing, the control gate 1
The threshold voltage _Vth of the memory cell after writing is set to a plurality of different levels by changing the voltage value and the application time of the write voltage Vg applied to the memory cell, and different data are stored according to the respective levels. A value memory can be realized. FIG. 7 shows the distribution of the threshold voltage of a binary memory cell that stores 2-bit data in one memory cell by setting the threshold voltage _Vth to four levels, and the storage data according to the distribution. ing.

As shown in the drawing, the threshold voltage _Vth of the memory cell is changed to, for example, 1 to 3 by changing the write condition.
V, 3.7 to 4 V, 4.7 to 5 V, and 5.7 to 6 V, and the threshold voltages of these four stages are, for example, data "00" and "0"
1, "10" and "11." Of these, the lowest threshold voltage level corresponding to data "11" is set to the erased state, and the other "00", "01" and "10" are set.
It is assumed that the level corresponding to the data is obtained by writing.

[0008]

By the way, in the general multi-valued memory described above, a plurality of threshold voltages V _th are applied by changing the voltage value of the write voltage Vg applied to the control gate 1 of the memory cell at the time of writing. Get the level. During the actual write, a write pulse is applied to the word line control gate 1 of the memory cell is connected to control the voltage value of the write pulse V _p, of the memory cell threshold voltage V
Set _th to a desired level. For example, a low pulse voltage to a low threshold voltage V _th, giving a high pulse voltage to high threshold voltage V _th. This avoids an increase in the writing time to obtain a high threshold voltage _Vth . However, when the pulse voltage is set to be high, there is a problem that the fluctuation of the threshold voltage _Vth increases for each pulse, and the distribution width of the threshold voltage _Vth after writing becomes wide.

For example, two memory cells are stored in one memory cell.
In the case of a binary memory cell for storing
A threshold voltage level is required. Four threshold voltages
2 bits of data “00”, “01”, “1” corresponding to
Of "0" and "11", "11" is in the erased state,
The other three are obtained by writing. Figure 8 shows three thresholds
Write pulse (program
Pulse), threshold voltage V_thChange curve and forecast
Threshold voltage V_thIs shown. Here, the threshold voltage
Pressure V_th0Corresponds to the data "11", and the threshold voltage V
_th1Corresponds to data "10" and has a threshold voltage V_th2Is
Threshold voltage V corresponding to data "01" _th3Is data
Assume that it corresponds to “00”. Threshold voltage V_th1,
V_th2And V_th3Are obtained by writing.
As shown, V_th2Distribution is V_th1Wider than the distribution of
And V_th3Distribution is V_th2Is wider than the distribution.
That is, the threshold voltage V_thIs higher, the distribution range is wider
Tend.

In the case of a multilevel memory, the highest threshold voltage V _th3 is set as low as possible, and the interval between the highest threshold voltage V _th3 and the lowest threshold voltage V _th0 is made as narrow as possible. Therefore, it is necessary to control the distribution range of each threshold voltage _Vth level to be narrow.

Further, the data stored in the memory cell can be rewritten by writing and erasing. In a normal floating gate type nonvolatile semiconductor memory device, the number of times of rewriting is up to 100 times.
Although it can be performed up to 10,000 times, the characteristics of the tunnel oxide film (gate insulating film) are deteriorated according to the number of times of rewriting. The data retention resistance and read disturb resistance also deteriorate in accordance with the number of rewrites.

The present invention has been made in view of the above circumstances, and has as its object to control the distribution range of the threshold voltage after writing to be narrow, and to improve the data retention resistance and read disturb resistance of a memory cell. An object of the present invention is to provide a nonvolatile semiconductor memory device.

[0013]

In order to achieve the above object, the present invention changes the amount of charge stored in a charge storage layer in accordance with a voltage value of a write signal and an application time, thereby changing a threshold voltage to a plurality of levels. A nonvolatile semiconductor memory device having a settable storage element, wherein the application time of the write signal set to a plurality of voltage values according to a desired threshold voltage level is reduced as the voltage value increases. Writing control means for causing

Further, in the present invention, the write control means applies the write signal to a control gate of a storage element in which a source electrode and a drain electrode are respectively biased to a predetermined potential during writing for a set time, and A voltage setting unit that sets a voltage value of the write signal according to a threshold voltage level

Further, according to the present invention, the threshold voltage is controlled by changing the amount of charge stored in the charge storage layer by transferring charges to and from the charge storage layer that is electrically insulated from the surroundings. A nonvolatile semiconductor memory device including a storage element that stores information corresponding to a voltage, and a storage characteristic of storage information of the storage element deteriorates with the transfer of the charge,
The writing of the storage information by the transfer of the electric charge includes a writing control means for limiting the writing to a predetermined number of times, for example, once.

According to the present invention, in a multilevel memory, a pulse voltage of a different level is selected according to a desired threshold voltage, the application time of the pulse is controlled according to the pulse voltage level, and the pulse voltage is reduced. The higher the value, the shorter the application time is set. As a result, the distribution width of the high-level threshold voltage can be controlled to be narrow, and the threshold voltage distribution range of the entire multi-level memory can be controlled to be narrow.

Further, according to the present invention, by limiting the number of rewrites of the multi-valued memory to a predetermined number of times, for example, one, the data retention resistance and the read disturb resistance of the multi-valued memory can be improved, and the memory chip can be improved. An inexpensive memory chip with a small size can be made.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of the nonvolatile semiconductor memory device according to the present invention. As shown in the figure, the present embodiment includes a multiplexer 10, a pulse controller 20, a row decoder 30, a word line switch 40, and a memory cell array 50. Multiplexer 10,
A write control circuit is constituted by the pulse controller 20, the row decoder 30, and the word line switch 40,
The write operation of the memory cell array 50 is controlled.

The multiplexer 10 is controlled by a pulse controller 20 to select one of three input program pulse voltages V _P1 , V _P2 , and V _P3 and output the selected one to the row decoder 30. Pulse controller 20 outputs a control signal Sp for selecting the program pulse voltage V _P to the multiplexer 10, further outputs a pulsed control signal .phi.p and its inverted signal / .phi.p for controlling program pulse width to the word line switch 40.

The row decoder 30 receives an input address A
Selects a word line in response to DR, applies a pulse voltage V _P received from the multiplexer 10 to the selected word line. Word line switch 40 receives control signal φp from pulse controller 20 and its inverted signal / φp,
The program pulse width applied to the word line is controlled according to these signals. The memory cell array 50 includes a plurality of nonvolatile memory cells arranged in a matrix, and the control gates of the memory cells arranged in each row are connected to the same word line WL. Word lines WL in each memory cell row is selected by row decoder 30, the program having the pulse width set by the pulse voltage V _P and the pulse controller 20 which is selected by the multiplexer 10 to the word line WL of the selected memory cell row A pulse is applied.

FIG. 2 shows the structure of the word line switch 40 controlled by the pulse controller 20 and the memory cell 5
0 shows an example of the configuration of a part of 0. As shown, the word line switch 40 includes a pair of nMOS transistors and pM
A transfer gate 41 composed of an OS transistor and an nMOS
It is composed of a transistor 42. Transfer gate 4
The control signal φp from the pulse controller 20 is applied to the gate of the nMOS transistor constituting
The inverted signal / φp is applied to the gate of the S transistor. One diffusion layer of the nMOS transistor 42 is connected to the word line WL, and the other diffusion layer is grounded. The transfer gate 41 is connected to the row decoder 30 and the word line WL.
Is connected between. Note that such word line switches 40 are connected to each word line on an actual memory chip.

FIG. 2 shows only one memory cell 60 out of the memory cells 50. The actual memory cell array is
It is composed of a plurality of memory cells arranged in a matrix. As shown, the control gate of the memory cell 60 is connected to the word line WL, the drain diffusion layer is connected to the bit line BL, and the source diffusion layer is connected to the source line SL.

[0023] In the word line switch 40, when the control signal φp from the pulse controller 20 is held at a low level, the transfer gate 41 is set to the conductive state, the program pulse voltage V _P output from the row decoder 30 It is applied to the word line WL via the transfer gate 41. When control signal φp is held at a high level, transfer gate 41 is set to a non-conductive state, and furthermore, n
Since the MOS transistor 42 is kept conductive,
Word line WL is held at ground potential GND. As described above, the width of the program pulse applied to the word line WL is controlled by the width of the control signal φp.

In this embodiment, the width of the program pulse applied to the word line WL selected by the row decoder 30 is controlled in accordance with the control signal φp output from the pulse controller 20 and the inverted signal / φp at the time of writing. Is done. Program pulse width is set in accordance with the pulse voltage V _P selected by the multiplexer 10 shown in FIG. The waveform diagram of FIG. 3 shows the relationship between the pulse voltage _VP and the program pulse width.

As shown in FIG. 3A, the program pulse voltage V _P is set to one of three levels V _P1 , V _P2 and V _P3 according to the level of the threshold voltage V _th . Then, the pulse controller 20, the pulse width of the control signal φp is controlled in accordance with the pulse voltage V _P selected. For example, as shown in FIG. 3B, when the low voltage V _P1 is selected, the width of the control signal φp is set wide, and t
It becomes ₁ . When a high voltage V _P2 than the voltage V _P1 is selected, the width of the control signal φp is set to a narrow t ₂ than t _1. Furthermore, when a high voltage V _P3 is selected, the width of the control signal φp is set to the narrowest t _3. As shown in FIG. 3 (c), the program pulses applied to the word line WL is its width is controlled according to the pulse voltage V _P. As described above, the program pulse width applied to the word line WL is controlled according to the width of the control signal φp from the pulse controller 20, and the program pulse is applied to the control gate of the memory cell connected to the word line WL. You. The threshold voltage V _th of the memory cell is controlled by the voltage V _P and the pulse width of the program pulse.

FIG. 4 shows a program pulse for a binary memory for storing 2-bit data in the circuit described above.
Shows the distribution of the curve and the threshold voltage V _th of the threshold voltage V _th. As shown, by the pulse width as the pulse voltage V _P is high is set narrow, the threshold voltage V _th to the memory after writing has substantially the same distribution width at each level. Thus, the distribution range of the threshold voltage _Vth can be controlled to be narrow, which is advantageous in a multi-valued memory.

[0027] As described above, according to this embodiment, the pulse controller 20 outputs a control signal Sp for selecting the pulse voltage V _P to the multiplexer 10 in accordance with the desired threshold voltage V _th, further It generates a control signal .phi.p and its inverted signal / .phi.p controlling the program pulse width according to the level of the selected pulse voltage V _P, and outputs to the word line switch 40. Word line switch 40
Controls the program pulse width applied to the word line selected by the row decoder 30 in accordance with these control signals φp, so that the threshold voltage V
_th can control the distribution width to be narrow.

Second Embodiment FIG. 5 is a distribution diagram of a threshold voltage _Vth showing a second embodiment of the nonvolatile semiconductor memory device according to the present invention. In the present embodiment, deterioration of the characteristics of the memory cell is prevented by limiting the number of times of rewriting of the memory cell of the nonvolatile semiconductor memory device. Normally, the number of rewritable times of the rewritable floating gate type is about one million, but the tunnel oxide film deteriorates according to the number of times of rewriting, and the data retention resistance and read disturb resistance also deteriorate with the number of times of rewriting.

FIG. 5 shows the distribution of the binary memory threshold voltage _Vth of 2 bits / cell. In a multi-valued memory, the highest threshold voltage V _th3 is required to be as low as possible, and the interval between the highest threshold voltage V _th3 and the lowest threshold voltage V _th0 is required to be as narrow as possible. For this reason,
The intervals between individual threshold voltage levels need to be narrow. In the data retention characteristics, the threshold voltage V _th3 approaches the underlying threshold voltage V _th2 quickly, making it difficult to read data “00”. Since the deterioration is accelerated as the number of times of rewriting increases, the data retention resistance of the multi-level memory is sensitive to the number of times of rewriting.

On the other hand, in the read disturb characteristic,
The threshold voltage V _th0 is above the threshold voltage V _th1
And it becomes difficult to read the data “11”. As in the case of the data retention characteristics, the deterioration is accelerated as the number of times of rewriting increases, so that read disturb resistance is also sensitive to the number of times of rewriting.

For this reason, in this embodiment, the number of rewrites is limited to only one. There are many program memory applications in which writing can actually be performed only once. By limiting the number of times of rewriting substantially to one, it is possible to improve the data retention resistance and the read disturb resistance of a multi-valued memory that is sensitive to the number of times of rewriting.

In this embodiment, the erasing of the memory cell may be performed by extracting electrons from the floating gate to the source by FN tunneling, or may be performed by ultraviolet erasing. In particular, in the case of erasing by ultraviolet rays, the distribution range of the threshold voltage _Vth after erasing is narrow, for example, about 0.6 V. As a result, the threshold voltage _{Vth of the} binary memory can be set within a narrow range.

FIG. 5A shows a setting state of the threshold voltage _Vth when erasing by FN tunneling, and FIG. 5B shows a setting state of the threshold voltage _Vth when erasing by ultraviolet rays. ing. In the case of ultraviolet erasing, the threshold voltage V _th0 in the erased state is controlled to about 0.6 V, so that each of the threshold voltages V _th0 , V _th1 , V _th2 , V _th3 is 0.5 V to 1.1 V. 1.8-2.1V;
It is set to four stages of 8-3.1V and 3.8-4.1V. The distribution range of the threshold voltage _Vth can be set narrower than when the electric erasing means shown in FIG. 5A is used.

Furthermore, the erase state data retention resistance of the threshold voltage V _th3 is a threshold voltage V _th3, i.e.,
There is a correlation between the difference between the threshold voltage V _{th0 in the} initial state where no electrons exist in the floating gate and the smaller the difference, the better the tolerance. Note that the initial threshold voltage V _th0 is usually about 1V. As a result, ultraviolet erasing has better data retention resistance than electrical erasing.

Further, in a memory chip using ultraviolet erasing, a circuit for erasing is not required, and an inexpensive memory chip having a small chip size can be obtained. In the manufacturing process, packaging is performed after erasure by ultraviolet rays, and the user performs writing only once and can use it as a program memory.

As described above, according to the present embodiment, by limiting the number of rewrites of the multi-valued memory to only one, both the data retention resistance and the read disturb resistance of the memory cell can be improved, and the chip size can be improved. , And an inexpensive program memory can be obtained.

[0037]

As described above, according to the nonvolatile semiconductor memory device of the present invention, there is an advantage that the distribution range of the threshold voltage of the memory cell can be controlled to be narrow. In addition, by limiting the number of rewrites of the multi-valued memory cell, for example, by limiting the actual writing to only one time, it is possible to improve the data retention resistance and the read disturb resistance that are sensitive to the number of rewrites.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a partial circuit that controls a program pulse.

FIG. 3 is a waveform diagram of a program pulse.

FIG. 4 is a diagram showing a curve and a distribution characteristic of a threshold voltage according to a program pulse.

FIG. 5 is a threshold voltage distribution diagram showing a second embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 6 is a diagram showing a configuration of a memory cell of a nonvolatile semiconductor memory device and a bias state at the time of writing and erasing;

FIG. 7 is a distribution diagram showing a threshold voltage distribution of a multi-level memory.

FIG. 8 is a diagram showing a threshold voltage curve and distribution characteristics according to a conventional program pulse.

[Explanation of symbols]

10: multiplexer, 20: pulse controller, 3
0: row decoder, 40: word line switch, 41: transfer gate, 42: nMOS transistor, 50: memory cell array, 60: nonvolatile memory cell, _VP : program pulse voltage, GND: ground potential.

Claims (6)

[Claims] 1. A nonvolatile semiconductor memory device having a storage element capable of changing a charge amount stored in a charge storage layer according to a voltage value of a write signal and an application time and setting a threshold voltage to a plurality of levels. A non-volatile semiconductor memory device having write control means for shortening the application time of the write signal set to a plurality of voltage values according to a desired threshold voltage level as the voltage value increases. 2. The non-volatile memory according to claim 1, wherein said write control means applies said write signal to a control gate of a storage element in which a source electrode and a drain electrode are respectively biased at a predetermined potential during writing for a set time. Semiconductor memory device. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising voltage setting means for setting a voltage value of said write signal to a plurality of values according to a desired threshold voltage level. 4. A method according to claim 1, wherein the threshold voltage is controlled by changing the amount of charge stored in the charge storage layer by transferring charges to and from the charge storage layer that is electrically insulated from the surroundings. A non-volatile semiconductor memory device having a storage element for storing the storage information, and the storage characteristic of the storage information of the storage element is deteriorated with the transfer of the electric charge. A nonvolatile semiconductor memory device having a write control means for limiting the number of write operations. 5. The nonvolatile semiconductor memory device according to claim 4, wherein said write control means limits the number of times of writing to one. 6. The non-volatile semiconductor memory device according to claim 4, wherein the storage element is erased by ultraviolet irradiation before writing.