JPH10189537A - Dry etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a dry etching method in which a silicon compound layer, particularly a low-dielectric constant interlayer insulating film represented by an SiOF film, can be dry-etched with high anisotropy and with high selectivity. SOLUTION: When a silicon compound layer is dry-etched, an etching gas containing at least one kind of an inert gas selected from a group composed of krypton, xenon and radon is used. In this case, in an overteching operation, it is preferable to use at least one kind of an inert gas selected from a group composed of argon, neon and helium whose mass is comparatively small instead of at least one kind of the inert gas selected from the group composed of krypton, xenon and radon. In addition, it is preferable that a sulfur-based compound which can generate free sulfur in a plasma under a discharge dissociation condition is contained in the etching gas.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for etching a silicon compound layer, which is preferably applied in the field of manufacturing semiconductor devices and the like. In particular, a low dielectric constant silicon compound layer such as a SiOF film is formed with a high aspect ratio, a high anisotropy,
The present invention relates to a method of performing dry etching while achieving high selectivity, high speed, and low particle contamination.

[0002]

2. Description of the Related Art As the integration and performance of semiconductor devices have increased as seen in recent VLSIs, ULSIs, etc., techniques for dry etching of a silicon oxide (SiO ₂ ) -based material layer have been developed. Demands are becoming more stringent.

For example, in order to increase the speed and miniaturization of a semiconductor device, the junction depth of an impurity diffusion region becomes shallower.
In addition, in a situation where various material layers are thin, a dry etching technique which has superior selectivity to the underlayer and less process damage than before is required. As an example of such an etching technique, when a contact is formed in an impurity diffusion region formed in a semiconductor substrate or a source region or a drain region of a PMOS transistor used as a resistance load element of an SRAM, an underlying silicon substrate or SiO ₂ formed on polycrystalline silicon layer
There is a technique for dry-etching an interlayer insulating film.
In this case, improvement of the resist selectivity is also an important issue. This is because in a submicron device, the generation of a slight dimensional conversion difference due to the receding of the resist mask is becoming unacceptable.

Conventionally, dry etching of a silicon oxide-based material layer is performed in a mode in which ionicity is increased in order to cut a strong Si—O bond. In this mode, the incident ion energy of CF _X ⁺ generated from a fluorocarbon-based gas such as CHF ₃ or CF _{4 as} an etching gas is used. In this case, it is also required to realize a high selectivity and anisotropy at the time of etching.However, in order to meet the demand, a protective polymer is conventionally applied to the side wall of a resist or a layer to be etched under gas chemistry conditions. Is formed thickly.

[0005]

However, if the incident ion energy of CF _X ⁺ is increased to perform high-speed etching, the etching reaction becomes closer to physical sputtering, and the etching selectivity decreases. Therefore, it was difficult to achieve both high-speed etching and selectivity. In addition, when etching is performed under gas chemistry conditions, there is a problem in that the etching rate and the particle level decrease during continuous processing. In particular, the problem of lowering the etching rate
This is more noticeable when a fine pattern is formed.

In particular, recently, in high-speed devices such as logic LSIs, the problem of signal delay due to wiring capacitance has become more serious with the increase in wiring layers and density, and a solution to this problem is represented by an SiOF film. The adoption of a low dielectric constant interlayer insulating film is being studied, but F ^* radicals are sequentially generated as an etchant for the resist mask and the underlying silicon material layer during the etching of the SiOF film. It is becoming increasingly difficult to secure the sex.

[0007] In the dry etching as described above, it is always required to prevent the occurrence of contamination which affects device characteristics.

The present invention has been made to solve the above-mentioned problems of the prior art, and has been made to solve the above-mentioned problems.
An object of the present invention is to enable low-dielectric-constant interlayer insulating films represented by iOF films to be dry-etched with high anisotropy and high selectivity.

[0009]

The present inventors have achieved the above object by using an inert gas having a relatively large mass as one component of an etching gas used for dry etching a silicon compound layer. They have found that they can do this and have completed the present invention.

That is, in the first aspect of the present invention, when dry etching a silicon compound layer, at least one selected from the group consisting of krypton, xenon and radon is used.
Provided is a dry etching method characterized by using an etching gas containing various kinds of inert gases.

According to a second aspect of the present invention, when dry etching a silicon compound layer, at least one inert gas selected from the group consisting of krypton, xenon and radon and a fluorocarbon-based compound are used. A first step of just etching the silicon compound layer using a gas to a depth substantially not exceeding its thickness; and removing the silicon compound layer etched in the first step from the group consisting of argon, neon and helium. A dry etching method comprising a second step of performing over-etching using an etching gas containing at least one selected inert gas and a fluorocarbon-based compound.

Further, a third aspect of the present invention is a method for dry-etching a silicon compound layer, wherein the temperature of a substrate to be etched having a silicon compound layer is controlled to a room temperature or lower while a group consisting of krypton, xenon, and radon. A dry etching method characterized by using an etching gas containing at least one kind of inert gas selected from the group consisting of sulfur and a sulfur-based compound capable of producing free sulfur in plasma under discharge dissociation conditions.

In the dry etching method according to the first to third aspects described above, the silicon compound layer may be a low dielectric constant silicon oxide layer containing a halogen element,
Preferably, an SiOF layer is used.

[0014] Other features, objects, and advantages of the invention will be apparent from the description below.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail.

In the first aspect of the present invention, when dry etching a silicon compound layer, krypton (K
r), an etching gas containing at least one inert gas selected from the group consisting of xenon (Xe) and radon (Rn) is used. This etching gas contains
In addition to the inert gas, it is preferable to contain a normal fluorocarbon-based compound used in this type of dry etching.

As described above, when an inert gas having a relatively large atomic weight (mass) as compared with helium (He) or argon (Ar) is used, when only a fluorocarbon compound is used or when an inert gas such as He or Ar is used. Compared to the case where an etching gas containing an active gas is used, the absolute amount of ions having a large mass among charged particles dissociated and generated in discharge plasma increases, and SiO
High-anisotropic and high-speed processing can be efficiently performed in dry etching of a silicon compound layer such as ₂ . In addition, the presence of inert gas particles having a large mass in the etching gas promotes the dissociation of the main etching species CF _x in order to increase the collision probability of electrons in the discharge plasma, and consequently competes with etching. As a result, the F concentration in the fluorocarbon-based polymer to be deposited decreases, and the proportion of carbon atoms in the polymer can be correspondingly stably increased. Thereby, the film quality of the fluorocarbon-based polymer is strengthened, and the resistance to the attack of incident ions and radicals can be increased.
Therefore, the etching of the resist mask and the underlying layer of the silicon material layer is suppressed, and the etching selectivity is greatly improved.

Here, the content ratio and flow rate of the inert gas in the etching gas, the type and the content ratio of the fluorocarbon polymer, and the like are determined with respect to the silicon compound layer to be etched or the resist or underlayer. It can be appropriately determined according to the type of the material, the layer thickness, and the like. Further, other dry etching conditions (pressure, temperature, high-frequency power for plasma generation, and the like) can be appropriately determined.

In particular, when the silicon compound layer is a low-dielectric-constant silicon oxide layer containing a halogen element, in particular, a SiOF film containing a fluorine atom (F) as a constituent element, the advantage of the method of the present invention is further enhanced. Be alive. This is because in the etching of a dielectric constant interlayer insulating film such as a SiOF film containing a halogen element, halogen radicals such as F ^* radicals are successively generated as a reaction product during the etching, so that conventionally, selectivity and anisotropy have been considered. This is because it is difficult to secure the security.

Next, a second embodiment of the present invention will be described.

In the dry etching method of the second aspect, when the silicon compound layer is dry-etched, a first step of etching (just etching) the silicon compound layer to a depth substantially not exceeding the thickness of the silicon compound layer; And a second step of over-etching. Here, the first
K, which has a relatively large mass,
at least one selected from the group consisting of r, Xe and Rn
A group consisting of relatively small masses of Ar, Ne and He instead of a relatively large mass inert gas as an etching gas in the second step using an etching gas containing various kinds of inert gas and a fluorocarbon compound; An etching gas containing at least one inert gas selected from the group consisting of a fluorocarbon compound and an inert gas is used.

In the first step of the second aspect of the present invention, in which the inert gas is properly used, the dry etching method of the first aspect of the present invention is applied. Similarly, highly anisotropic and high-speed processing can be performed efficiently, and the resistance to attack of incident ions and radicals can be increased. Therefore, etching of a resist mask and an underlayer of a silicon material layer can be performed. It is suppressed and the etching selectivity is greatly improved.

The second step of the second aspect of the present invention is a step of over-etching the silicon compound layer just etched, and in this step, the mass of the ion species incident on the substrate is reduced. When the silicon compound layer is etched off and the underlying layer is exposed, physical etching damage to the device by ion impact energy can be reduced. In addition, it is possible to suppress the occurrence of contamination in which impurities are mixed in the underlayer by knocking on the fluorocarbon polymer that is deposited in competition with the etched surface. Therefore, the second aspect of the present invention
The dry etching of the silicon compound layer can be performed with higher anisotropy and higher selectivity than in the case of the first embodiment of the present invention, which is more excellent in low damage and low contamination.

Also in the case of the second embodiment, the content and flow rate of the inert gas in the etching gas, and the type and content of the fluorocarbon polymer, etc. Alternatively, it can be appropriately determined according to the type and layer thickness of the material such as the resist and the underlayer. Further, other dry etching conditions (pressure, temperature, high-frequency power for plasma generation, and the like) can be appropriately determined.

Further, when the silicon compound layer is a low dielectric constant silicon oxide layer containing a halogen element, in particular, a SiOF film containing a fluorine atom (F) as a constituent element, the advantage of the method of the present invention is further enhanced. It will be alive.

Next, a dry etching method according to a third embodiment of the present invention will be described.

In the dry etching method of the third aspect, when the silicon compound layer is dry-etched, the temperature of the substrate to be etched having the silicon compound layer is controlled to a room temperature or lower, and the dry etching method is performed from a group consisting of krypton, xenon and radon. An etching gas containing at least one selected inert gas and a sulfur-based compound capable of generating free sulfur in plasma under discharge dissociation conditions is used.

When the substrate to be etched (wafer) is cooled to a room temperature or lower, the radical reaction is suppressed, and the progress of etching of the resist mask and the underlying material layer is further promoted by the deposition of sulfur that occurs in competition with the etching. Effectively suppressed.

On the other hand, on a silicon compound layer such as SiO ₂ , sulfur reacts with oxygen atoms released during etching and becomes SO or SO ₂ and is easily desorbed. There is almost no decline. Therefore,
Etching with higher selectivity can be performed while maintaining high anisotropy and an etch rate achieved by using an inert gas having a large atomic weight.

If O ₂ plasma ashing is performed after completion of the etching, the deposited sulfur is quickly removed together with the resist mask, so that it does not remain as a residue and does not become a source of particle contamination.

Also in the case of the third embodiment, the content ratio and the flow rate of the inert gas in the etching gas, the type of the fluorocarbon polymer, the type and the content ratio of the sulfur compound, and the like depend on the object to be etched. It can be appropriately determined according to the type and layer thickness of a certain silicon compound layer or a material such as a resist or an underlayer. Further, other dry etching conditions (pressure, temperature, high-frequency power for plasma generation, and the like) can be appropriately determined.

Further, when the silicon compound layer is a low-dielectric-constant silicon oxide layer containing a halogen element, in particular, a SiOF film containing a fluorine atom (F) as a constituent element, the advantage of the method of the present invention is further enhanced. It will be alive.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

Example 1 This example is a specific example of the first embodiment of the present invention, and uses a mixed gas of C ₄ F ₈ and Kr as an etching gas.
This is an example in which a contact hole facing an impurity diffusion layer formed in a silicon substrate is formed in an interlayer insulating film made of silicon oxide (see FIGS. 1A and 1B).

First, an interlayer insulating film 3 made of a SiO ₂ film was formed on a single crystal silicon substrate 1 on which an impurity diffusion layer 2 was formed by a CVD method. On the interlayer insulating film 3, a resist pattern layer 4 having an opening 4a was formed as a mask for etching by predetermined patterning.
(A)).

Next, the substrate to be etched (wafer) was set in a magnetron RIE (reactive ion etching) apparatus, and was etched under the following conditions.

Gas flow rate: C ₄ F ₈ / Kr = 30/90 sccm Pressure: 2.0 Pa RF power Density: 2.0 W / cm ² (13.56 MHz) Magnetic field strength: 1.5 × 10 ⁻² T (150 Gauss) )

In this etching process, SiO ₂ etching by CFx ⁺ ions progressed at an etching rate of about 850 nm / min on the surface of the interlayer insulating film 3 exposed in the opening 4a. As a result, a contact hole 5 having a favorable anisotropic shape was formed (FIG. 1B).
Further, high selectivity is achieved for the resist pattern layer 4 and the single crystal silicon substrate 1, and the selectivity to resist is about 7,
The selectivity to silicon was about 40.

Example 2 This example is a specific example of the first embodiment of the present invention, similar to Example 1, and uses a mixed gas of C ₄ F ₈ and Xe as an etching gas, This is an example in which a via hole facing a lower metal wiring layer is formed in a low dielectric constant interlayer insulating film (see FIGS. 2A and 2B).

First, as the substrate to be processed used in this embodiment, a low dielectric constant interlayer insulating film 8 made of SiOF was formed so as to cover the lower metal wiring layer 7 on the lower interlayer insulating film 6. Further, a resist pattern layer 9 having an opening 9a was formed by predetermined patterning as a mask for etching the interlayer insulating film 8 (FIG. 2A).

Next, the substrate to be etched (wafer) was set in a magnetron RIE apparatus, and was etched under the following conditions.

Gas flow rate: C ₄ F ₈ / Xe = 30/90 sccm Pressure: 2.0 Pa RF power density: 2.0 W / cm ² (13.56 MHz) Magnetic field strength: 1.5 × 10 ⁻² T (150 Gauss) )

In this etching process, the etching of SiOF with CFx ⁺ ions progressed at an etching rate of about 900 nm / min on the surface of the interlayer insulating film 8 exposed in the opening 9a. As a result, a via hole 10 having a favorable anisotropic shape could be formed (FIG. 2).
(B)). Also in this example, the interlayer insulating film 8 could be etched with high selectivity to the resist pattern layer 9 and the lower metal wiring layer 7.

Embodiment 3 This embodiment is a specific example of the second embodiment of the present invention, in which a contact hole facing an impurity diffusion layer formed in a substrate is formed in an interlayer insulating film made of silicon oxide. (See FIGS. 3A to 3C). Here, this embodiment includes a first step (just etching step) and a second step (over etching step).

(First Step) First, S is deposited on a single crystal silicon substrate 1 on which an impurity diffusion layer 2 is formed by CVD.
An interlayer insulating film 3 made of an iO ₂ film was formed. A resist pattern layer 4 having an opening 4a was formed on the interlayer insulating film 3 as a mask for etching by predetermined patterning (FIG. 3A).

Next, the substrate to be etched (wafer) was set in a magnetron RIE (reactive ion etching) apparatus, and was etched under the following conditions.

Gas flow rate: C ₃ F ₈ / Kr = 30/90 sccm Pressure: 2.0 Pa RF power Density: 2.2 W / cm ² (13.56 MHz) Magnetic field strength: 1.5 × 10 ⁻² T (150 Gauss) ) Wafer temperature: 15 ℃

In this etching, the etching of the interlayer insulating film 3 is performed on the single crystal silicon substrate 1, more precisely, on the impurity diffusion layer 2.
Was performed just before the exposure. As a result, as shown in FIG. 3B, a state was left in which a small portion 3a of the interlayer insulating film 3 was left at the bottom of the contact hole 5.

(Second Step) Next, while the wafer in the state shown in FIG. 3B is set in a magnetron RIE (reactive ion etching) apparatus, the etching conditions are changed as follows, and the contact is made. The remaining portion 3a inside the hole 5 was etched and over-etched.

Gas flow rate: C ₄ F ₈ / He = 60/60 sccm Pressure: 2.0 Pa RF power Density: 1.2 W / cm ² (13.56 MHz) Magnetic field strength: 1.5 × 10 ⁻² T (150 Gauss) ) Wafer temperature: 15 ℃

As a result, a contact hole having a favorable anisotropic shape could be formed without damaging the underlying impurity diffusion layer 2 (FIG. 3C).

Embodiment 4 This embodiment is a specific example of the third embodiment of the present invention, and uses a mixed gas of CF ₄ / S ₂ F ₂ / Xe as an etching gas to form a low dielectric constant layer of SiOF. This is an example in which a via hole facing a lower metal wiring layer is formed in an insulating film.

First, as the substrate to be processed used in this embodiment, a low dielectric constant interlayer insulating film 8 made of SiOF was formed so as to cover the lower metal wiring layer 7 on the lower interlayer insulating film 6. Further, a resist pattern layer 9 having an opening 9a was formed by predetermined patterning as a mask for etching the interlayer insulating film 8 (FIG. 2A).

Next, the substrate to be etched (wafer)
Bias applying type ICP (Inductively Coupled Plasm
a) The substrate was set in an etching apparatus, and the substrate to be etched was cooled and held at about −30 ° C. using a chiller and an alcohol-based refrigerant, and etching was performed under the following conditions.

Gas flow rate: CF ₄ / S ₂ F ₂ / Xe = 20/20/60 sccm Pressure: 0.3 Pa ICP Power supply: 1000 W (2 MHz) Substrate bias voltage: 300 V (13.56 MHz) Wafer temperature: −30 ° C

As a result, as shown in FIG. 2B, a via hole 10 having a favorable anisotropic shape could be formed at a high speed without a micro-loading effect. Moreover, no significant decrease in the thickness of the resist pattern layer 9 and no erosion of the underlying layer due to pattern etching were observed.

In the present embodiment, free sulfur was generated in the plasma by the discharge dissociation of the sulfur-based compound, and the free sulfur was deposited on the resist mask and the underlying material layer together with the carbon-based polymer having a low fluorine content. Due to this deposition and the substrate cooling effect, an etching process having high selectivity can be established without generating a micro-loading effect even when the deposition of the carbon-based polymer is slight.

The sulfur deposited during the etching is 1
In order to easily sublimate at a temperature of about 00 ° C., by performing wafer heating after etching in a heated chamber,
It could be removed outside the system. Therefore, the particle level after increasing the number of processed wafers is improved, which leads to an improvement in device yield.

[0059]

According to the dry etching method of the present invention, dry etching of a silicon compound layer proceeds efficiently with high anisotropy and high selectivity.

As a result, high aspect ratio processing of a low dielectric constant interlayer insulating film such as a SiOF film, which was difficult to secure selectivity and anisotropy in the prior art, can be performed by a process having high anisotropy and high selectivity. Can be realized.

Therefore, the present invention provides a fine design
It is designed based on rules and is extremely effective in the future manufacture of semiconductor devices that require high integration, high performance, and high reliability.

[Brief description of the drawings]

FIG. 1 is a process explanatory view when the dry etching method according to the first embodiment of the present invention is applied to the formation of a contact hole (FIGS. (A) and (b)).

FIG. 2 is a process explanatory view when the dry etching method according to the first or third embodiment of the present invention is applied to formation of a via hole (FIGS. 2A and 2B).

FIGS. 3A to 3C are process explanatory diagrams when the dry etching method according to the second embodiment of the present invention is applied to the formation of a contact hole. FIGS.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Single-crystal silicon substrate, 2 ... Diffusion layer, 3 ... Interlayer insulating film (silicon oxide material layer), 3a ... Remaining part of interlayer insulating film, 4 ... Resist pattern layer, 4a ... Opening, 5 ...
Contact hole, 6: lower interlayer insulating film, 7: lower metal wiring layer, 8: upper interlayer insulating film, 9: resist pattern layer, 9a: opening, 10: via hole

Claims (10)

[Claims] 1. A dry etching method, wherein an etching gas containing at least one inert gas selected from the group consisting of krypton, xenon and radon is used when dry etching a silicon compound layer. 2. The dry etching method according to claim 1, wherein the etching gas contains a fluorocarbon compound. 3. The dry etching method according to claim 1, wherein the silicon compound layer is a low dielectric constant silicon oxide layer containing a halogen element. 4. The dry etching method according to claim 3, wherein the low dielectric constant silicon oxide layer containing a halogen element is a SiOF layer. 5. The dry etching of a silicon compound layer, wherein the silicon compound layer is substantially etched using an etching gas containing at least one inert gas selected from the group consisting of krypton, xenon and radon and a fluorocarbon compound. A first step of just etching to a depth not exceeding the thickness of the silicon compound layer; and at least one inert gas selected from the group consisting of argon, neon, and helium in the silicon compound layer etched in the first step. A dry etching method comprising a second step of performing over-etching using an etching gas containing a gas and a fluorocarbon-based compound. 6. The dry etching method according to claim 5, wherein the silicon compound layer is a low dielectric constant silicon oxide layer containing a halogen element. 7. The dry etching method according to claim 6, wherein the low dielectric constant silicon oxide layer containing a halogen element is a SiOF layer. 8. When dry-etching a silicon compound layer, at least one inert material selected from the group consisting of krypton, xenon and radon while controlling the temperature of the substrate to be etched having the silicon compound layer at room temperature or lower. A dry etching method characterized by using an etching gas containing a gas and a sulfur-based compound capable of generating free sulfur in plasma under discharge dissociation conditions. 9. The dry etching method according to claim 8, wherein the silicon compound layer is a low dielectric constant silicon oxide layer containing a halogen element. 10. The dry etching method according to claim 9, wherein the low dielectric constant silicon oxide layer containing a halogen element is a SiOF layer.