JPH10171713A - Disk storage device and method for controlling cache applied to the same device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a processing time required for a read cache processing, and to improve the access speed of a disk storage device by executing each kind of processing necessary for a read cache function by an exclusive hardware without any interference of a CPU. SOLUTION: A read cache controller 20 provided in an HDC 10 sets cache data(look-ahead data) stored in a buffer RAM 11 as a hit range, and judges whether or not read request data from a host system are included in the hit range. When the read request data are included in the hit range as the result of the hit judgment, a buffer address in which the cache data pertinent to the request data are stored is searched, and the cache data are automatically transferred from this buffer address to the host system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a disk storage device having a read cache function applied to, for example, a magnetic disk device and utilizing data read from a disk recording medium as cache data.

[0002]

2. Description of the Related Art Conventionally, a disk storage device such as a hard disk drive (HDD), which is a magnetic disk device,
Although the storage capacity is large as compared with the semiconductor IC memory, the data access speed is low. Therefore, the host system (computer body such as a personal computer)
When a request is made to the HDD for required data (read request), the processing time from when the data is read from the disk recording medium of the HDD (hereinafter simply referred to as a disk) and transferred is relatively long. Therefore, in order to improve the data processing efficiency of the host system, it is desirable to increase the access speed of the HDD, which is a peripheral device that is particularly important as an external storage device.

As a technique for increasing the speed of such access, a so-called read cache function is well known. The read cache function is to transfer data read from the disk in response to the first read request from the host system to the host system, and then continue the read operation from the disk to pre-read the data following the read request data. , A process of storing the data in a buffer memory (buffer RAM). Next, when a read request is issued from the host system, the requested data is stored in the buffer RAM.
If the data is stored in the disk drive, the data is transferred to the host system without executing the read operation from the disk. With such a read cache function, frequently read data can be directly transferred from the buffer RAM to the host system without performing a read operation on the disk, and as a result, the data access operation of the HDD can be speeded up.

As a method of the read cache function, when there is a read request for an address that is continuous with the address of the sector data (logical address from the host system) read by the first read request, the buffer R
There is a process of transferring pre-read sector data to the host system in the AM. These consecutive addresses are called sequential data addresses, and correspond to the start addresses of cache data (pre-read sector data) stored in the buffer RAM.

On the other hand, when a read request of a discontinuous address (random address) occurs with respect to the address of the first read request, the requested data address is replaced with the address of the cache data stored in the buffer RAM. Then, it is determined whether or not the corresponding request data exists in the buffer RAM (hit determination processing). That is, when the sequential data address is SA, the requested data address is A, and the last address (cache data address) of the cache data is EA, the conditional expression "SA
≦ A ≦ EA ”is determined. Here, the cache data address EA is calculated from the sequential data address SA and the number of sector data (the number of pre-read data) read into the buffer RAM. If the requested data address A satisfies the above conditional expression, since the requested data exists in the buffer RAM, the address of the buffer RAM in which the cache data as the requested data is stored is obtained and read from this address. Transfer cache data to the host system.

The HDD is provided with a disk controller (HDC) constituting an interface between the drive and the host system, and the HDC executes data transfer between the disk and the host system. Further, a microprocessor (CPU) constituting the drive control device manages the address of the buffer RAM, and executes the hit determination process and the buffer RAM address calculation process in the read cache function.

[0007]

As described above, the HD
D, etc., use a buffer R used for data transfer operation.
A read cache function is used in which pre-read data is stored as cache data using an AM, and the cache data hit by a read request from the host system is transferred. With such a read cache function, a high-speed data access operation can be realized. However, in the conventional read cache function, the CPU is considerably involved.
An AM address calculation process is being executed. Usually CP
U performs monitoring of various registers (such as a status register) necessary for HDC access command processing in addition to read cache processing, and performs polling processing in a data transfer operation. Therefore, the read cache function involving the CPU is not always efficient, and even if a hit occurs, it takes a considerable processing time to transfer the cache data existing in the buffer RAM.

Accordingly, an object of the present invention is to reduce the processing time required for the read cache process by using a configuration in which various processes required for the read cache function can be executed by dedicated hardware without involving the CPU. To improve the access speed of the disk storage device.

[0009]

SUMMARY OF THE INVENTION The present invention is a disk storage device having a so-called read cache function,
Setting means for setting a hit range of cache data stored in the buffer memory means, determining means for determining whether or not data of a read request from the host system is included in the hit range; When the data of the read request is included in the hit range according to the result of the determination, the apparatus includes an address determination unit that determines an address of the buffer memory unit, and a data transfer unit. The hit range setting means includes, specifically, a cache address holding means for holding a head address of cache data stored in the buffer memory means, and a data number for each predetermined unit of the cache data stored in the buffer memory means. And a means for calculating the last address of the cache data based on the start address and the number of data.

By configuring each of these processing means with a dedicated logic circuit, it is possible to greatly reduce the involvement of the CPU of the drive required for the read cache processing, thereby reducing the processing time of the read cache processing. Can be shortened.

Further, according to the present invention, there is provided a read-ahead means for reading data at an address continuous with an address of data read from a disk recording medium at the time of read access, and storing the data in a buffer memory means; Only the data or the data read by the pre-reading means is set as cache data, the head address holding means for holding the head address of the cache data, and the number of data of the cache data stored in the buffer memory means per predetermined unit. And a data counter means for counting.

The hit range setting means comprises a start address holding means and a data counter means, and sets the hit range based on the start address of cache data and the number of data. Also, the data counter means
The number of pieces of cache data to be stored in the buffer memory means continuously from the cache data is counted together with the number of pieces of cache data for each predetermined unit.
If the data address of the read request is included in the hit range, but the requested data does not exist in the buffer memory means, the cache data corresponding to the requested data is stored in the buffer memory means. Transfer to the host system at that time.

Therefore, the hit determination process required for the read cache process is completed before the cache data is stored in the buffer memory means. Therefore, the requested data is immediately transferred to the host system when the data is stored in the buffer memory means. It becomes possible.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of a disk controller having a read cache function related to the present embodiment, and FIG.
FIG. 3 is a block diagram illustrating a main part of the DD. (System Configuration of HDD) FIG.
As shown in FIG. 1, a disk (recording medium) 1 rotated by a spindle motor 2 and a head actuator 4 hold the disk. A large number of concentric tracks are formed on the disk 1, and each track is divided into a plurality of sectors. In the HDD, data is accessed in sector units. The head actuator 4 is rotationally driven by a voice coil motor (VCM) 5 to move the head 3 in the radial direction of the disk 1. The VCM 5 is driven by a VCM driver 6a included in the double driver 6.
The spindle motor 2 is driven by a spindle motor (SPM) driver 6b.

The head amplifier 7 and the read / write circuit 8 are elements constituting a signal processing system for recording and reproduction. In this embodiment, only the read signal processing system, which is a reproduction operation related to the read cache function, is handled. That is, the read signal read by the head 3 is amplified by the head amplifier 7 and then sent to the read / write circuit 8 to be reproduced as read data. In addition, lead /
The write circuit 8 reproduces not only user data from the read signal but also servo data necessary for controlling the positioning of the head 3. The servo circuit 11 transmits the servo data from the read / write circuit 8 to the CPU 1 via the disk control circuit 9.
2 or VC under the control of the CPU 12.
The drive control of the M driver 6a is performed to execute the positioning control of the head 3. The disk control circuit 9 is composed of a gate array, and is an interface control circuit necessary for controlling various control signals and data transfer.

The CPU 12 is a drive control device.
It operates by a program stored in the ROM 13 and executes various control processes required for the operation of the drive. EEP
The ROM 14 is an electrically erasable PROM,
Stores data requiring non-volatility in the operation of U12. (Structure of Disk Controller) As shown in FIG. 1, a disk controller (HDC) 10 of the present embodiment has a read cache control device 20 related to the present embodiment. The HDC 10 includes a drive and a host system (OS
And a host computer including application programs, and has a disk interface 10a with the disk 1 and a host interface 10b with the host system. HD
The C10 uses the buffer RAM 11 to execute a read / write data transfer operation. The buffer RAM 11 is a buffer memory that stores cache data used for the read cache process related to the present embodiment. (First Embodiment) FIG. 3 is a block diagram showing a specific hardware configuration of a read cache control device 20 as a first embodiment. That is, the read cache control device 20 includes a register 21 for holding a sequential data address (hereinafter, referred to as an address SA), which is a start address of cache data, and a buffer RAM 11.
A disk counter 22 that counts and holds the number of data (sector data number) of cache data stored in the
A register 23 for holding a buffer base address (referred to as a base address BA) of the head data of the cache data stored in the buffer RAM 11;

Further, the read cache control device 20
Is the last data address of the cache data stored in the buffer RAM 11 (cache end address,
A calculation circuit 24 for calculating an end address EA), a register 25 for holding a requested data address QA of a read request from the host system, a hit determination circuit 26, a buffer address calculation circuit 27, and an automatic transfer circuit 28 And

The hit determination circuit 26 calculates the result (end address EA) of the calculation circuit 24 and the requested data address QA.
Then, it is determined whether or not the request data of the read request hits. As will be described later, the buffer address calculation circuit 27 calculates the buffer address of the buffer RAM 11 in which the cache data as the requested data is stored when the result of the determination by the hit determination circuit 26 is a hit. The automatic transfer circuit 28 is a circuit for automatically transferring data read from the address of the buffer RAM 11 calculated by the buffer address calculation circuit 27 to the host system. (Read Cache Processing of First Embodiment) The read cache processing of the first embodiment will be described below with reference to FIGS.

First, when a read command (read request) is issued from the host system, a series of read command processing is executed by the HDC 10 and the CPU 12, and data is read from the disk 1 via the head 3 (step S1). ). Specifically, the CPU 12 controls the disk 1 including the sector corresponding to the logical address of the read command.
The head actuator 4 is driven and controlled to move the head 3 to the upper track. Read data read by the head 3 is transferred to the HDC 10 via the head amplifier 7, the read / write circuit 8, and the disk control circuit 9.

Here, as shown in FIG. 4A, it is assumed that the sector data S1 to S9 are accessed from the disk 1 in accordance with the read request of the host system. These sector data S1 to S9 are transferred to the HDC 10,
As shown in FIG. 3B, the data is temporarily stored in the buffer RAM 11. The data is transferred from the buffer RAM 11 to the host system via the host interface 10B of the HDC 10. This data transfer operation is performed by the automatic transfer circuit 28 shown in FIG.
11 to the host system automatically.

Sector data S1 which is the first request data
When S9 to S9 complete the transfer to the host system, the HDC 10
Then, the CPU 12 executes a normal prefetching process (YES in step S2, S3). By this pre-reading process, the sector data S10-Sn of the address (logical address) continuous to the accessed sector data S1-S9 is transferred to the disk 1
, And store it in the buffer RAM 11 (step S4). The pre-read sector data S10 to Sn are stored as cache data in the buffer RAM 11, as shown in FIG. At this time, cache data of a data amount corresponding to a free area of the buffer RAM 11 is naturally stored.

The read cache control device 2 of the embodiment
At 0, when the cache data is stored in the buffer RAM 11, an address SA (logical address), which is the start address of the cache data, is set in the register 21, as shown in FIG. Further, as shown in FIG. 3B, when the data is stored in the buffer RAM 11 by the disk counter 22, the number of cache data (the number of sector data, here, n-9) is counted and held. Is done. Further, as shown in FIG. 3E, the base address BA (physical address) of the head data of the cache data stored in the buffer RAM 11 is set in the register 23.

In such a state, a new read request is issued from the host system, the requested data is sector data S20, and the logical address is "R20".
(YES in step S5). In the read cache control device 20, as shown in FIG.
In the register 25, a logical address R20 which is a request data address QA of a read request from the host system is set. In the read cache control device 20, the hit determination circuit 26 determines that the request data of the read request
A hit determination process is performed to determine whether the cache data is included in the cache data stored in the AM 11 (step S
6).

Here, in this embodiment, before the operation of the hit determination circuit 26, the buffer RAM is calculated by the calculation circuit 24.
The end address EA (logical address Rn), which is the last data address of the cache data stored in No. 11, is calculated and held (see FIG. 5C). Calculation circuit 2
4 calculates the end address EA from the start address SA of the cache data stored in the register 21 and the number of sector data (n-9) of the disk counter 22. In the embodiment, as shown in FIG. 4B, the hit range is from the logical address R10 (the physical address A10 of the buffer RAM 11) to the logical address Rn (the physical address An of the buffer RAM 11). That is, the hit determination circuit 26 determines whether or not the request data of the read request (sector data S20) hits based on the conditional expression “SA ≦ QA ≦ EA”.

If the result of the determination is not hit, that is, if the requested data of the read request does not exist in the buffer RAM 11, the HDC 10 and the CPU 12 execute the normal read operation as described above and read the requested data from the disk 1. The data is read and transferred to the host system (NO in step S7, S8).

In the embodiment, the request data address QA
Is "R20", the hit determination circuit 26 determines that the corresponding cache data exists in the buffer RAM 11 (YES in step S7). In response to the hit determination result, the buffer address calculation circuit 27 calculates the requested data address QA and the start address S of the cache data.
Based on A and the base address BA of the buffer RAM 11, a buffer address (A20 shown in FIG. 5F) of the buffer RAM 11 in which the cache data as the requested data (sector data S20) is stored (step S9). ). The automatic transfer circuit 28 includes a buffer R
When the buffer address A20 of the AM 11 is set, the data S20 is automatically read from the address A20 and transferred to the host system (Step S10).

As described above, according to this embodiment, the read cache control device 20 responds to the read request from the host system without the involvement of the CPU 12 and performs the hit determination process of the hit determination circuit Buffer address (physical address) of the buffer RAM 11
Is executed. Thereby, the buffer RA
If the cache data prefetched in M11 includes the request data of the read request, the buffer RAM is not involved without the involvement of the CPU 11 and the operation of reading from the disk 1.
11 automatically transfers the requested data to the host system. Therefore, it is possible to greatly shorten the read access time and increase the access speed, as compared with the conventional method in which the CPU 12 is involved.

The first embodiment is based on the premise that the data read first from the data accessed first is stored as cache data in the buffer RAM 11, and the cache data is set as a hit range (FIG. 4).
(See (B)). However, data S1 to S9 read first may be set as the hit range according to the storage area amount of the buffer RAM 11. In this case, when the host system requests the same data (for example, S1) as the data S1 to S9 requested to be read first, the read cache control device 20 reads the data from the buffer RAM 11 and automatically transfers the data to the host system. Will be. If the read request from the host system does not hit, the contents of the buffer RAM 11 are all updated, and the data newly read from the disk 1 and the prefetch data are stored in the buffer RAM 11. (Second Embodiment) FIGS. 7 to 10 show a read cache process related to the second embodiment. Second
In the embodiment, as shown in FIG.
Not only the cache data that stores the hit range of
This is a method that expands to cache data to be stored.

More specifically, as shown in FIG. 7, the read cache control device 20 of the embodiment includes a segment size counter 30 for counting the number of sector data that can be stored in the buffer RAM 11 instead of the disk counter 22. Have. The other configuration is the same as the first configuration shown in FIG.
This is the same as the embodiment.

The operation of this embodiment will be described below with reference to the flowchart of FIG. First, when a read request is issued from the host system, a series of read command processing is executed by the HDC 10 and the CPU 12, and as shown in FIG.
The data is transferred to C10 and stored in the buffer RAM11. Then, the first request data, ie, the sector data S1
When S9 to S9 complete the transfer to the host system, the HDC 10
Then, the CPU 12 executes a normal prefetching process (steps S20 to S22). As a result of this pre-reading process, the sector data S10 to Sn of addresses (logical addresses) consecutive to the accessed sector data S1 to S9 are read from the disk 1 and stored in the buffer RAM 11 (step S23). Up to this point, the operation is the same as in the first embodiment.

Next, when a new read request is issued from the host system, in the read cache control device 20, the hit determination circuit 26 determines that the request data from the host system is included in the cache data stored in the buffer RAM 11. A hit determination process is performed to determine whether a hit has occurred (steps S24 and S25). In the same embodiment, the request data of the host system is the sector data S.
20 and the logical address is “R20”. Therefore, the request data address QA is stored in the register 25.
Is set.

In the embodiment, the calculation circuit 24 calculates the start address S of the cache data stored in the register 21.
The end address EA is calculated from A and the number of sector data counted by the segment size counter 30. The segment size counter 30 has a buffer R
This is the number of sector data stored in the AM 11 and counts not only the sector data currently stored but also the number of sector data to be stored according to the free space. here,
As shown in FIG. 9, the segment size counter 30 holds "m-9" as the number of sector data. "M"
Is, in the buffer RAM 11, as shown in FIG.
This is a value obtained by adding the number n of prefetched sector data and the number of sector data to be stored (the final physical address is Am).

When the result of the determination by the hit determination circuit 26 does not hit, that is, when the request data of the read request
If not present in M11, HDC10 and CPU1
2 executes the normal read operation as described above, reads the requested data from the disk 1, and transfers it to the host system (NO in step S26, S27).

In the embodiment, the request data address QA
Is "R20", the hit determination circuit 26 determines that the corresponding cache data exists in the buffer RAM 11 (YES in step S26). In response to the hit determination result, the buffer address calculation circuit 27 calculates the requested data address QA, the start address SA of the cache data, and the base address BA of the buffer RAM 11.
RAM 11 storing cache data as request data (sector data S20) based on
The buffer address (A20 shown in FIG. 8) is calculated (step S28). The automatic transfer circuit 28 includes a buffer R
When the buffer address A20 of the AM 11 is set, the data S20 is automatically read from the address A20 and transferred to the host system (YES in step S29).
S31).

In this embodiment, as shown in FIG. 8, the hit range of the buffer RAM 11 by the hit determination circuit 26 is expanded not only to the number of sector data currently stored but also to the number of sector data to be stored. . Therefore, even when the data of the read request from the host system hits, a state where the data is not currently stored in the buffer RAM 11 may occur. In this case,
The automatic transfer circuit 28 waits until the data is read from the disk 1 and stored in the buffer RAM 11, and performs a process of transferring the requested data (cache data) to the host system when the requested data is stored (NO in S29, S29).
30). Here, when the data is not stored in the buffer RAM 11 at the present time, the automatic transfer circuit 28 selects whether or not to wait under a predetermined condition (for example, standby time), and stops the data transfer operation when not waiting. As a result, the CPU 12 may switch the read cache operation to the normal read operation and read the requested data from the disk 1.

As described above, according to the first embodiment, the sector data pre-read during the pre-read processing is stored in the buffer RAM 1.
Even when a read request is issued from the host system during the period of transfer to 1, the read cache function can be exhibited. That is, a hit range including cache data that is not stored in the buffer RAM 11 at the time of the read request but is to be stored can be set, and hit determination processing of the requested data can be executed. Therefore, when the prefetch data to be stored is stored in the buffer RAM 11, it can be automatically transferred to the host system immediately. This makes it possible to further improve the efficiency of the read access process as compared with the case of the above-described first embodiment.

[0037]

As described above in detail, according to the present invention, in a disk storage device having a read cache function, data can be stored in a buffer memory by a dedicated hardware configuration without involving a CPU for controlling a drive. It is possible to shorten the processing time of the read cache processing using the cache data obtained. Therefore, as a result, the read operation for reading data from the low-speed access disk can be reduced, and the read access speed can be increased by high-speed transfer from the buffer memory. Further, the hit rate in the read cache processing can be increased by a method of expanding the hit range including the cache data to be stored in the buffer memory. Also, even if a read request is issued from the host system during the cache data read-ahead processing from the disk, the cache data corresponding to the requested data can be automatically transferred when stored in the buffer memory, resulting in read access. Processing efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a disk controller according to an embodiment of the present invention.

FIG. 2 is an exemplary block diagram showing a main part of the HDD related to the embodiment;

FIG. 3 is a block diagram showing a main part of the read cache control device according to the first embodiment;

FIG. 4 is a conceptual diagram for explaining an operation related to the first embodiment.

FIG. 5 is a conceptual diagram showing the contents of each register for describing an operation related to the first embodiment.

FIG. 6 is a flowchart for explaining an operation related to the first embodiment.

FIG. 7 is a block diagram showing a main part of a read cache control device according to the second embodiment;

FIG. 8 is a conceptual diagram of a buffer RAM for explaining an operation related to the second embodiment.

FIG. 9 is a conceptual diagram showing the contents of a segment size counter for describing an operation related to the second embodiment.

FIG. 10 is a flowchart for explaining an operation related to the second embodiment.

[Explanation of symbols]

 Reference Signs List 1 disk 2 spindle motor 3 head 4 head actuator 5 voice coil motor (VCM) 6 double driver 6a VCM driver 6b SPM driver 7 head amplifier 8 read / write circuit 9 disk control circuit 10 ... Disk controller (HDC) 11 ... Buffer RAM (buffer memory means) 12 ... CPU 13 ... ROM 14 ... EEPROM 20 ... Read cache control device 21 ... Sequential data address register 22 ... Disk counter 23 ... Buffer base address register 24 ... Cache end address calculation circuit 25 Request data address register 26 Hit detection circuit 27 Buffer address calculation circuit 28 Automatic transfer circuit

Claims (10)

[Claims] 1. A disk having buffer memory means for storing data read from a disk recording medium at the time of read access, and having a read cache function of reading read request data from said buffer memory means and transferring it to a host system. A storage device, comprising: setting means for setting a hit range of cache data stored in the buffer memory means; and determining whether data of a read request from the host system is included in the hit range. Determining the address of the buffer memory in which the cache data corresponding to the read request is stored when the data of the read request is included in the hit range based on the determination result of the determining unit. Address determining means for determining Disk storage device according to claim cache data address from said buffer memory means that has and a data transfer means for transferring to the host system. 2. The method according to claim 1, wherein the setting unit includes a cache address holding unit that holds a start address of the cache data stored in the buffer memory unit, and a data of the cache data stored in the buffer memory unit for each predetermined unit. Data counter means for counting the number, and means for calculating the last address of the cache data based on the start address and the number of data, wherein the hit range is calculated based on the start address and the end address. 2. The disk storage device according to claim 1, wherein the setting is performed. 3. The disk storage device according to claim 1, wherein said address determination means comprises a dedicated logic circuit. 4. The data transfer means has an automatic transfer function for reading cache data at the address determined by the address determination means from the buffer memory means and automatically transferring the data to the host system. 2. The disk storage device according to claim 1, wherein: 5. A disk having buffer memory means for storing data read from a disk recording medium at the time of read access, and having a read cache function of reading read request data from said buffer memory means and transferring it to a host system. A prefetch means for reading data at an address subsequent to an address of data read from the disk recording medium at the time of the read access, and storing the data in the buffer memory means; All data or only data read by the pre-reading means is set as cache data, and a head address holding means for holding a head address of the cache data; and a predetermined unit of the cache data stored in the buffer memory means. Count the number of data Data counter means, base address holding means for holding a base address of the buffer memory means corresponding to the head address of the cache data, and setting a hit range based on the head address of the cache data and the number of data. Determining means for determining whether a request data address issued by a read request from the host system is included in the hit range; and when the request data address is included in the hit range by the determination means, Address determining means for calculating an address of the buffer memory means in which cache data corresponding to the read request is stored based on the base address, the head address and the request data address; and an address of the address determined by the address determining means. cache A data transfer unit for transferring data from the buffer memory unit to the host system. 6. The data counter means for counting the data number of the cache data scheduled to be stored in the buffer memory means consecutively with the cache data, together with the data number of the cache data for each predetermined unit. The data transfer unit, when the cache data of the address calculated by the address determination unit is not stored in the buffer memory unit, stores the cache data to be stored in the buffer memory unit 6. The disk storage device according to claim 5, further comprising means for transferring the read data to the host system as request data corresponding to the read request. 7. When the cache data at the address calculated by the address determination means is not stored in the buffer memory means, the data transfer means stores the cache data to be stored in the buffer memory means. Means for selecting whether or not to wait until the data is stored; when the scheduled cache data is stored in the buffer memory means in a standby state, the host system outputs the request data as request data corresponding to the read request. 7. The disk storage device according to claim 6, wherein the data is transferred. 8. The address determining means includes means for calculating a difference between the start address and the requested data address, and adding the calculated difference to the base address to determine whether the cache data corresponding to the read request is present. 6. The disk storage device according to claim 5, further comprising means for calculating an address of said buffer memory means stored therein. 9. A disk having buffer memory means for storing data read from a disk recording medium at the time of read access, and having a read cache function of reading read request data from said buffer memory means and transferring it to a host system. A cache control method applied to a storage device, comprising: a read-ahead process of reading data at an address subsequent to an address of data read from the disk recording medium at the time of the read access, and storing the data in the buffer memory unit; A process of setting all data stored in the memory means or only data read by the prefetch processing as cache data, and holding a head address of the cache data; and storing the head address of the cache data and the buffer memory means Done A process of setting a hit range based on the number of pieces of cache data, a process of determining whether a request data address issued by a read request from the host system is included in the hit range, and a process of determining the request data address. Is included in the hit range, an address calculation process of calculating an address of the buffer memory means in which cache data corresponding to the read request is stored; and calculating the cache data corresponding to the read request by the address calculation. Reading from the address of the buffer memory means calculated by the processing and transferring the read data to the host system. 10. A disk having buffer memory means for storing data read from a disk recording medium at the time of read access, and having a read cache function of reading read request data from said buffer memory means and transferring it to a host system. A cache control method applied to a storage device, comprising: a read-ahead process of reading data at an address subsequent to an address of data read from the disk recording medium at the time of the read access, and storing the data in the buffer memory unit; A process of setting all data stored in the memory means or only data read by the pre-read processing as cache data, and holding a head address of the cache data; and setting a predetermined value of the cache data stored in the buffer memory means. Data for each unit Data count processing for counting the data number of the cache data to be stored in the buffer memory means continuously with the cache data together with the data number, and a hit based on the head address of the cache data and the data number. A process of setting a range; a process of determining whether a request data address issued by a read request from the host system is included in the hit range; and a process of determining whether the request data address is included in the hit range. An address calculation process for calculating an address of the buffer memory means in which cache data corresponding to the read request is stored; and an address calculation process for calculating the cache data corresponding to the read request by the address calculation process. Read from the host system Transfer to the system
If the cache data is not stored in the buffer memory means, it waits until it is stored, and when the cache data is stored in the buffer memory means, the cache data is sent to the host system as request data corresponding to the read request. And a transfer process.