JPH10135735A - Oscillator output buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the current consumption by decreasing current consumption of a pre-stage circuit that provides an output of a clock signal with a small amplitude. SOLUTION: A clock signal whose amplitude is 0.5V is fed to a capacitor 1. Through charging/discharging to/from the capacitor 1, the input signal to the capacitor 1 is given to a NAND gate 3 while being level-shifted in a AC signal level around a threshold level of the NAND gate 3. In the case that an oscillation control signal is at logical H, when a level at a point (a) is smaller than the threshold level, a current flows to a ground of an output buffer circuit from a power supply through an output terminal of the NAND gate 3, a resistor 2 and the capacitor 1 to bring a voltage at the output terminal close to a power supply voltage. In the case that the level at the point (a) by the AC signal is larger than the threshold level, a current flows to the ground through the resistor 2 and the output terminal of the NAND gate 3 to bring the voltage of the output terminal close to a ground level. The output of the NAND gate 3 is inverted by an inverter 4, its output is given to an AND gate 5, from which a waveform-shaped output is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an oscillator output of a low power supply voltage system (for example, 1.0 V system) whose amplitude can be used as a clock of a control unit of a high power supply voltage system (for example, 3.0 V system). The present invention relates to reducing the current consumption of an oscillator output buffer circuit for amplification.

[0002]

2. Description of the Related Art Generally, a receiver includes an antenna, a power supply,
Radio unit, demodulation unit, control unit, CPU, sounder, and LC
A D display and the like are provided. With the development of mobile communications,
A receiver using a battery (for example, 1.5 V) such as a pager receiver, a mobile phone, and a PHS is widely used. As described above, in a receiver using a battery, reduction in current consumption is an issue. From the viewpoint of reduction in current consumption, the wireless unit uses a low power supply voltage system such as 1.0 V and uses a control unit and a CPU. In many cases, the power supply unit operates on a high power supply voltage system in which the battery voltage is boosted by the power supply unit.

Since the operation of the receiver is generally similar, the following description will be given by taking the case of a pager receiver as an example. The radio section employs a double superheterodyne system. 280 received by antenna
The reception wave in the MHz band is amplified by an RF amplifier, passes through a SAW band-pass filter (hereinafter referred to as BPF) in a wireless band, and received by a first mixer at a first intermediate point of a difference between the reception wave and a first local oscillation frequency. Converted to frequency. Then, X'tal BP
F, the frequency is converted to a second intermediate frequency of a difference between the first intermediate frequency and the second local frequency by the second mixer,
Through the BPF of the intermediate frequency band, IF amplifier, IF
Amplified by limiter amplifier, passed through detector, 450K
The signal is passed to the demodulation unit as a signal of Hz.

[0004] The radio section has two local oscillators. In the first local oscillator, the frequency synthesizer divides the frequency of the output of a voltage controlled oscillator (hereinafter, referred to as VCO) by frequency information from the controller, and divides the frequency of the output into a crystal oscillator (reference oscillation). By comparing the output of the VCO with the phase, the output of the VCO is fixed to a frequency that matches the frequency information from the control unit. Thereafter, the output of the VCO is tripled by a triple buffer circuit, and is amplified to a specified level.
Input to the mixer. The second local oscillator extracts the output of the crystal oscillator of the frequency synthesizer, doubles the frequency with a double buffer circuit, amplifies the frequency to a specified level, and inputs the amplified signal to the second mixer as a second local oscillator. Is done.

Here, the frequency relationship will be described. The top frequency of the radio section is in the 280 MHz band, passed to the demodulation section at a frequency of 450 KHz, and the second intermediate frequency is 29.25 MHz, so the second local oscillation frequency is:
It becomes 28.8 MHz. The second local station has doubled,
The frequency of the source crystal oscillator is 14.4 MHz. The frequency of the reference oscillator of the frequency synthesizer of the first local oscillator can be varied by frequency information from the controller. The reference frequency at the phase comparator in the frequency synthesizer is 12.5 / 3 Khz, and the frequency of the reference oscillator may be an integer multiple of this reference frequency, so 14.4 MHz
There is no problem with z. For this reason, the frequency of the crystal resonator is 14.4 MHz.

[0006] As one function of the demodulation section, a clock having a frequency used in the demodulation section and the control section is generated. The control unit includes blocks such as a decoder and a CPU interface. The frequency of the clock used in the demodulation unit and the control unit is 160 KHz, 800 KH
z, 1.6 KHz, 3.2 KHz, etc. There are various kinds of these, but when they are multiplied by an integer, they all become 14.4 MHz of the frequency of the crystal unit used in the radio unit. Can share the reference oscillation crystal unit of the frequency synthesizer of the first local oscillator of the radio unit. This is effective for reducing the number of parts and reducing the manufacturing cost of the device. These frequencies correspond to the crystal oscillator 1 supplied from the radio unit in the demodulation unit.
An output of 4.4 MHz is taken out and frequency-divided (depending on the frequency) several times to generate a clock of a required frequency in the demodulation unit and the control unit.

Next, the power supply system will be described. The radio section
A 1.5V power supply is supplied from a battery, and this is converted to a stable power supply of 1.0V by a radio unit and supplied to each block. The radio unit operates on a 1.0V system. This is a low voltage operation to reduce the current. On the other hand, the power supply voltage of the LSI constituting the demodulation unit and the control unit is:
3.0 V, which is limited due to the physical characteristics of the standard cell LSI used for the LSI.
Operation is impossible. This is supplied by boosting a 1.5V power supply from a battery to 3V by a DC / DC converter. As described above, the wireless unit and the LSI cannot operate at the same power supply voltage, and therefore have different power supply voltages.

The output of the crystal oscillator of the reference oscillator of the frequency synthesizer section of the radio section has an amplitude of only 0.1 V _pp because the power supply voltage is operated at 1.0 V, and is a pure analog circuit. Is a logic circuit using complementary field effect transistors (hereinafter, referred to as CMOS), the threshold level of which is 1.
It is necessary that the amplitude be such that the logic L / H can be identified stably around 5 V. As the amplitude for that purpose, 2.5-3.
The value was 0 V _pp . Therefore, in the radio section, the output of the crystal oscillator is taken out before the output of the crystal oscillator is passed to the demodulation section, and an oscillator output buffer circuit using an NPN bipolar transistor can operate with a 3 V system with an amplitude of 3 V _pp.
The amplitude has been amplified until it is supplied to the demodulation unit.

[0009]

However, in the conventional oscillator output buffer circuit, the output (0.
1 V _pp ), and in order to obtain the required amplitude (3.0 V _pp ) in the demodulation unit and the control unit, a current of about 1 mA is consumed in an oscillator output buffer circuit using a transistor using a 3 V system power supply. I will. For example, in a pager receiver, about 3 mA is used for other output buffer circuits, mixers, BPFs, and the like of the reception section of the radio section, and about 1 m is used for the control section.
A, about 5 including the current consumption of the oscillator output buffer circuit
A current consumption of mA flows. The consumed current of the oscillator output buffer circuit consumes about 1/5 of the whole, and reduction of the consumed current is a problem in the pager receiver using the battery. This is because, even in other receivers, the clock of the oscillator using the low power supply voltage is set to L using the high power supply voltage.
The same problem has been encountered when amplifying to the SI clock.

[0010]

In order to solve the above-mentioned problems, an oscillator output buffer circuit according to the present invention comprises a capacitor to which a clock signal having a constant amplitude voltage is input to one electrode, and another electrode of the capacitor. Is connected to the gate,
A P-channel field effect transistor having a source connected to the first power supply voltage and a drain connected to the output terminal;
A gate is connected to the other electrode of the capacitor,
A source is connected between an N-channel field-effect transistor whose source is connected to a second power supply voltage, the other electrode of the capacitor, and the output terminal. The ON resistance of the P-channel field-effect transistor when the P-channel field-effect transistor is turned on, and the N-channel type when the N-channel field-effect transistor is turned on by the input of the clock signal to the capacitor. And a resistor having a resistance value larger than the on-resistance of the field effect transistor. Since the present invention is configured as described above, when the input voltage of the inverter constituted by the PMOS and the NMOS is smaller than the threshold level, the PMOS is turned on, and the PMOS transistor is turned on from the first power supply voltage.
S, a charging current flows to the capacitor via the resistor, and the voltage of the other electrode of the capacitor increases.

When the input voltage of the inverter becomes higher than the threshold level, the NMOS turns on, a discharge current flows from the capacitor to the second power supply voltage via the resistor and the NMOS, and the other electrode of the capacitor is turned on. Voltage drops. As a result, the voltage of the other electrode of the capacitor becomes equal to the threshold level of the inverter, and the DC component (intermediate potential) of the clock signal to the capacitor is level-shifted so as to be equal to the threshold level of the inverter. The input voltage is an AC signal whose amplitude is centered on the threshold level. When the input voltage is higher than the threshold level, the NMOS turns on, and a discharge current flows from the capacitor to the second power supply voltage via the resistor, the output terminal, and the NMOS. Since the resistance is greater than the on-resistance of the NMOS, the voltage at the output terminal drops to near the second power supply voltage. When the input voltage of the inverter is lower than the threshold level, the PMOS turns on, and a charging current flows to the capacitor via the first power supply voltage, the PMOS, the output terminal, and the resistor. Since the resistance is larger than the ON resistance of the PMOS, the voltage at the output terminal rises to near the first power supply voltage.

[0012]

FIG. 1 is a configuration diagram of an oscillator output buffer circuit according to an embodiment of the present invention. This oscillator output buffer circuit includes a capacitor 1, a resistor 2, a NAND gate 3, an inverter 4, and an AND gate 5.
A clock having a small amplitude voltage is input to one electrode of the capacitor 1. The other electrode of the capacitor 1 is connected to one terminal of the resistor 2 and the
It is connected to one input terminal of the ND gate 3. NA
An oscillation control signal is input to the other input terminal of the ND gate 3 via a pad provided at point d. The output terminal of the NAND gate 3 is connected to the input terminal of the inverter 4 and the other terminal of the resistor 2 via a pad provided at point b. The output terminal of the inverter 4 is connected to an AND gate 5
Connected to one of the input terminals.

The other input terminal of the AND gate 5 receives an oscillation control signal. The output terminal of the AND gate 5
It is connected to a pad provided at point c. The NAND gate 3, the inverter 4, and the AND gate 5 are standard cells (oscillation macro cells). The NAND gate 3, the inverter 4, and the AND gate 5 are formed of CMOS, and have a first power supply voltage (hereinafter simply referred to as a power supply voltage) of a PMOS source of 3.0 V and a second power supply voltage of an NMOS source. Is ground (0 V), and the threshold level is 1.5 V. The lower limit of the amplitude voltage of the clock of the input signal that can be amplified by the oscillator output buffer circuit is determined by the power supply voltage, the threshold level of the NAND gate 3, and the like. The threshold level is set to 1.5 V, and the amplitude voltage of the clock of the input signal is set to 0.5 V _pp .

The capacitor 1 is for shifting the level of the DC component (intermediate potential) of the input signal to a threshold level (1.5 V) by charging from the power supply voltage to discharging to ground. The resistor 2 electrically connects the output terminal of the NAND gate 3 and one of the input terminals to charge the capacitor 1 from the power supply voltage or discharge the capacitor 1 to the ground, thereby providing an intermediate signal between the input signals to the capacitor 1. The potential is level-shifted to a threshold level, and the input signal of one input terminal of the NAND gate 3 is converted into an AC signal with the threshold being an intermediate potential.
When the MOS / NMOS is turned on to charge the capacitor 1 via the resistor 2 from the power supply voltage of 3.0 V / discharge the capacitor 1 from the capacitor 1 to the ground via the resistor 2, the NAND3
A resistance value (for example, 1 MΩ to 10 MΩ) that is set so that the voltage of the output terminal is amplified to a voltage close to the power supply voltage / ground and the current consumption is low (several μA or less).
Is used.

FIG. 2 is a block diagram of a pager receiver using the oscillator output buffer circuit of FIG. In this pager receiver, the oscillator output buffer circuit of FIG.
60 are provided. The pager receiver includes an antenna 10, a 1.5V battery 20, a radio unit 30, a power supply unit 50,
It includes an LSI 60, a crystal oscillator 100, a CPU 110, a sounder 120, an LCD display 130, and the like.
The output terminal of the antenna 10 is connected to the input terminal of the radio unit 30. Battery 2 is connected to wireless unit 30 and power supply unit 50. The power supply unit 50 has a DC / DC converter 51 and supplies 3.0 V power to the LSI 60 and the CPU 110.

The LSI 60 is composed of 3.0 V standard cells and a CPU, and has an oscillator output buffer circuit 70, a demodulation unit 80, and a control unit 90. The control unit 90 has a decoder 91, a CPU interface 92, and the like. An output terminal of the detection signal of the radio unit 30 is connected to an input terminal of the demodulation unit 80, and an output terminal of the clock signal of the radio unit 30 is connected to the oscillator output buffer circuit 7.
0 is connected to one electrode of the capacitor 1 in FIG. An output terminal of the oscillator output buffer circuit 70 is connected to an input terminal of the demodulation unit 80. An output terminal of the demodulation unit 80 is connected to an input terminal of the control unit 90. LSI
The output side of 60 is connected to CPU 110 and sounder 120. The output terminal of the crystal oscillator 100 is connected to the CPU of the control unit 90 and the CPU 110. C
The output terminal of the PU 110 is connected to the input terminal of the LCD display 130.

FIG. 3 is a configuration diagram of the radio unit 30 in FIG. As shown in FIG. 3, the radio unit 30 includes the RF amplifier 3
1, BPF 32, mixer 33, BPF 34, crystal oscillator 33, frequency synthesizer 34, VCO 35, triple output buffer circuit 36, mixer 37, BPF 38, double output buffer circuit 39, mixer 40, BPF 41, IF
An amplifier 42, an IF limiter amplifier 43, a detection unit 44, and an output buffer circuit 45 are provided.
Is connected to the output terminal of the output buffer circuit 45. The power supply of the radio unit 30 is:
The battery 2 is a 0 V system and is not shown, but is a 1.5 V battery 2 in FIG.
It is generated by a stabilized power supply circuit from 0 and uses 1.0V. In this example, the RF amplifier 31 has a 280 MHz band, a BP
F32 is a 280 MHz band SAW filter, the triple output buffer circuit 36 is a triple output buffer circuit for outputting a clock of the first local frequency in the 250 MHz band, and the double output buffer circuit 39 is a first local frequency of 28.8 MHz. Output buffer circuit that outputs the clock of
38 is a 29.25 MHz band X'tal filter, BPF4
Reference numeral 1 denotes a 450 KHz ceramic filter. The oscillation frequency of the crystal oscillator 33 is 14.4 MHz, the output amplitude V _pp is 0.1 V. Output buffer circuit 45
Is composed of an amplifier circuit using a transistor of 1.0 V system, the output amplitude is 0.5 V _pp , and the current consumption is 0.2 m
A.

FIG. 4 is a time chart of FIG. Hereinafter, the operation of FIGS. 1 to 3 will be described with reference to FIG.
The voltage of 1.5 V from the power supply 20 is supplied to the wireless unit 30 and the power supply unit 50. The DC / DC converter 51 in the power supply unit 50 converts a 1.5V power supply to a 3.0V power supply and supplies the power to the LSI unit 60. On the other hand, the radio unit 30 converts the voltage into a stable power supply of 1.0 V by a stabilized power supply circuit (not shown),
5 is supplied with a power of 1.0 V. Crystal oscillator 33
Generates a reference clock having a frequency of 14.4 MHz. Since the power supply voltage of the crystal unit 33 is 1.0 V, the amplitude of the reference clock is 0.1 Vp _{- p} . This reference clock is input to the frequency synthesizer 34, the doubled output buffer 39, and the output buffer circuit 45. The frequency information defining the oscillation frequency of the VCO 35 is input from the control unit 90 to the frequency synthesizer 34, and the VCO 3
From 5, a clock having a specified oscillation frequency is output to the tripled output buffer circuit 36. The frequency is tripled by the tripled output buffer circuit 36, so that the first
The clock of the local oscillation frequency is input to the mixer 37.

The frequency of the reference clock is doubled by a double output buffer circuit 39, and a clock having a second local oscillation frequency of 28.8 MHz is input to the mixer 40. The output buffer circuit 45 is an amplifying circuit having a gain of 5 constituted by a 1.0 V transistor or the like. Therefore, the output buffer circuit 45 amplifies a reference clock having an amplitude of 0.1 V _{pp into} a clock having an amplitude of 0.5 V _pp , 1 to one of the electrodes. At this time, the consumption current flowing through the output buffer circuit 45 is 0.
2 mA. The base station transmits a 280 MHz band radio wave at a frame interval of 12.5 kHz by modulating a user unique number and a message designating a pager receiver as a transmission destination on a predetermined frame by FSK modulation or the like.

In the radio section 30, the received wave received by the antenna 1 is amplified by the RF amplifier 31, passes through the BPF 32 of the 280 MHz band, and is received by the first mixer 37 and the third wave from the tripled output buffer circuit 36. It is converted to a first intermediate frequency having a difference from one local oscillation frequency. After that, the signal passes through the BPF 38 of the first intermediate frequency band and the second intermediate mixer 40 and the second intermediate frequency from the doubled output buffer circuit 39.
Frequency conversion to a second intermediate frequency of the difference from the local oscillation frequency,
The signal passes through the BPF 41 in the band of the second intermediate frequency, is amplified by the IF amplifier 42 and the IF limiter amplifier 43, and
4, the detection output signal is input to the demodulation unit 80 in FIG. When no radio wave is transmitted from the base station to the pager receiver, the control unit 90 does not need to perform demodulation and decoding.
When a radio wave in the HZ band is received, the transmission control signal is set to the “H” level (3.0 V). At other times, the oscillation control signal is set to the “L” level (0 V), and the oscillator output buffer circuit 70 is controlled. It is output to point d in FIG. The oscillation control signal is input to the input terminals of the NAND gate 3 and the AND gate 5 in FIG.

(A) When the oscillation control signal is at "H" level The oscillation control signal at "H" level is inputted to the other input terminal of the NAND gate 3, and the PMOS to which the oscillation control signal is inputted is turned on. , NMOS is turned off, and NAND
The gate 3 is connected between the PMOS connected to the capacitor 1 and the NM.
It will operate as an inverter by the OS. When the voltage at the input terminal of the inverter is lower than the threshold level, the PMOS of the inverter is turned on, the capacitor 1 is charged from the power supply voltage via the resistor 2, and the potential of the other electrode of the capacitor 1 ( The inverter input voltage). Then, when the input voltage of the inverter becomes higher than the threshold level, the NMOS is turned on, and the capacitor 1 is discharged to ground via the resistor 2 to lower the input voltage of the inverter. As a result, the capacitor 1 is charged until the potential of the other electrode of the capacitor 1 reaches the threshold level of the inverter. The input signal of the inverter is such that the intermediate potential of the input signal of the capacitor 1 is the threshold level of the inverter (1. 5V).

When the potential at point a due to this AC signal is smaller than the threshold level,
The MOS is turned on, the NMOS is turned off, and the output terminal of the PMOS, the NAND gate 3, the resistor 2,
The output buffer circuit 45 in FIG.
A current flows to the ground. The voltage at the output terminal of the NAND gate 3 has a value obtained by dividing the voltage by the on-resistance of the PMOS of the inverter and the resistor 2. However, since the resistance of the resistor 2 is sufficiently larger than the on-resistance of the PMOS, NA
The voltage at the output terminal of the ND gate 3 is substantially equal to the power supply voltage 3V and attains the "H" level. Since the resistance value of the resistor 2 is sufficiently large, the current consumption is on the order of μA, which is smaller than the current consumption (4.2 mA) of the wireless unit 30.
The current consumption in the gate 3 does not matter. On the other hand, when the potential at the point a due to the AC signal is higher than the threshold level, the PMOS of the inverter is turned off, the NMOS is turned on, and the current flows through the resistor 2 and the output terminal of the NAND gate 3 to the ground of the NMOS. . The voltage at the output terminal of the NAND gate 3 is a value obtained by dividing the voltage by the on-resistance of the NMOS of the inverter and the resistor 2. Since the resistance of the resistor 2 is sufficiently larger than the on-resistance of the NMOS, the NAND gate 3 The voltage of the output terminal of No. 3 is substantially equal to the ground, and becomes “L” level.

Since the resistance value of the resistor 2 is sufficiently large, the current consumption is on the order of μA, and the current consumption in the NAND gate 3 does not matter as compared with the current consumption (4.2 mA) of the radio unit 30. . The output of NAND gate 3 is inverted by inverter 4 and
Is an in-phase output obtained by amplifying the output of the output buffer circuit 45 with a gain of 6. The output of inverter 4 is AND
The signal is input to one input terminal of the gate 5. Since the "H" level oscillation control signal is input to the other input terminal of the AND gate 5, the logic level of the output signal of the inverter 4 is output as it is. The AND gate 5 shapes the waveform of the rising and falling edges of the output signal of the inverter 5 and removes noise, and outputs a clock having an amplitude of 3.0 V _pp . Inverter 4 and AND gate 5
Is composed of CMOS, so that the current consumption does not matter even in these logic gates. The output signal of the AND gate 5 is output to the demodulation unit 80 of the LSI 60 in FIG.
Is input to The demodulation unit 80 generates a clock signal from the output signal of the AND gate 5 and outputs the clock signal to the control unit 90. The demodulation unit 80 also demodulates a demodulated detection output such as FSK modulation of the radio unit 30 from the clock signal into a digital signal. ,
Output to the control unit 90.

The control unit 90 synchronizes the frames,
The decoder 91 determines whether or not the user unique number set in the frame matches the one assigned to the pager receiver.
It returns to 0 and sounds the sounder 120 to indicate an incoming call. When the match signal is returned, the control unit 90 extracts the message from the frame, and sends the message to the CP via the CPU interface.
Output to U110. The CPU 110 controls the crystal unit 10
0 operates as a system clock, receives a message from the control unit 90, and receives a message from the LCD display unit 1.
30 is displayed. The control unit 90 controls the pager receiver 2
When the radio wave of the 80 MHz band is transmitted, the oscillation control signal is set to “H” level, otherwise, the oscillation control signal is set to “L” level and output to the oscillator output buffer circuit 70.

(B) When the oscillation control signal is at "L" level When the oscillation control signal is at "L" level, the NAND in FIG.
The output signal of the gate 3 becomes "H" level, the output signal of the inverter 4 becomes "L" level, the output signal of the AND gate 5 becomes "L" level, the clock output to the LSI 60 becomes "L" level, Since the level does not change, the current consumption of the LSI 60 is reduced. As described above, according to the present embodiment, the small-amplitude clock signal is constituted by the oscillator output buffer circuit using the low-current-consumption CMOS and the high-resistance resistor 2, so that
Since the amplification factor when the output of an oscillator such as a crystal oscillator having a small amplitude is once amplified by the output buffer circuit 45 can be suppressed, the current consumption in a pager receiver or the like can be reduced. For example, in this example, the current consumption of the output buffer circuit 45 can be set to 0.2 mA, and the current consumption can be reduced by 0.8 mA.

The present invention is not limited to the above embodiment, but can be variously modified. For example, there are the following modifications. (1) In the embodiment, the example in which the oscillator output buffer circuit is applied to the pager receiver has been described. However, the output signal of the oscillator such as the crystal oscillator having the low power supply voltage is converted to the L signal having the high power supply voltage.
The present invention can be applied to any case as long as it is transferred to the logic part of the SI. In this case, the NAND gate 3 is configured so that an intermediate value of the amplitude of the input signal becomes the threshold voltage, and the resistor 2 is configured so that the voltage of the output terminal becomes the “H” level or the “L” level. Good. (2) Although the configuration is such that the oscillation control signal is input to the NAND gate 3 and the AND gate 5, the oscillation control signal may not be input, but may be configured only by the inverter instead of the NAND gate 3.

[0027]

As described above in detail, according to the present invention, a small-amplitude clock signal is amplified by the oscillator output buffer circuit using CMOS with low current consumption, so that the small-amplitude clock signal is output. A circuit with low current consumption can be used in the circuit at the preceding stage, and the current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an oscillator output buffer circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a pager receiver using the oscillator output buffer circuit of FIG. 1;

FIG. 3 is a configuration diagram of a wireless unit 30 in FIG. 2;

FIG. 4 is a time chart of FIG. 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Capacitor 2 Resistance 3 NAND gate 4 Inverter 5 AND gate 10 Antenna 20 Battery 30 Radio part 33 Crystal oscillator 45 Output buffer circuit 50 Power supply part 60 LSI 70 Oscillator output buffer circuit 80 Demodulation part 90 Control part

Claims (1)

[Claims] 1. A capacitor to which an AC clock signal having a constant amplitude voltage is inputted to one electrode, a gate connected to the other electrode of the capacitor, a source connected to the first power supply voltage, and a drain connected A P-channel field-effect transistor connected to an output terminal; and a gate connected to the other electrode of the capacitor;
An N-channel field-effect transistor having a source connected to a second power supply voltage, connecting between the other electrode of the capacitor and the output terminal, and inputting the clock signal to the capacitor to form the P-channel The ON resistance of the P-channel field-effect transistor when the P-channel field-effect transistor is turned on, and the N-channel type when the N-channel field-effect transistor is turned on by the input of the clock signal to the capacitor. An oscillator output buffer circuit comprising: a resistor having a resistance value larger than the on-resistance of the field-effect transistor.