JPH10112511A - Semiconductor nonvolatile storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent metal wirings from breaking and improve the coverage of a layer insulation film by filling trenches of a semiconductor substrate with floating gates and control gates to reduce steps on the substrate. SOLUTION: Trenches 15 are formed in memory-forming regions of an Si semiconductor substrate 10, floating gates 3 composed of side walls are self- alignedly provided through a tunnel oxide film 2 on the side walls of the trenches 15. Source regions 1 are formed by a line-based resist pattern opened only at storage regions and source regions. Control gates 5 are buried through an insulation layer 8 between the floating gates 3 in the trenches 15 to form a select gate oxide film 9 on the control gates 5 and substrate surface and select gates 6 are provided thereon. In the bottoms of the trenches 15, drain regions 4 are formed by the gates 3 self-alignedly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory having a floating gate and, more particularly, to a semiconductor nonvolatile memory having a high degree of integration while preventing over-erasing at the time of erasing, and a method of manufacturing the same.

[0002]

2. Description of the Related Art An electrically rewritable and erasable semiconductor nonvolatile memory (hereinafter referred to as an EEPROM) or
In a batch erasure type electrically erasable and writable read-only semiconductor non-volatile memory (hereinafter, referred to as a flash memory), a problem of excessive erasing (overwriting) at the time of erasing becomes a problem. As a countermeasure against leakage at the time of reading due to over-erasing, there is a split gate type memory cell provided with a select gate (for example, see US Pat. No. 5,029,130).

On the other hand, Japanese Patent Application Laid-Open No. 6-163925 proposes a semiconductor non-volatile memory in which a planar area is reduced to achieve high integration. In this semiconductor nonvolatile memory, a trench is formed on the surface of a silicon substrate, a control gate is buried in the entire area of the trench, and a source is formed at the bottom of the trench. The channel is controlled to prevent over-erase. This eliminates the need for the select gate and reduces the planar area correspondingly.

Further, Japanese Patent Application Laid-Open Nos. 4-111470, 4-164372, and 62-15947
Japanese Patent Application Laid-open No. 2 discloses an ETOX type memory cell in which a floating gate and a control gate are embedded to reduce a step.

[0005]

However, in the above-mentioned conventional split gate type memory cell, the channel length of the select gate cannot be determined in a self-aligned manner. Is set, which hinders miniaturization of the cell.

Further, in the conventional split gate type memory cell, since the channel length of the split gate varies, there is also a problem that the cell current at the time of reading varies, causing deterioration of characteristics.

Further, in the conventional split gate type memory cell structure, since there is a multi-layer polysilicon structure in which two or three layers of polysilicon are stacked, a step in a chip is large, and exposure in a later step is performed. However, it is difficult to secure the depth of focus, and there is a problem in that the metal wiring becomes thinner, the wire breaks, the coverage of the passivation film deteriorates, and the reliability decreases.

In the method disclosed in Japanese Patent Application Laid-Open No. 6-163925, since the control gate is buried in the whole area of the trench, there is a problem that the cell area is increased and the degree of integration is reduced.

Further, Japanese Patent Application Laid-Open Nos. 4-111470, 4-164372, and 62-1
The memory cell disclosed in Japanese Patent No. 59472 does not solve the problem of over-erase.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is possible to determine a select gate channel length of a split gate memory cell without an overerasing problem without variation. Can,
It is another object of the present invention to provide a semiconductor non-volatile memory which can eliminate the steps such as disconnection of wiring in a later process and insufficient coverage of a protective film by eliminating steps in a chip.

[0011]

According to the present invention, there is provided a semiconductor nonvolatile memory, comprising: a trench formed in a semiconductor substrate; a floating gate comprising a sidewall formed on a side wall of the trench; and the floating gate in the trench. And a control gate embedded with an insulating layer interposed therebetween, a source region formed with the trench and a predetermined gate length, a drain region provided at the bottom of the trench, and an insulating layer on the substrate. And a select gate provided through the intermediary.

In the present invention, since the floating gate and the control gate are completely buried, the step on the substrate is small and there is no disconnection of the metal wiring. In addition, the coverage of the interlayer insulating film is good, and the reliability is improved.

Further, the present invention is characterized in that a pair of floating gates is provided on a side wall of the groove, and a memory area for 2 bits is formed in the groove.

As described above, by forming a memory area for two bits in one groove, the degree of integration is improved as compared with the case where a stacked memory cell is formed with the same bottom area. Further, the degree of integration is improved as compared to forming one memory cell with one groove.

Further, according to a method of manufacturing a semiconductor nonvolatile memory of the present invention, there is provided a method of forming a resist pattern in which only a memory region and a source region are formed on a surface of a semiconductor substrate, and forming the resist pattern as a mask over the entire surface of the substrate. Forming a conductive type impurity layer, forming a groove serving as a memory region in the semiconductor substrate, forming a sidewall serving as a floating gate on a side wall of the groove, and opening a portion of the groove. Forming a resist pattern,
Forming a one-conductivity-type impurity layer using the resist pattern as a mask, forming an oxide film on the sidewalls and the one-conductivity-type impurity layer, burying a control gate in the trench, and forming a select gate oxide film Forming a select gate on the surface of the substrate.

The manufacturing method of the present invention can be configured so that the positions of the source region and the memory region are determined by one photolithography, and the select gate channel length is determined in a self-aligned manner.

As described above, since the length of the select gate is formed in a self-aligned manner, the memory cell can be miniaturized, and the variation in characteristics between cells can be suppressed.

Further, according to the present invention, the floating gate can be formed on the groove side wall in a self-aligned manner.

Further, according to the present invention, after a polysilicon film is formed on the entire surface of the substrate by a chemical vapor deposition method, the control gate can be formed by performing etch-back.

Further, according to the present invention, a thick oxide film can be formed on the source and drain diffusion layers by accelerated oxidation.

As described above, by forming a thick oxide film, the parasitic capacitance between the source / select gate and the drain / control gate can be suppressed, and the speed can be improved.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a sectional view showing an embodiment of a semiconductor nonvolatile memory according to the present invention, and FIG.
FIG. 4 is a cross-sectional view showing the semiconductor nonvolatile memory of the present invention in the order of manufacturing steps.

As shown in FIG. 1, a silicon semiconductor substrate 1
A groove 15 is formed at a location to be a memory area of 0,
A floating gate 3 composed of a sidewall is provided on the side wall of the groove 15 in a self-aligned manner with a tunnel oxide film 2 interposed therebetween.

As will be described later, the source region 1 is formed by a line / space resist pattern in which only the memory region and the source region are opened. Therefore, the channel region of the select gate 6 is determined by the resist pattern. For example, in the case of the 0.35 μm rule, the source regions S, S and the channel regions C, C shown in FIG.
35 μm.

The floating gate 3 in the groove 15
A control gate 5 is buried between 3 via an insulating layer 8, a select gate oxide film 9 is formed on the control gate 5 and a select gate length portion of the substrate 10, and a select gate 6 is provided thereon. I have.

A drain region 4 is formed at the bottom of the groove 15 by the floating gates 3 and 3 in a self-aligned manner. Therefore, the gate length F and the drain region D of the floating gate 3
Will be determined by the side wall when forming.

Further, the source region 1 and the drain region 4
The upper oxide film forms a thick oxide film by accelerated oxidation.

As described above, since the floating gate 3 and the control gate 5 are buried in the silicon substrate 10, the step is only the select gate 6 and the field oxide film, and the step is smaller than that of the conventional EEPROM and flash memory. It is possible to prevent disconnection of the metal wiring on the interlayer insulating film formed on the select gate 6. Further, the problem of insufficient coverage of the interlayer insulating film is eliminated.

Since the select gate length is formed in a self-aligned manner, it is possible to miniaturize the memory cells, and it is possible to suppress variations in characteristics between the memory cells.

Since a 2-bit memory area is formed in one groove 15, the integration degree is improved as compared with the case where a stacked memory cell is formed with the same bottom area. Of course, the degree of integration is improved as compared to forming one memory cell with one groove.

Further, the parasitic capacitance between the source / select gate and the drain / control gate can be suppressed by the thick oxide film formed by the accelerated oxidation, and the speed can be improved.

Next, the manufacturing method of the present invention will be described with reference to FIG. 2A to 2G are cross-sectional views showing the manufacturing method according to the embodiment of the present invention step by step.

First, as shown in FIG.
After forming a field oxide film according to the process, buffer oxidation is performed on the entire surface of the silicon
50 Å silicon dioxide film (SiO ₂ )
11 is formed. Then, by photolithography, a resist pattern 12 of a line / space in which only the memory region and the source region are opened is formed. The channel region of the select gate is determined by the resist pattern 12. For example, in the case of the 0.35 μm rule, the source regions S and S and the channel regions C and C shown in FIG.

Subsequently, as shown in FIG.
Using the resist pattern 12 as a mask, an N-type impurity such as arsenic (As) is ion-implanted over the entire surface,
An N-type impurity layer 13 is formed.

Next, as shown in FIG. 2C, a resist 14 is formed by a double coating technique so as to cover the area other than the memory area. At this time, since the source region S and the channel region C have a width of about 0.35 μm, the alignment margin is sufficient. Then, the SiO ₂ film 11 at the opening of the resist 14 is removed, and a groove 15 is formed in the substrate 10 by silicon etching.

Thereafter, as shown in FIG. 2D, after removing the resists 12 and 14, the buffer oxide layer 11 is removed.
After pre-gate oxidation and removal of the oxide film, thermal oxidation
A tunnel oxide film 2 of 00 Å is formed.
At this time, the heat treatment activates the N-type impurity layer ion-implanted into the source region to form the source region 1, and the oxide film on the source region 1 is formed as a thick oxide film by accelerated oxidation. You. And on top of that LPCV
The first polysilicon film 16 is deposited by the D method or the like.

Next, as shown in FIG.
The entire surface is etched back to form a polysilicon sidewall on the sidewall of the groove 15. This sidewall becomes the floating gate 3. Then, a resist pattern 17 having a linear opening only in the memory region is formed, and an N-type impurity such as arsenic (As) is ion-implanted again using the resist pattern 17 as a mask over the entire surface of the substrate 10 to form a drain region. The N-type impurity layer 18 is formed at a location where
To form At this time, the misalignment of the photolithography is within 0.20 μm. Therefore, if the width (F) of the sidewall of the polysilicon is about 0.3 μm, there is no problem in manufacturing variation of the transistor.

Subsequently, after an oxide film is formed on the polysilicon sidewall 3 and the N-type impurity layer 18 by heat treatment, a second polysilicon film is deposited by CVD or the like, and the polysilicon side is deposited by etch back or the like. The polysilicon film other than the polysilicon 5 in the groove 15 sandwiched between the walls 3 and 3 is removed. Polysilicon 5 in groove 15
Becomes the control gate 5. The heat treatment activates the N-type impurity layer ion-implanted into the drain region to form the drain region 4, and the oxide film on the drain region 4 is formed as a thick oxide film by accelerated oxidation. .

Thereafter, the select gate oxide film is
A third polysilicon film is deposited thereon by CVD or the like, and a select gate (word line) 6 is patterned by photography and etching.

Thereafter, an interlayer insulating film and a metal wiring are formed in accordance with a normal process to obtain a semiconductor nonvolatile memory according to the present invention.

At this time, since the first polysilicon (floating gate 3) and the second polysilicon (control gate 5) are embedded in the silicon substrate 10, the steps after FIG. 3 polysilicon 3
(Select gate 6) and only the field oxide film,
The steps are smaller than those of the conventional EEPROM and flash memory, and disconnection of the metal wiring on the interlayer insulating film formed on the select gate 6 can be prevented. Further, the problem of insufficient coverage of the interlayer insulating film is eliminated.

[0042]

As described above, in the memory cell of the present invention, since the floating gate control gate is completely buried, the step on the substrate is small and there is no disconnection of the metal wiring. In addition, the coverage of the interlayer insulating film is good, and the reliability is improved.

Since the select gate length is formed in a self-aligned manner, memory cells can be miniaturized, and variations in characteristics between cells can be suppressed.

Since a 2-bit memory area is formed for one groove, the degree of integration is improved as compared with the case where a stacked memory cell is formed with the same bottom area. Further, the degree of integration is improved as compared to forming one memory cell with one groove.

The thick oxide film suppresses the parasitic capacitance between the source / select gate and the drain / control gate, thereby improving the speed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor nonvolatile memory of the present invention.

FIG. 2 is a sectional view showing a semiconductor nonvolatile memory according to the present invention in the order of manufacturing steps.

[Explanation of symbols]

 Reference Signs List 1 source region 3 floating gate 4 drain region 5 control gate 6 select gate

Claims (7)

[Claims] A floating gate comprising a trench formed in a semiconductor substrate, a sidewall formed on a side wall of the trench, a control gate embedded in the trench via the floating gate and an insulating layer; A source region formed with the trench and a predetermined gate length;
A non-volatile semiconductor memory, comprising: a drain region provided at a bottom of the groove; and a select gate provided on the substrate via an insulating layer. 2. The semiconductor nonvolatile memory according to claim 1, wherein a pair of floating gates is provided on a side wall of said groove, and a memory area for 2 bits is formed in said groove. Forming a resist pattern in which only a memory region and a source region are formed on the surface of the semiconductor substrate;
Forming a one-conductivity-type impurity layer on the entire surface of the substrate using a resist pattern as a mask, forming a groove to be a memory region in the semiconductor substrate, and forming a sidewall to be a floating gate on a side wall of the groove; Forming a resist pattern in which the groove portion is opened,
Forming a one-conductivity-type impurity layer using the resist pattern as a mask, forming an oxide film on the sidewalls and the one-conductivity-type impurity layer, burying a control gate in the trench, and forming a select gate oxide film Forming a select gate on the surface of the substrate after performing the method. 4. The method according to claim 3, wherein the positions of the source region and the memory region are determined by one photolithography, and the length of the select gate channel is determined in a self-aligned manner. 5. The method according to claim 3, wherein the floating gate is formed on the side wall of the groove in a self-aligned manner. 6. A control gate is formed by forming a polysilicon film over the entire surface of the substrate by a chemical vapor deposition method and then performing an etch back.
3. The method for manufacturing a semiconductor nonvolatile memory according to 1. 7. A thick oxide film is formed on the source and drain diffusion layers by accelerated oxidation.
3. The method for manufacturing a semiconductor nonvolatile memory according to 1.