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JPH038140B2 - - Google Patents

Info

Publication number
JPH038140B2
JPH038140B2 JP57120943A JP12094382A JPH038140B2 JP H038140 B2 JPH038140 B2 JP H038140B2 JP 57120943 A JP57120943 A JP 57120943A JP 12094382 A JP12094382 A JP 12094382A JP H038140 B2 JPH038140 B2 JP H038140B2
Authority
JP
Japan
Prior art keywords
metric
terminal
output
signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57120943A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5912649A (ja
Inventor
Yutaka Yasuda
Yasuo Hirata
Yukitsuna Furuya
Shuji Murakami
Katsuhiro Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
KDDI Corp
Original Assignee
Kokusai Denshin Denwa KK
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Denshin Denwa KK, Nippon Electric Co Ltd filed Critical Kokusai Denshin Denwa KK
Priority to JP57120943A priority Critical patent/JPS5912649A/ja
Publication of JPS5912649A publication Critical patent/JPS5912649A/ja
Publication of JPH038140B2 publication Critical patent/JPH038140B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Landscapes

  • Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP57120943A 1982-07-12 1982-07-12 ビタ−ビ復号器の同期回路 Granted JPS5912649A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57120943A JPS5912649A (ja) 1982-07-12 1982-07-12 ビタ−ビ復号器の同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57120943A JPS5912649A (ja) 1982-07-12 1982-07-12 ビタ−ビ復号器の同期回路

Publications (2)

Publication Number Publication Date
JPS5912649A JPS5912649A (ja) 1984-01-23
JPH038140B2 true JPH038140B2 (ko) 1991-02-05

Family

ID=14798803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57120943A Granted JPS5912649A (ja) 1982-07-12 1982-07-12 ビタ−ビ復号器の同期回路

Country Status (1)

Country Link
JP (1) JPS5912649A (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4802174A (en) * 1986-02-19 1989-01-31 Sony Corporation Viterbi decoder with detection of synchronous or asynchronous states
JP2768621B2 (ja) * 1993-06-25 1998-06-25 沖電気工業株式会社 分散送信される畳み込み符号の復号装置

Also Published As

Publication number Publication date
JPS5912649A (ja) 1984-01-23

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