JPH0358531B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which an etching means for forming a fine pattern is improved.

(Prior Art) In recent years, etching methods such as reactive ion etching that cause almost no side etching have been adopted for etching polycrystalline silicon gates.
However, this method has the disadvantage that there is no side etching in the overhang portion, and the polycrystalline silicon remains under the overhang portion. This will be explained below using as an example the manufacturing process of a MOS dynamic RAM having a two-layer polycrystalline silicon gate in the n-channel shown in FIGS. 3a to 3h.

First, a field oxide film 2 with a thickness of 7000 Å is formed on a p-type silicon substrate 1 having a (100) crystal plane by selective oxidation, and element regions 3 separated by the same oxide film 2 are formed (third (Figure a shown).

Next, thermal oxidation treatment is performed to form a first layer with a thickness of 300 Å.
After forming the gate oxide film 4, a thickness of 6000 Å is applied to the entire surface.
A phosphorus-doped polycrystalline silicon film is deposited. Subsequently, the polycrystalline silicon film is patterned by photolithography to form a first layer gate electrode 5, and then the oxide film 4 is removed by etching using the gate electrode 5 as a mask (as shown in FIG. 1B).

Then, for example, 100
Perform thermal oxidation for minutes. At this time, as shown in FIG.
However, on the exposed silicon substrate 1, for example, a thickness of
A thin oxide film 6' of 1200 Å is grown respectively. In addition, a first layer gate electrode 5 made of polycrystalline silicon
Since the lower surface of the stepped portion is also oxidized and an oxide film is grown, the ends of the electrode 5 are lifted up and overhangs 7, 7' are formed.

Next, the oxide film 6' on the silicon substrate 1 is etched away using, for example, an ammonium fluoride solution. At this time, as shown in Figure d, the oxide film 6 on the first layer gate electrode 5 made of polycrystalline silicon is also etched to a thickness of 2500 Å. Continuing, the same figure e
An oxide film 8 having a thickness of 600 Å was grown by performing thermal oxidation at 1000° C. as shown in FIG. Continuing,
Phosphorus-doped polycrystalline silicon film 9 with a thickness of 4000 Å on the entire surface
Deposit. At this time, the overhang portions 7 and 7' at the ends of the first layer gate electrode 5 are filled with the polycrystalline silicon film 9, as shown in FIG.

Next, a polycrystalline silicon film 9 is formed by photolithography.
is patterned to form a second layer gate electrode 10 in the memory cell portion, a gate electrode 10' in the peripheral circuit,
form respectively. At this time, an isotropic etching method (for example, plasma etching method) is used to etch the polycrystalline silicon film 9, and it is thoroughly etched so that the polycrystalline silicon portions of the overhang portions 7 and 7' are not left behind. to be removed. Thereafter, the oxide film 8 is etched using the gate electrodes 10, 10' as a mask to form a second layer in the memory cell area.
Gate oxide film 11, gate oxide film 1 on peripheral circuits
1' (shown in g of the same figure).

Hereinafter, according to a conventional method, an n ⁺ region 12 as a digital line is formed on the first part of the memory cell substrate, and an n ⁺ type source and drain region 1 is formed on the first part of the peripheral circuit substrate.
3 and 14, and further deposited a CVD-SiO ₂ film 15, a contact hole 16 is opened and the Al
A wiring 17 is formed to manufacture a MOS dynamic RAM (as shown in h of the same figure).

However, in the conventional method mentioned above, the second
In the isotropic etching for forming the gate electrode 10 and the gate electrode 10', the polycrystalline silicon film 9 is sufficiently overetched so that no polycrystalline silicon remains in the overhang parts 7 and 7'. The gate electrode 10' is also considerably overetched. As a result, the gate length became narrower, resulting in the problem of so-called short channel effect or punch-through phenomenon. In order to prevent this, it is necessary to increase the size of the resist during photolithography when forming the gate electrode 10', which hinders the integration of elements.

For this reason, known etching methods for polycrystalline silicon films, such as reactive ion etching, which have no or almost no side etching have been adopted, greatly contributing to the integration of devices.

However, in the process of manufacturing the dynamic RAM described above, when the second polycrystalline silicon film is etched by the reactive ion etching method, there is no side etching as shown in FIG. remains. A similar problem arises not only when overhanging structures but also when a film on a vertical or nearly vertical step is etched using the reactive ion etching method. That is, Figure 5a
After depositing the polycrystalline silicon film 20 on the vertical step portion 19 as shown in FIG.
Polycrystalline silicon 21 remains on the side surface of 9 without being etched.

On the other hand, as a technique for forming a fine pattern on a semiconductor substrate having a stepped portion, an invention disclosed in Japanese Patent Laid-Open No. 55-91130 is known. When selectively etching a film formed on the surface of a semiconductor substrate having a stepped portion, the present invention selectively etches the film in a direction perpendicular to an etching mask, and then etches the film remaining on the stepped portion. This is a method for manufacturing a semiconductor device in which a film formed by etching is etched in the same direction. However, in this method, a highly accurate pattern faithful to the mask is formed after selective etching in the vertical direction with respect to the mask, but the pattern under the mask is side-etched due to subsequent iso-directional etching. be done. In other words, the above method only eliminates the etching residue at the stepped portion, but the pattern is side-etched as in the case where only isodirectional etching is performed, making it difficult to form a highly accurate pattern.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned conventional problems, and is capable of preventing etching residues at overhang portions or step portions formed on a semiconductor substrate. , it is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a highly accurate coating pattern without side etching in areas other than the overhang portion or step portion.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a step of depositing a film on the entire surface of a semiconductor substrate, including an overhang portion or a stepped portion having nearly vertical side surfaces, and a step of forming a first mask material on the substrate so that the desired coating region where the overhang portion or step portion does not exist is exposed; After removing the first mask material, a second mask material is applied again onto the air plate containing the remaining coating at least on the overhang portion or step portion. forming a film pattern so that the remaining film region is exposed, and selectively etching the exposed remaining film region using the second mask material using isotropic or near-isotropic etching means to form a film pattern. A method of manufacturing a semiconductor device is characterized by comprising the steps of:

Examples of the above-mentioned film include a polycrystalline silicon film that becomes a gate electrode or wiring, an impurity-doped polycrystalline silicon film, a metal silicide film, or Al, Pt,
Metal films such as W, CVD-SiO ₂ films for interlayer insulation and passivation, phosphorus silicide glass (PSG)
film), silicon nitride film, alumina film, etc.

Examples of the mask material include a resist pattern, an insulating film pattern formed using the resist pattern, and the like.

Etching using gaseous ions incident substantially perpendicularly to the substrate is used to perform patterning faithful to the mask material without side etching. Examples of such etching means include reactive ion etching, reactive ion beam etching, and the like.

The above-mentioned isotropic or near-isotropic etching is used to pattern the remaining film without leaving any residue after selective etching with gaseous ions on the overhang or step portion. Examples of such etching means include wet etching, plasma etching, and the like.

(Function) According to the present invention, after forming a first mask material on a coating so that a desired coating region in which no overhang portion or step portion is present is exposed, the exposed coating is coated using the mask material. By selectively etching the region with gaseous ions incident in a direction substantially perpendicular to the substrate, patterning faithful to the first mask material without side etching is performed in regions other than the overhang portion or step portion. be able to. Subsequently, after removing the first mask material, a second mask material is again formed on the substrate including the remaining coating so that at least the remaining coating region on the overhang portion or the stepped portion is exposed. By selectively etching the exposed remaining film region using the second mask material using isotropic or near-isotropic etching means, no residual film remains on the over-angular portion or the stepped portion. Can be patterned. At this time, the film pattern on the area other than the overhang part or step part patterned by the etching using the gaseous ions and the etched surface formed by the same etching on the same area are covered with the second mask material. , it is possible to prevent side etching during isotropic or near-isotropic etching. Therefore, it is possible to prevent etching residue from remaining on the overhang or step portion formed on the semiconductor substrate, and to form a highly accurate coating pattern without side etching in areas other than the overhang or step portion. A highly integrated and highly reliable semiconductor device can be obtained.

(Embodiments of the Invention) Hereinafter, an example in which the present invention is applied to a MOS dynamic RAM having an n-channel two-layer polycrystalline silicon gate structure will be described with reference to FIGS. 1a to 1d.

First, p
A first layer gate electrode 5, an oxide film 6 as an interlayer insulating film, a second gate oxide film of the memory cell, and an oxide film 8 serving as the gate oxide film of the peripheral circuit are formed in the element region (memory cell part) of the type silicon substrate 1. A second phosphorus-doped polycrystalline silicon film 9 with a thickness of 4000 Å is formed.
Thereafter, resist films 22 ₁ and 22 ₂ were formed as a first mask material to cover the intended gate electrode portions of the memory cell portion and the peripheral circuit portion by photolithography (as shown in FIG. 1A). Subsequently, reactive ion etching was performed using these resist films 22 ₁ and 22 ₂ as masks. At this time, since reactive ion etching causes less side etching, the phosphorus-doped polycrystalline silicon film 9 is patterned as shown in _FIG . Ta.
Further, the polycrystalline silicon film 9' remained in the memory cell portion.

Next, after removing the resist films 22 ₁ and 22 ₂ , the second layer of the memory cell portion is again etched by photolithography.
Resist films 23 ₁ and 23 ₂ were formed as a second mask material to cover the intended layer gate electrode portion and the peripheral circuit portion (as shown in c in the same figure). At this time, the portions corresponding to the overhang portions 7 formed by the lifting of the ends of the first layer gate electrode 5 are resist films 23 ₁ , 23 _{2 .}
exposed from. Subsequently, the resist films 23 ₁ , 2
Using ₃₂ as a mask, the exposed remaining polycrystalline silicon film 9' was selectively etched with CF ₄ plasma gas. At this time, since the etching with the plasma gas is isotropic, the second layer gate electrode 10 was formed without any polycrystalline silicon remaining in the overhang portion 7, as shown in FIG. 4D. Note that since the peripheral circuit section is covered with a resist film ₂₃₂ ,
Gate electrode 10' already formed in the peripheral circuit section
is not etched.

Thereafter, after removing the resists 23 ₂ and 23 ₂ , a MOS dynamic RAM was manufactured according to the steps shown in FIGS. 3g and 3h described above.

Therefore, in this example, the second polycrystalline silicon film is formed using the first and second mask materials.
By employing reactive ion etching for selective etching with the second mask material and isotropic etching for selective etching with the second mask material, polycrystalline silicon is removed in the overhang portion of the memory cell area. In addition to eliminating etching residue, we were also able to form gate electrodes faithful to the mask without side etching in the peripheral circuit area, and we were able to obtain a highly integrated and highly reliable MOS dynamic RAM.

Note that the method of the present invention is not limited to the above-mentioned MOS dynamic RAM.
A covering pattern may be formed by the step of.

First, as shown in FIG. 2a, after depositing a polycrystalline silicon film 102 on the entire surface including the stepped portion 101,
By photolithography, a resist film 103 1 is used as a first mask material to cover a portion of the polycrystalline silicon film 102 near the stepped portion 101, and a resist film 103 ₁ is used as a first mask material to cover a portion of the polycrystalline silicon film 102 where the stepped portion 101 does not exist. A cyst pattern 103 ₂ was formed.

Then, using the resist films 103 ₁ and 103 ₂ as masks, the polycrystalline silicon film 102 was patterned by reactive ion etching.
At this time, the polycrystalline silicon films 104 ₁ , 104 ₂ faithful to the resist films 103 ₁ , 103 ₂ remain, and the stepped portion 101 where the resist film 103 ₁ is exposed
An etching residue 104 is formed on the polycrystalline silicon film 10 which is connected to the etching residue 104.
2' is formed, and a polycrystalline silicon pattern 105 ₁ faithful to the resist film 103 ₂ is formed on the region where the stepped portion 101 does not exist. Subsequently, the resist films 103 ₁ and 103 ₂ are removed, and the remaining polycrystalline silicon film 10 is etched again by photolithography.
A resist film 106 ₁ is used as a second mask material covering the end portion of the step portion 2′ in the direction of the stepped portion 101.
A resist film 106 ₂ was formed as a mask material covering the entire polycrystalline silicon pattern 105 ₁ (as shown in FIG. 1B).

Next, plasma etching was performed using the resist films 106 ₁ and 106 ₂ as masks. At this time, the remaining polycrystalline silicon film 102' exposed from the resist film 106 ₁ was patterned without leaving any etching residue on the stepped portion 101, and a polycrystalline silicon pattern 105 ₂ was formed. on the other hand,
Since the region covered with the resist film 106 ₂ was not etched, the polycrystalline silicon pattern 105 ₁ , which was entirely covered with the resist film 106 ₂ , was not etched and a highly accurate patterned state was maintained (as shown in c in the same figure). ).

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to prevent etching residues in overhang portions or step portions, and to prevent side etching in other areas, resulting in highly accurate and fine gate electrodes. It is possible to provide a method for manufacturing a semiconductor device that can form a film pattern such as wiring and achieves high reliability and high integration.

[Brief explanation of drawings]

Figures 1a to d are MOS in the embodiment of the present invention.
2A to 2C are plan views showing other embodiments of the present invention;
Figure 3 a to h are MOS dynamics using the conventional method.
FIG. 4 is a cross-sectional view showing the manufacturing process of RAM. FIG. b is a cross-sectional view showing a patterning process of a polycrystalline silicon film in a portion having a stepped portion, which is a problem with the conventional method. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 5... First layer gate electrode, 7, 7'... Overhang part, 9, 102... Polycrystalline silicon film, 10,... Second layer gate electrode, 10'... gate electrode, 12... n ⁺ diffusion layer, 13... n ⁺ type source region, 14... n ⁺ type drain region, 22 ₁ ,
22 ₂ , 23 ₁ , 23 ₂ , 103 ₁ , 103 ₂ , 106
₁ , 106 ₂ ... resist film, 101 ... step part,
105 ₁ , 105 ₂ ... Polycrystalline silicon pattern.

Claims (1)

[Scope of Claims] 1. A step of depositing a film over the entire surface of the semiconductor substrate, including an overhang or a step having a nearly vertical side surface, and applying a first mask material on the film to the overhang. Alternatively, a step of forming a desired coating region in which no step portion is present is exposed, and a step of selectively etching the exposed coating region using the mask material with gaseous ions that are incident approximately perpendicularly to the substrate. and after removing the first mask material, forming a second mask material again on the substrate including the remaining coating so that at least the remaining coating region on the overhang portion or the stepped portion is exposed. , a step of selectively etching the exposed remaining film region using the second mask material by isotropic or near-isotropic etching means to form a film pattern. manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the coating is made of polycrystalline silicon or metal silicide. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the overhang portion is formed by lifting the first layer gate electrode of the two-layer gate electrode structure.